1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Hanyi Wu <hanyi.wu@mediatek.com>
5 * Sascha Hauer <s.hauer@pengutronix.de>
6 * Dawei Chien <dawei.chien@mediatek.com>
7 * Louis Yu <louis.yu@mediatek.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/nvmem-consumer.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
21 #include <linux/io.h>
22 #include <linux/thermal.h>
23 #include <linux/reset.h>
24 #include <linux/types.h>
25
26 /* AUXADC Registers */
27 #define AUXADC_CON1_SET_V 0x008
28 #define AUXADC_CON1_CLR_V 0x00c
29 #define AUXADC_CON2_V 0x010
30 #define AUXADC_DATA(channel) (0x14 + (channel) * 4)
31
32 #define APMIXED_SYS_TS_CON1 0x604
33
34 /* Thermal Controller Registers */
35 #define TEMP_MONCTL0 0x000
36 #define TEMP_MONCTL1 0x004
37 #define TEMP_MONCTL2 0x008
38 #define TEMP_MONIDET0 0x014
39 #define TEMP_MONIDET1 0x018
40 #define TEMP_MSRCTL0 0x038
41 #define TEMP_AHBPOLL 0x040
42 #define TEMP_AHBTO 0x044
43 #define TEMP_ADCPNP0 0x048
44 #define TEMP_ADCPNP1 0x04c
45 #define TEMP_ADCPNP2 0x050
46 #define TEMP_ADCPNP3 0x0b4
47
48 #define TEMP_ADCMUX 0x054
49 #define TEMP_ADCEN 0x060
50 #define TEMP_PNPMUXADDR 0x064
51 #define TEMP_ADCMUXADDR 0x068
52 #define TEMP_ADCENADDR 0x074
53 #define TEMP_ADCVALIDADDR 0x078
54 #define TEMP_ADCVOLTADDR 0x07c
55 #define TEMP_RDCTRL 0x080
56 #define TEMP_ADCVALIDMASK 0x084
57 #define TEMP_ADCVOLTAGESHIFT 0x088
58 #define TEMP_ADCWRITECTRL 0x08c
59 #define TEMP_MSR0 0x090
60 #define TEMP_MSR1 0x094
61 #define TEMP_MSR2 0x098
62 #define TEMP_MSR3 0x0B8
63
64 #define TEMP_SPARE0 0x0f0
65
66 #define TEMP_ADCPNP0_1 0x148
67 #define TEMP_ADCPNP1_1 0x14c
68 #define TEMP_ADCPNP2_1 0x150
69 #define TEMP_MSR0_1 0x190
70 #define TEMP_MSR1_1 0x194
71 #define TEMP_MSR2_1 0x198
72 #define TEMP_ADCPNP3_1 0x1b4
73 #define TEMP_MSR3_1 0x1B8
74
75 #define PTPCORESEL 0x400
76
77 #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
78
79 #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
80 #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
81
82 #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
83
84 #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
85 #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
86
87 #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
88 #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
89
90 /* MT8173 thermal sensors */
91 #define MT8173_TS1 0
92 #define MT8173_TS2 1
93 #define MT8173_TS3 2
94 #define MT8173_TS4 3
95 #define MT8173_TSABB 4
96
97 /* AUXADC channel 11 is used for the temperature sensors */
98 #define MT8173_TEMP_AUXADC_CHANNEL 11
99
100 /* The total number of temperature sensors in the MT8173 */
101 #define MT8173_NUM_SENSORS 5
102
103 /* The number of banks in the MT8173 */
104 #define MT8173_NUM_ZONES 4
105
106 /* The number of sensing points per bank */
107 #define MT8173_NUM_SENSORS_PER_ZONE 4
108
109 /* The number of controller in the MT8173 */
110 #define MT8173_NUM_CONTROLLER 1
111
112 /* The calibration coefficient of sensor */
113 #define MT8173_CALIBRATION 165
114
115 /*
116 * Layout of the fuses providing the calibration data
117 * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
118 * MT8183 has 6 sensors and needs 6 VTS calibration data.
119 * MT8173 has 5 sensors and needs 5 VTS calibration data.
120 * MT2701 has 3 sensors and needs 3 VTS calibration data.
121 * MT2712 has 4 sensors and needs 4 VTS calibration data.
122 */
123 #define CALIB_BUF0_VALID BIT(0)
124 #define CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff)
125 #define CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff)
126 #define CALIB_BUF0_VTS_TS2(x) (((x) >> 8) & 0x1ff)
127 #define CALIB_BUF1_VTS_TS3(x) (((x) >> 0) & 0x1ff)
128 #define CALIB_BUF2_VTS_TS4(x) (((x) >> 23) & 0x1ff)
129 #define CALIB_BUF2_VTS_TS5(x) (((x) >> 5) & 0x1ff)
130 #define CALIB_BUF2_VTS_TSABB(x) (((x) >> 14) & 0x1ff)
131 #define CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f)
132 #define CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f)
133 #define CALIB_BUF0_O_SLOPE_SIGN(x) (((x) >> 7) & 0x1)
134 #define CALIB_BUF1_ID(x) (((x) >> 9) & 0x1)
135
136 enum {
137 VTS1,
138 VTS2,
139 VTS3,
140 VTS4,
141 VTS5,
142 VTSABB,
143 MAX_NUM_VTS,
144 };
145
146 /* MT2701 thermal sensors */
147 #define MT2701_TS1 0
148 #define MT2701_TS2 1
149 #define MT2701_TSABB 2
150
151 /* AUXADC channel 11 is used for the temperature sensors */
152 #define MT2701_TEMP_AUXADC_CHANNEL 11
153
154 /* The total number of temperature sensors in the MT2701 */
155 #define MT2701_NUM_SENSORS 3
156
157 /* The number of sensing points per bank */
158 #define MT2701_NUM_SENSORS_PER_ZONE 3
159
160 /* The number of controller in the MT2701 */
161 #define MT2701_NUM_CONTROLLER 1
162
163 /* The calibration coefficient of sensor */
164 #define MT2701_CALIBRATION 165
165
166 /* MT2712 thermal sensors */
167 #define MT2712_TS1 0
168 #define MT2712_TS2 1
169 #define MT2712_TS3 2
170 #define MT2712_TS4 3
171
172 /* AUXADC channel 11 is used for the temperature sensors */
173 #define MT2712_TEMP_AUXADC_CHANNEL 11
174
175 /* The total number of temperature sensors in the MT2712 */
176 #define MT2712_NUM_SENSORS 4
177
178 /* The number of sensing points per bank */
179 #define MT2712_NUM_SENSORS_PER_ZONE 4
180
181 /* The number of controller in the MT2712 */
182 #define MT2712_NUM_CONTROLLER 1
183
184 /* The calibration coefficient of sensor */
185 #define MT2712_CALIBRATION 165
186
187 #define MT7622_TEMP_AUXADC_CHANNEL 11
188 #define MT7622_NUM_SENSORS 1
189 #define MT7622_NUM_ZONES 1
190 #define MT7622_NUM_SENSORS_PER_ZONE 1
191 #define MT7622_TS1 0
192 #define MT7622_NUM_CONTROLLER 1
193
194 /* The maximum number of banks */
195 #define MAX_NUM_ZONES 8
196
197 /* The calibration coefficient of sensor */
198 #define MT7622_CALIBRATION 165
199
200 /* MT8183 thermal sensors */
201 #define MT8183_TS1 0
202 #define MT8183_TS2 1
203 #define MT8183_TS3 2
204 #define MT8183_TS4 3
205 #define MT8183_TS5 4
206 #define MT8183_TSABB 5
207
208 /* AUXADC channel is used for the temperature sensors */
209 #define MT8183_TEMP_AUXADC_CHANNEL 11
210
211 /* The total number of temperature sensors in the MT8183 */
212 #define MT8183_NUM_SENSORS 6
213
214 /* The number of banks in the MT8183 */
215 #define MT8183_NUM_ZONES 1
216
217 /* The number of sensing points per bank */
218 #define MT8183_NUM_SENSORS_PER_ZONE 6
219
220 /* The number of controller in the MT8183 */
221 #define MT8183_NUM_CONTROLLER 2
222
223 /* The calibration coefficient of sensor */
224 #define MT8183_CALIBRATION 153
225
226 struct mtk_thermal;
227
228 struct thermal_bank_cfg {
229 unsigned int num_sensors;
230 const int *sensors;
231 };
232
233 struct mtk_thermal_bank {
234 struct mtk_thermal *mt;
235 int id;
236 };
237
238 struct mtk_thermal_data {
239 s32 num_banks;
240 s32 num_sensors;
241 s32 auxadc_channel;
242 const int *vts_index;
243 const int *sensor_mux_values;
244 const int *msr;
245 const int *adcpnp;
246 const int cali_val;
247 const int num_controller;
248 const int *controller_offset;
249 bool need_switch_bank;
250 struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
251 };
252
253 struct mtk_thermal {
254 struct device *dev;
255 void __iomem *thermal_base;
256
257 struct clk *clk_peri_therm;
258 struct clk *clk_auxadc;
259 /* lock: for getting and putting banks */
260 struct mutex lock;
261
262 /* Calibration values */
263 s32 adc_ge;
264 s32 degc_cali;
265 s32 o_slope;
266 s32 vts[MAX_NUM_VTS];
267
268 const struct mtk_thermal_data *conf;
269 struct mtk_thermal_bank banks[MAX_NUM_ZONES];
270 };
271
272 /* MT8183 thermal sensor data */
273 static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
274 MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
275 };
276
277 static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
278 TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
279 };
280
281 static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
282 TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
283 TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
284 };
285
286 static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
287 static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
288
289 static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
290 VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
291 };
292
293 /* MT8173 thermal sensor data */
294 static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
295 { MT8173_TS2, MT8173_TS3 },
296 { MT8173_TS2, MT8173_TS4 },
297 { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
298 { MT8173_TS2 },
299 };
300
301 static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
302 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
303 };
304
305 static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
306 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
307 };
308
309 static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
310 static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
311
312 static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
313 VTS1, VTS2, VTS3, VTS4, VTSABB
314 };
315
316 /* MT2701 thermal sensor data */
317 static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
318 MT2701_TS1, MT2701_TS2, MT2701_TSABB
319 };
320
321 static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
322 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
323 };
324
325 static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
326 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
327 };
328
329 static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
330 static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
331
332 static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
333 VTS1, VTS2, VTS3
334 };
335
336 /* MT2712 thermal sensor data */
337 static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
338 MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
339 };
340
341 static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
342 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
343 };
344
345 static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
346 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
347 };
348
349 static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
350 static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
351
352 static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
353 VTS1, VTS2, VTS3, VTS4
354 };
355
356 /* MT7622 thermal sensor data */
357 static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
358 static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
359 static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
360 static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
361 static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
362 static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
363
364 /**
365 * The MT8173 thermal controller has four banks. Each bank can read up to
366 * four temperature sensors simultaneously. The MT8173 has a total of 5
367 * temperature sensors. We use each bank to measure a certain area of the
368 * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
369 * areas, hence is used in different banks.
370 *
371 * The thermal core only gets the maximum temperature of all banks, so
372 * the bank concept wouldn't be necessary here. However, the SVS (Smart
373 * Voltage Scaling) unit makes its decisions based on the same bank
374 * data, and this indeed needs the temperatures of the individual banks
375 * for making better decisions.
376 */
377 static const struct mtk_thermal_data mt8173_thermal_data = {
378 .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
379 .num_banks = MT8173_NUM_ZONES,
380 .num_sensors = MT8173_NUM_SENSORS,
381 .vts_index = mt8173_vts_index,
382 .cali_val = MT8173_CALIBRATION,
383 .num_controller = MT8173_NUM_CONTROLLER,
384 .controller_offset = mt8173_tc_offset,
385 .need_switch_bank = true,
386 .bank_data = {
387 {
388 .num_sensors = 2,
389 .sensors = mt8173_bank_data[0],
390 }, {
391 .num_sensors = 2,
392 .sensors = mt8173_bank_data[1],
393 }, {
394 .num_sensors = 3,
395 .sensors = mt8173_bank_data[2],
396 }, {
397 .num_sensors = 1,
398 .sensors = mt8173_bank_data[3],
399 },
400 },
401 .msr = mt8173_msr,
402 .adcpnp = mt8173_adcpnp,
403 .sensor_mux_values = mt8173_mux_values,
404 };
405
406 /**
407 * The MT2701 thermal controller has one bank, which can read up to
408 * three temperature sensors simultaneously. The MT2701 has a total of 3
409 * temperature sensors.
410 *
411 * The thermal core only gets the maximum temperature of this one bank,
412 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
413 * Voltage Scaling) unit makes its decisions based on the same bank
414 * data.
415 */
416 static const struct mtk_thermal_data mt2701_thermal_data = {
417 .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
418 .num_banks = 1,
419 .num_sensors = MT2701_NUM_SENSORS,
420 .vts_index = mt2701_vts_index,
421 .cali_val = MT2701_CALIBRATION,
422 .num_controller = MT2701_NUM_CONTROLLER,
423 .controller_offset = mt2701_tc_offset,
424 .need_switch_bank = true,
425 .bank_data = {
426 {
427 .num_sensors = 3,
428 .sensors = mt2701_bank_data,
429 },
430 },
431 .msr = mt2701_msr,
432 .adcpnp = mt2701_adcpnp,
433 .sensor_mux_values = mt2701_mux_values,
434 };
435
436 /**
437 * The MT2712 thermal controller has one bank, which can read up to
438 * four temperature sensors simultaneously. The MT2712 has a total of 4
439 * temperature sensors.
440 *
441 * The thermal core only gets the maximum temperature of this one bank,
442 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
443 * Voltage Scaling) unit makes its decisions based on the same bank
444 * data.
445 */
446 static const struct mtk_thermal_data mt2712_thermal_data = {
447 .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
448 .num_banks = 1,
449 .num_sensors = MT2712_NUM_SENSORS,
450 .vts_index = mt2712_vts_index,
451 .cali_val = MT2712_CALIBRATION,
452 .num_controller = MT2712_NUM_CONTROLLER,
453 .controller_offset = mt2712_tc_offset,
454 .need_switch_bank = true,
455 .bank_data = {
456 {
457 .num_sensors = 4,
458 .sensors = mt2712_bank_data,
459 },
460 },
461 .msr = mt2712_msr,
462 .adcpnp = mt2712_adcpnp,
463 .sensor_mux_values = mt2712_mux_values,
464 };
465
466 /*
467 * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
468 * access.
469 */
470 static const struct mtk_thermal_data mt7622_thermal_data = {
471 .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
472 .num_banks = MT7622_NUM_ZONES,
473 .num_sensors = MT7622_NUM_SENSORS,
474 .vts_index = mt7622_vts_index,
475 .cali_val = MT7622_CALIBRATION,
476 .num_controller = MT7622_NUM_CONTROLLER,
477 .controller_offset = mt7622_tc_offset,
478 .need_switch_bank = true,
479 .bank_data = {
480 {
481 .num_sensors = 1,
482 .sensors = mt7622_bank_data,
483 },
484 },
485 .msr = mt7622_msr,
486 .adcpnp = mt7622_adcpnp,
487 .sensor_mux_values = mt7622_mux_values,
488 };
489
490 /**
491 * The MT8183 thermal controller has one bank for the current SW framework.
492 * The MT8183 has a total of 6 temperature sensors.
493 * There are two thermal controller to control the six sensor.
494 * The first one bind 2 sensor, and the other bind 4 sensors.
495 * The thermal core only gets the maximum temperature of all sensor, so
496 * the bank concept wouldn't be necessary here. However, the SVS (Smart
497 * Voltage Scaling) unit makes its decisions based on the same bank
498 * data, and this indeed needs the temperatures of the individual banks
499 * for making better decisions.
500 */
501
502 static const struct mtk_thermal_data mt8183_thermal_data = {
503 .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
504 .num_banks = MT8183_NUM_ZONES,
505 .num_sensors = MT8183_NUM_SENSORS,
506 .vts_index = mt8183_vts_index,
507 .cali_val = MT8183_CALIBRATION,
508 .num_controller = MT8183_NUM_CONTROLLER,
509 .controller_offset = mt8183_tc_offset,
510 .need_switch_bank = false,
511 .bank_data = {
512 {
513 .num_sensors = 6,
514 .sensors = mt8183_bank_data,
515 },
516 },
517
518 .msr = mt8183_msr,
519 .adcpnp = mt8183_adcpnp,
520 .sensor_mux_values = mt8183_mux_values,
521 };
522
523 /**
524 * raw_to_mcelsius - convert a raw ADC value to mcelsius
525 * @mt: The thermal controller
526 * @raw: raw ADC value
527 *
528 * This converts the raw ADC value to mcelsius using the SoC specific
529 * calibration constants
530 */
raw_to_mcelsius(struct mtk_thermal * mt,int sensno,s32 raw)531 static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw)
532 {
533 s32 tmp;
534
535 raw &= 0xfff;
536
537 tmp = 203450520 << 3;
538 tmp /= mt->conf->cali_val + mt->o_slope;
539 tmp /= 10000 + mt->adc_ge;
540 tmp *= raw - mt->vts[sensno] - 3350;
541 tmp >>= 3;
542
543 return mt->degc_cali * 500 - tmp;
544 }
545
546 /**
547 * mtk_thermal_get_bank - get bank
548 * @bank: The bank
549 *
550 * The bank registers are banked, we have to select a bank in the
551 * PTPCORESEL register to access it.
552 */
mtk_thermal_get_bank(struct mtk_thermal_bank * bank)553 static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
554 {
555 struct mtk_thermal *mt = bank->mt;
556 u32 val;
557
558 if (mt->conf->need_switch_bank) {
559 mutex_lock(&mt->lock);
560
561 val = readl(mt->thermal_base + PTPCORESEL);
562 val &= ~0xf;
563 val |= bank->id;
564 writel(val, mt->thermal_base + PTPCORESEL);
565 }
566 }
567
568 /**
569 * mtk_thermal_put_bank - release bank
570 * @bank: The bank
571 *
572 * release a bank previously taken with mtk_thermal_get_bank,
573 */
mtk_thermal_put_bank(struct mtk_thermal_bank * bank)574 static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
575 {
576 struct mtk_thermal *mt = bank->mt;
577
578 if (mt->conf->need_switch_bank)
579 mutex_unlock(&mt->lock);
580 }
581
582 /**
583 * mtk_thermal_bank_temperature - get the temperature of a bank
584 * @bank: The bank
585 *
586 * The temperature of a bank is considered the maximum temperature of
587 * the sensors associated to the bank.
588 */
mtk_thermal_bank_temperature(struct mtk_thermal_bank * bank)589 static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
590 {
591 struct mtk_thermal *mt = bank->mt;
592 const struct mtk_thermal_data *conf = mt->conf;
593 int i, temp = INT_MIN, max = INT_MIN;
594 u32 raw;
595
596 for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
597 raw = readl(mt->thermal_base + conf->msr[i]);
598
599 temp = raw_to_mcelsius(mt,
600 conf->bank_data[bank->id].sensors[i],
601 raw);
602
603 /*
604 * The first read of a sensor often contains very high bogus
605 * temperature value. Filter these out so that the system does
606 * not immediately shut down.
607 */
608 if (temp > 200000)
609 temp = 0;
610
611 if (temp > max)
612 max = temp;
613 }
614
615 return max;
616 }
617
mtk_read_temp(void * data,int * temperature)618 static int mtk_read_temp(void *data, int *temperature)
619 {
620 struct mtk_thermal *mt = data;
621 int i;
622 int tempmax = INT_MIN;
623
624 for (i = 0; i < mt->conf->num_banks; i++) {
625 struct mtk_thermal_bank *bank = &mt->banks[i];
626
627 mtk_thermal_get_bank(bank);
628
629 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
630
631 mtk_thermal_put_bank(bank);
632 }
633
634 *temperature = tempmax;
635
636 return 0;
637 }
638
639 static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
640 .get_temp = mtk_read_temp,
641 };
642
mtk_thermal_init_bank(struct mtk_thermal * mt,int num,u32 apmixed_phys_base,u32 auxadc_phys_base,int ctrl_id)643 static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
644 u32 apmixed_phys_base, u32 auxadc_phys_base,
645 int ctrl_id)
646 {
647 struct mtk_thermal_bank *bank = &mt->banks[num];
648 const struct mtk_thermal_data *conf = mt->conf;
649 int i;
650
651 int offset = mt->conf->controller_offset[ctrl_id];
652 void __iomem *controller_base = mt->thermal_base + offset;
653
654 bank->id = num;
655 bank->mt = mt;
656
657 mtk_thermal_get_bank(bank);
658
659 /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
660 writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
661
662 /*
663 * filt interval is 1 * 46.540us = 46.54us,
664 * sen interval is 429 * 46.540us = 19.96ms
665 */
666 writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
667 TEMP_MONCTL2_SENSOR_INTERVAL(429),
668 controller_base + TEMP_MONCTL2);
669
670 /* poll is set to 10u */
671 writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
672 controller_base + TEMP_AHBPOLL);
673
674 /* temperature sampling control, 1 sample */
675 writel(0x0, controller_base + TEMP_MSRCTL0);
676
677 /* exceed this polling time, IRQ would be inserted */
678 writel(0xffffffff, controller_base + TEMP_AHBTO);
679
680 /* number of interrupts per event, 1 is enough */
681 writel(0x0, controller_base + TEMP_MONIDET0);
682 writel(0x0, controller_base + TEMP_MONIDET1);
683
684 /*
685 * The MT8173 thermal controller does not have its own ADC. Instead it
686 * uses AHB bus accesses to control the AUXADC. To do this the thermal
687 * controller has to be programmed with the physical addresses of the
688 * AUXADC registers and with the various bit positions in the AUXADC.
689 * Also the thermal controller controls a mux in the APMIXEDSYS register
690 * space.
691 */
692
693 /*
694 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
695 * automatically by hw
696 */
697 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
698
699 /* AHB address for auxadc mux selection */
700 writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
701 controller_base + TEMP_ADCMUXADDR);
702
703 /* AHB address for pnp sensor mux selection */
704 writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
705 controller_base + TEMP_PNPMUXADDR);
706
707 /* AHB value for auxadc enable */
708 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
709
710 /* AHB address for auxadc enable (channel 0 immediate mode selected) */
711 writel(auxadc_phys_base + AUXADC_CON1_SET_V,
712 controller_base + TEMP_ADCENADDR);
713
714 /* AHB address for auxadc valid bit */
715 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
716 controller_base + TEMP_ADCVALIDADDR);
717
718 /* AHB address for auxadc voltage output */
719 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
720 controller_base + TEMP_ADCVOLTADDR);
721
722 /* read valid & voltage are at the same register */
723 writel(0x0, controller_base + TEMP_RDCTRL);
724
725 /* indicate where the valid bit is */
726 writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
727 controller_base + TEMP_ADCVALIDMASK);
728
729 /* no shift */
730 writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
731
732 /* enable auxadc mux write transaction */
733 writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
734 controller_base + TEMP_ADCWRITECTRL);
735
736 for (i = 0; i < conf->bank_data[num].num_sensors; i++)
737 writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
738 mt->thermal_base + conf->adcpnp[i]);
739
740 writel((1 << conf->bank_data[num].num_sensors) - 1,
741 controller_base + TEMP_MONCTL0);
742
743 writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
744 TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
745 controller_base + TEMP_ADCWRITECTRL);
746
747 mtk_thermal_put_bank(bank);
748 }
749
of_get_phys_base(struct device_node * np)750 static u64 of_get_phys_base(struct device_node *np)
751 {
752 u64 size64;
753 const __be32 *regaddr_p;
754
755 regaddr_p = of_get_address(np, 0, &size64, NULL);
756 if (!regaddr_p)
757 return OF_BAD_ADDR;
758
759 return of_translate_address(np, regaddr_p);
760 }
761
mtk_thermal_get_calibration_data(struct device * dev,struct mtk_thermal * mt)762 static int mtk_thermal_get_calibration_data(struct device *dev,
763 struct mtk_thermal *mt)
764 {
765 struct nvmem_cell *cell;
766 u32 *buf;
767 size_t len;
768 int i, ret = 0;
769
770 /* Start with default values */
771 mt->adc_ge = 512;
772 for (i = 0; i < mt->conf->num_sensors; i++)
773 mt->vts[i] = 260;
774 mt->degc_cali = 40;
775 mt->o_slope = 0;
776
777 cell = nvmem_cell_get(dev, "calibration-data");
778 if (IS_ERR(cell)) {
779 if (PTR_ERR(cell) == -EPROBE_DEFER)
780 return PTR_ERR(cell);
781 return 0;
782 }
783
784 buf = (u32 *)nvmem_cell_read(cell, &len);
785
786 nvmem_cell_put(cell);
787
788 if (IS_ERR(buf))
789 return PTR_ERR(buf);
790
791 if (len < 3 * sizeof(u32)) {
792 dev_warn(dev, "invalid calibration data\n");
793 ret = -EINVAL;
794 goto out;
795 }
796
797 if (buf[0] & CALIB_BUF0_VALID) {
798 mt->adc_ge = CALIB_BUF1_ADC_GE(buf[1]);
799
800 for (i = 0; i < mt->conf->num_sensors; i++) {
801 switch (mt->conf->vts_index[i]) {
802 case VTS1:
803 mt->vts[VTS1] = CALIB_BUF0_VTS_TS1(buf[0]);
804 break;
805 case VTS2:
806 mt->vts[VTS2] = CALIB_BUF0_VTS_TS2(buf[0]);
807 break;
808 case VTS3:
809 mt->vts[VTS3] = CALIB_BUF1_VTS_TS3(buf[1]);
810 break;
811 case VTS4:
812 mt->vts[VTS4] = CALIB_BUF2_VTS_TS4(buf[2]);
813 break;
814 case VTS5:
815 mt->vts[VTS5] = CALIB_BUF2_VTS_TS5(buf[2]);
816 break;
817 case VTSABB:
818 mt->vts[VTSABB] = CALIB_BUF2_VTS_TSABB(buf[2]);
819 break;
820 default:
821 break;
822 }
823 }
824
825 mt->degc_cali = CALIB_BUF0_DEGC_CALI(buf[0]);
826 if (CALIB_BUF1_ID(buf[1]) &
827 CALIB_BUF0_O_SLOPE_SIGN(buf[0]))
828 mt->o_slope = -CALIB_BUF0_O_SLOPE(buf[0]);
829 else
830 mt->o_slope = CALIB_BUF0_O_SLOPE(buf[0]);
831 } else {
832 dev_info(dev, "Device not calibrated, using default calibration values\n");
833 }
834
835 out:
836 kfree(buf);
837
838 return ret;
839 }
840
841 static const struct of_device_id mtk_thermal_of_match[] = {
842 {
843 .compatible = "mediatek,mt8173-thermal",
844 .data = (void *)&mt8173_thermal_data,
845 },
846 {
847 .compatible = "mediatek,mt2701-thermal",
848 .data = (void *)&mt2701_thermal_data,
849 },
850 {
851 .compatible = "mediatek,mt2712-thermal",
852 .data = (void *)&mt2712_thermal_data,
853 },
854 {
855 .compatible = "mediatek,mt7622-thermal",
856 .data = (void *)&mt7622_thermal_data,
857 },
858 {
859 .compatible = "mediatek,mt8183-thermal",
860 .data = (void *)&mt8183_thermal_data,
861 }, {
862 },
863 };
864 MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
865
mtk_thermal_probe(struct platform_device * pdev)866 static int mtk_thermal_probe(struct platform_device *pdev)
867 {
868 int ret, i, ctrl_id;
869 struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
870 struct mtk_thermal *mt;
871 struct resource *res;
872 u64 auxadc_phys_base, apmixed_phys_base;
873 struct thermal_zone_device *tzdev;
874
875 mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
876 if (!mt)
877 return -ENOMEM;
878
879 mt->conf = of_device_get_match_data(&pdev->dev);
880
881 mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
882 if (IS_ERR(mt->clk_peri_therm))
883 return PTR_ERR(mt->clk_peri_therm);
884
885 mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
886 if (IS_ERR(mt->clk_auxadc))
887 return PTR_ERR(mt->clk_auxadc);
888
889 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
890 mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
891 if (IS_ERR(mt->thermal_base))
892 return PTR_ERR(mt->thermal_base);
893
894 ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
895 if (ret)
896 return ret;
897
898 mutex_init(&mt->lock);
899
900 mt->dev = &pdev->dev;
901
902 auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
903 if (!auxadc) {
904 dev_err(&pdev->dev, "missing auxadc node\n");
905 return -ENODEV;
906 }
907
908 auxadc_phys_base = of_get_phys_base(auxadc);
909
910 of_node_put(auxadc);
911
912 if (auxadc_phys_base == OF_BAD_ADDR) {
913 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
914 return -EINVAL;
915 }
916
917 apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
918 if (!apmixedsys) {
919 dev_err(&pdev->dev, "missing apmixedsys node\n");
920 return -ENODEV;
921 }
922
923 apmixed_phys_base = of_get_phys_base(apmixedsys);
924
925 of_node_put(apmixedsys);
926
927 if (apmixed_phys_base == OF_BAD_ADDR) {
928 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
929 return -EINVAL;
930 }
931
932 ret = device_reset(&pdev->dev);
933 if (ret)
934 return ret;
935
936 ret = clk_prepare_enable(mt->clk_auxadc);
937 if (ret) {
938 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
939 return ret;
940 }
941
942 ret = clk_prepare_enable(mt->clk_peri_therm);
943 if (ret) {
944 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
945 goto err_disable_clk_auxadc;
946 }
947
948 for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
949 for (i = 0; i < mt->conf->num_banks; i++)
950 mtk_thermal_init_bank(mt, i, apmixed_phys_base,
951 auxadc_phys_base, ctrl_id);
952
953 platform_set_drvdata(pdev, mt);
954
955 tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
956 &mtk_thermal_ops);
957 if (IS_ERR(tzdev)) {
958 ret = PTR_ERR(tzdev);
959 goto err_disable_clk_peri_therm;
960 }
961
962 return 0;
963
964 err_disable_clk_peri_therm:
965 clk_disable_unprepare(mt->clk_peri_therm);
966 err_disable_clk_auxadc:
967 clk_disable_unprepare(mt->clk_auxadc);
968
969 return ret;
970 }
971
mtk_thermal_remove(struct platform_device * pdev)972 static int mtk_thermal_remove(struct platform_device *pdev)
973 {
974 struct mtk_thermal *mt = platform_get_drvdata(pdev);
975
976 clk_disable_unprepare(mt->clk_peri_therm);
977 clk_disable_unprepare(mt->clk_auxadc);
978
979 return 0;
980 }
981
982 static struct platform_driver mtk_thermal_driver = {
983 .probe = mtk_thermal_probe,
984 .remove = mtk_thermal_remove,
985 .driver = {
986 .name = "mtk-thermal",
987 .of_match_table = mtk_thermal_of_match,
988 },
989 };
990
991 module_platform_driver(mtk_thermal_driver);
992
993 MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
994 MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
995 MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
996 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
997 MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
998 MODULE_DESCRIPTION("Mediatek thermal driver");
999 MODULE_LICENSE("GPL v2");
1000