1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2006, Intel Corporation.
4 *
5 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
6 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
7 */
8
9 #ifndef __DMAR_H__
10 #define __DMAR_H__
11
12 #include <linux/acpi.h>
13 #include <linux/types.h>
14 #include <linux/msi.h>
15 #include <linux/irqreturn.h>
16 #include <linux/rwsem.h>
17 #include <linux/rculist.h>
18
19 struct acpi_dmar_header;
20
21 #ifdef CONFIG_X86
22 # define DMAR_UNITS_SUPPORTED MAX_IO_APICS
23 #else
24 # define DMAR_UNITS_SUPPORTED 64
25 #endif
26
27 /* DMAR Flags */
28 #define DMAR_INTR_REMAP 0x1
29 #define DMAR_X2APIC_OPT_OUT 0x2
30 #define DMAR_PLATFORM_OPT_IN 0x4
31
32 struct intel_iommu;
33
34 struct dmar_dev_scope {
35 struct device __rcu *dev;
36 u8 bus;
37 u8 devfn;
38 };
39
40 #ifdef CONFIG_DMAR_TABLE
41 extern struct acpi_table_header *dmar_tbl;
42 struct dmar_drhd_unit {
43 struct list_head list; /* list of drhd units */
44 struct acpi_dmar_header *hdr; /* ACPI header */
45 u64 reg_base_addr; /* register base address*/
46 struct dmar_dev_scope *devices;/* target device array */
47 int devices_cnt; /* target device count */
48 u16 segment; /* PCI domain */
49 u8 ignored:1; /* ignore drhd */
50 u8 include_all:1;
51 struct intel_iommu *iommu;
52 };
53
54 struct dmar_pci_path {
55 u8 bus;
56 u8 device;
57 u8 function;
58 };
59
60 struct dmar_pci_notify_info {
61 struct pci_dev *dev;
62 unsigned long event;
63 int bus;
64 u16 seg;
65 u16 level;
66 struct dmar_pci_path path[];
67 } __attribute__((packed));
68
69 extern struct rw_semaphore dmar_global_lock;
70 extern struct list_head dmar_drhd_units;
71
72 #define for_each_drhd_unit(drhd) \
73 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
74 dmar_rcu_check())
75
76 #define for_each_active_drhd_unit(drhd) \
77 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
78 dmar_rcu_check()) \
79 if (drhd->ignored) {} else
80
81 #define for_each_active_iommu(i, drhd) \
82 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
83 dmar_rcu_check()) \
84 if (i=drhd->iommu, drhd->ignored) {} else
85
86 #define for_each_iommu(i, drhd) \
87 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
88 dmar_rcu_check()) \
89 if (i=drhd->iommu, 0) {} else
90
dmar_rcu_check(void)91 static inline bool dmar_rcu_check(void)
92 {
93 return rwsem_is_locked(&dmar_global_lock) ||
94 system_state == SYSTEM_BOOTING;
95 }
96
97 #define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check())
98
99 #define for_each_dev_scope(devs, cnt, i, tmp) \
100 for ((i) = 0; ((tmp) = (i) < (cnt) ? \
101 dmar_rcu_dereference((devs)[(i)].dev) : NULL, (i) < (cnt)); \
102 (i)++)
103
104 #define for_each_active_dev_scope(devs, cnt, i, tmp) \
105 for_each_dev_scope((devs), (cnt), (i), (tmp)) \
106 if (!(tmp)) { continue; } else
107
108 extern int dmar_table_init(void);
109 extern int dmar_dev_scope_init(void);
110 extern void dmar_register_bus_notifier(void);
111 extern int dmar_parse_dev_scope(void *start, void *end, int *cnt,
112 struct dmar_dev_scope **devices, u16 segment);
113 extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt);
114 extern void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt);
115 extern int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
116 void *start, void*end, u16 segment,
117 struct dmar_dev_scope *devices,
118 int devices_cnt);
119 extern int dmar_remove_dev_scope(struct dmar_pci_notify_info *info,
120 u16 segment, struct dmar_dev_scope *devices,
121 int count);
122 /* Intel IOMMU detection */
123 extern int detect_intel_iommu(void);
124 extern int enable_drhd_fault_handling(void);
125 extern int dmar_device_add(acpi_handle handle);
126 extern int dmar_device_remove(acpi_handle handle);
127
dmar_res_noop(struct acpi_dmar_header * hdr,void * arg)128 static inline int dmar_res_noop(struct acpi_dmar_header *hdr, void *arg)
129 {
130 return 0;
131 }
132
133 #ifdef CONFIG_INTEL_IOMMU
134 extern int iommu_detected, no_iommu;
135 extern int intel_iommu_init(void);
136 extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg);
137 extern int dmar_parse_one_atsr(struct acpi_dmar_header *header, void *arg);
138 extern int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg);
139 extern int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg);
140 extern int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert);
141 extern int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info);
142 #else /* !CONFIG_INTEL_IOMMU: */
intel_iommu_init(void)143 static inline int intel_iommu_init(void) { return -ENODEV; }
144
145 #define dmar_parse_one_rmrr dmar_res_noop
146 #define dmar_parse_one_atsr dmar_res_noop
147 #define dmar_check_one_atsr dmar_res_noop
148 #define dmar_release_one_atsr dmar_res_noop
149
dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info * info)150 static inline int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
151 {
152 return 0;
153 }
154
dmar_iommu_hotplug(struct dmar_drhd_unit * dmaru,bool insert)155 static inline int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
156 {
157 return 0;
158 }
159 #endif /* CONFIG_INTEL_IOMMU */
160
161 #ifdef CONFIG_IRQ_REMAP
162 extern int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert);
163 #else /* CONFIG_IRQ_REMAP */
dmar_ir_hotplug(struct dmar_drhd_unit * dmaru,bool insert)164 static inline int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
165 { return 0; }
166 #endif /* CONFIG_IRQ_REMAP */
167
168 extern bool dmar_platform_optin(void);
169
170 #else /* CONFIG_DMAR_TABLE */
171
dmar_device_add(void * handle)172 static inline int dmar_device_add(void *handle)
173 {
174 return 0;
175 }
176
dmar_device_remove(void * handle)177 static inline int dmar_device_remove(void *handle)
178 {
179 return 0;
180 }
181
dmar_platform_optin(void)182 static inline bool dmar_platform_optin(void)
183 {
184 return false;
185 }
186
187 #endif /* CONFIG_DMAR_TABLE */
188
189 struct irte {
190 union {
191 /* Shared between remapped and posted mode*/
192 struct {
193 __u64 present : 1, /* 0 */
194 fpd : 1, /* 1 */
195 __res0 : 6, /* 2 - 6 */
196 avail : 4, /* 8 - 11 */
197 __res1 : 3, /* 12 - 14 */
198 pst : 1, /* 15 */
199 vector : 8, /* 16 - 23 */
200 __res2 : 40; /* 24 - 63 */
201 };
202
203 /* Remapped mode */
204 struct {
205 __u64 r_present : 1, /* 0 */
206 r_fpd : 1, /* 1 */
207 dst_mode : 1, /* 2 */
208 redir_hint : 1, /* 3 */
209 trigger_mode : 1, /* 4 */
210 dlvry_mode : 3, /* 5 - 7 */
211 r_avail : 4, /* 8 - 11 */
212 r_res0 : 4, /* 12 - 15 */
213 r_vector : 8, /* 16 - 23 */
214 r_res1 : 8, /* 24 - 31 */
215 dest_id : 32; /* 32 - 63 */
216 };
217
218 /* Posted mode */
219 struct {
220 __u64 p_present : 1, /* 0 */
221 p_fpd : 1, /* 1 */
222 p_res0 : 6, /* 2 - 7 */
223 p_avail : 4, /* 8 - 11 */
224 p_res1 : 2, /* 12 - 13 */
225 p_urgent : 1, /* 14 */
226 p_pst : 1, /* 15 */
227 p_vector : 8, /* 16 - 23 */
228 p_res2 : 14, /* 24 - 37 */
229 pda_l : 26; /* 38 - 63 */
230 };
231 __u64 low;
232 };
233
234 union {
235 /* Shared between remapped and posted mode*/
236 struct {
237 __u64 sid : 16, /* 64 - 79 */
238 sq : 2, /* 80 - 81 */
239 svt : 2, /* 82 - 83 */
240 __res3 : 44; /* 84 - 127 */
241 };
242
243 /* Posted mode*/
244 struct {
245 __u64 p_sid : 16, /* 64 - 79 */
246 p_sq : 2, /* 80 - 81 */
247 p_svt : 2, /* 82 - 83 */
248 p_res3 : 12, /* 84 - 95 */
249 pda_h : 32; /* 96 - 127 */
250 };
251 __u64 high;
252 };
253 };
254
dmar_copy_shared_irte(struct irte * dst,struct irte * src)255 static inline void dmar_copy_shared_irte(struct irte *dst, struct irte *src)
256 {
257 dst->present = src->present;
258 dst->fpd = src->fpd;
259 dst->avail = src->avail;
260 dst->pst = src->pst;
261 dst->vector = src->vector;
262 dst->sid = src->sid;
263 dst->sq = src->sq;
264 dst->svt = src->svt;
265 }
266
267 #define PDA_LOW_BIT 26
268 #define PDA_HIGH_BIT 32
269
270 /* Can't use the common MSI interrupt functions
271 * since DMAR is not a pci device
272 */
273 struct irq_data;
274 extern void dmar_msi_unmask(struct irq_data *data);
275 extern void dmar_msi_mask(struct irq_data *data);
276 extern void dmar_msi_read(int irq, struct msi_msg *msg);
277 extern void dmar_msi_write(int irq, struct msi_msg *msg);
278 extern int dmar_set_interrupt(struct intel_iommu *iommu);
279 extern irqreturn_t dmar_fault(int irq, void *dev_id);
280 extern int dmar_alloc_hwirq(int id, int node, void *arg);
281 extern void dmar_free_hwirq(int irq);
282
283 #endif /* __DMAR_H__ */
284