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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-1012A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 *
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/thermal/thermal.h>
11
12/ {
13	compatible = "fsl,ls1012a";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	aliases {
19		crypto = &crypto;
20		rtic-a = &rtic_a;
21		rtic-b = &rtic_b;
22		rtic-c = &rtic_c;
23		rtic-d = &rtic_d;
24		sec-mon = &sec_mon;
25	};
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		cpu0: cpu@0 {
32			device_type = "cpu";
33			compatible = "arm,cortex-a53";
34			reg = <0x0>;
35			clocks = <&clockgen 1 0>;
36			#cooling-cells = <2>;
37			cpu-idle-states = <&CPU_PH20>;
38		};
39	};
40
41	idle-states {
42		/*
43		 * PSCI node is not added default, U-boot will add missing
44		 * parts if it determines to use PSCI.
45		 */
46		entry-method = "psci";
47
48		CPU_PH20: cpu-ph20 {
49			compatible = "arm,idle-state";
50			idle-state-name = "PH20";
51			arm,psci-suspend-param = <0x0>;
52			entry-latency-us = <1000>;
53			exit-latency-us = <1000>;
54			min-residency-us = <3000>;
55		};
56	};
57
58	sysclk: sysclk {
59		compatible = "fixed-clock";
60		#clock-cells = <0>;
61		clock-frequency = <125000000>;
62		clock-output-names = "sysclk";
63	};
64
65	coreclk: coreclk {
66		compatible = "fixed-clock";
67		#clock-cells = <0>;
68		clock-frequency = <100000000>;
69		clock-output-names = "coreclk";
70	};
71
72	timer {
73		compatible = "arm,armv8-timer";
74		interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
75			     <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
76			     <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
77			     <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
78	};
79
80	pmu {
81		compatible = "arm,armv8-pmuv3";
82		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
83	};
84
85	gic: interrupt-controller@1400000 {
86		compatible = "arm,gic-400";
87		#interrupt-cells = <3>;
88		interrupt-controller;
89		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
90		      <0x0 0x1402000 0 0x2000>, /* GICC */
91		      <0x0 0x1404000 0 0x2000>, /* GICH */
92		      <0x0 0x1406000 0 0x2000>; /* GICV */
93		interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
94	};
95
96	reboot {
97		compatible = "syscon-reboot";
98		regmap = <&dcfg>;
99		offset = <0xb0>;
100		mask = <0x02>;
101	};
102
103	thermal-zones {
104		cpu_thermal: cpu-thermal {
105			polling-delay-passive = <1000>;
106			polling-delay = <5000>;
107			thermal-sensors = <&tmu 0>;
108
109			trips {
110				cpu_alert: cpu-alert {
111					temperature = <85000>;
112					hysteresis = <2000>;
113					type = "passive";
114				};
115
116				cpu_crit: cpu-crit {
117					temperature = <95000>;
118					hysteresis = <2000>;
119					type = "critical";
120				};
121			};
122
123			cooling-maps {
124				map0 {
125					trip = <&cpu_alert>;
126					cooling-device =
127						<&cpu0 THERMAL_NO_LIMIT
128						THERMAL_NO_LIMIT>;
129				};
130			};
131		};
132	};
133
134	soc {
135		compatible = "simple-bus";
136		#address-cells = <2>;
137		#size-cells = <2>;
138		ranges;
139
140		esdhc0: esdhc@1560000 {
141			compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
142			reg = <0x0 0x1560000 0x0 0x10000>;
143			interrupts = <0 62 0x4>;
144			clocks = <&clockgen 4 0>;
145			voltage-ranges = <1800 1800 3300 3300>;
146			sdhci,auto-cmd12;
147			big-endian;
148			bus-width = <4>;
149			status = "disabled";
150		};
151
152		scfg: scfg@1570000 {
153			compatible = "fsl,ls1012a-scfg", "syscon";
154			reg = <0x0 0x1570000 0x0 0x10000>;
155			big-endian;
156		};
157
158		esdhc1: esdhc@1580000 {
159			compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
160			reg = <0x0 0x1580000 0x0 0x10000>;
161			interrupts = <0 65 0x4>;
162			clocks = <&clockgen 4 0>;
163			voltage-ranges = <1800 1800 3300 3300>;
164			sdhci,auto-cmd12;
165			big-endian;
166			broken-cd;
167			bus-width = <4>;
168			status = "disabled";
169		};
170
171		crypto: crypto@1700000 {
172			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
173				     "fsl,sec-v4.0";
174			fsl,sec-era = <8>;
175			#address-cells = <1>;
176			#size-cells = <1>;
177			ranges = <0x0 0x00 0x1700000 0x100000>;
178			reg = <0x00 0x1700000 0x0 0x100000>;
179			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
180			dma-coherent;
181
182			sec_jr0: jr@10000 {
183				compatible = "fsl,sec-v5.4-job-ring",
184					     "fsl,sec-v5.0-job-ring",
185					     "fsl,sec-v4.0-job-ring";
186				reg	   = <0x10000 0x10000>;
187				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
188			};
189
190			sec_jr1: jr@20000 {
191				compatible = "fsl,sec-v5.4-job-ring",
192					     "fsl,sec-v5.0-job-ring",
193					     "fsl,sec-v4.0-job-ring";
194				reg	   = <0x20000 0x10000>;
195				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
196			};
197
198			sec_jr2: jr@30000 {
199				compatible = "fsl,sec-v5.4-job-ring",
200					     "fsl,sec-v5.0-job-ring",
201					     "fsl,sec-v4.0-job-ring";
202				reg	   = <0x30000 0x10000>;
203				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
204			};
205
206			sec_jr3: jr@40000 {
207				compatible = "fsl,sec-v5.4-job-ring",
208					     "fsl,sec-v5.0-job-ring",
209					     "fsl,sec-v4.0-job-ring";
210				reg	   = <0x40000 0x10000>;
211				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
212			};
213
214			rtic@60000 {
215				compatible = "fsl,sec-v5.4-rtic",
216					     "fsl,sec-v5.0-rtic",
217					     "fsl,sec-v4.0-rtic";
218				#address-cells = <1>;
219				#size-cells = <1>;
220				reg = <0x60000 0x100 0x60e00 0x18>;
221				ranges = <0x0 0x60100 0x500>;
222
223				rtic_a: rtic-a@0 {
224					compatible = "fsl,sec-v5.4-rtic-memory",
225						     "fsl,sec-v5.0-rtic-memory",
226						     "fsl,sec-v4.0-rtic-memory";
227					reg = <0x00 0x20 0x100 0x100>;
228				};
229
230				rtic_b: rtic-b@20 {
231					compatible = "fsl,sec-v5.4-rtic-memory",
232						     "fsl,sec-v5.0-rtic-memory",
233						     "fsl,sec-v4.0-rtic-memory";
234					reg = <0x20 0x20 0x200 0x100>;
235				};
236
237				rtic_c: rtic-c@40 {
238					compatible = "fsl,sec-v5.4-rtic-memory",
239						     "fsl,sec-v5.0-rtic-memory",
240						     "fsl,sec-v4.0-rtic-memory";
241					reg = <0x40 0x20 0x300 0x100>;
242				};
243
244				rtic_d: rtic-d@60 {
245					compatible = "fsl,sec-v5.4-rtic-memory",
246						     "fsl,sec-v5.0-rtic-memory",
247						     "fsl,sec-v4.0-rtic-memory";
248					reg = <0x60 0x20 0x400 0x100>;
249				};
250			};
251		};
252
253		sec_mon: sec_mon@1e90000 {
254			compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
255				     "fsl,sec-v4.0-mon";
256			reg = <0x0 0x1e90000 0x0 0x10000>;
257			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
258				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
259		};
260
261		dcfg: dcfg@1ee0000 {
262			compatible = "fsl,ls1012a-dcfg",
263				     "syscon";
264			reg = <0x0 0x1ee0000 0x0 0x10000>;
265			big-endian;
266		};
267
268		clockgen: clocking@1ee1000 {
269			compatible = "fsl,ls1012a-clockgen";
270			reg = <0x0 0x1ee1000 0x0 0x1000>;
271			#clock-cells = <2>;
272			clocks = <&sysclk &coreclk>;
273			clock-names = "sysclk", "coreclk";
274		};
275
276		tmu: tmu@1f00000 {
277			compatible = "fsl,qoriq-tmu";
278			reg = <0x0 0x1f00000 0x0 0x10000>;
279			interrupts = <0 33 0x4>;
280			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
281			fsl,tmu-calibration = <0x00000000 0x00000026
282					       0x00000001 0x0000002d
283					       0x00000002 0x00000032
284					       0x00000003 0x00000039
285					       0x00000004 0x0000003f
286					       0x00000005 0x00000046
287					       0x00000006 0x0000004d
288					       0x00000007 0x00000054
289					       0x00000008 0x0000005a
290					       0x00000009 0x00000061
291					       0x0000000a 0x0000006a
292					       0x0000000b 0x00000071
293
294					       0x00010000 0x00000025
295					       0x00010001 0x0000002c
296					       0x00010002 0x00000035
297					       0x00010003 0x0000003d
298					       0x00010004 0x00000045
299					       0x00010005 0x0000004e
300					       0x00010006 0x00000057
301					       0x00010007 0x00000061
302					       0x00010008 0x0000006b
303					       0x00010009 0x00000076
304
305					       0x00020000 0x00000029
306					       0x00020001 0x00000033
307					       0x00020002 0x0000003d
308					       0x00020003 0x00000049
309					       0x00020004 0x00000056
310					       0x00020005 0x00000061
311					       0x00020006 0x0000006d
312
313					       0x00030000 0x00000021
314					       0x00030001 0x0000002a
315					       0x00030002 0x0000003c
316					       0x00030003 0x0000004e>;
317			big-endian;
318			#thermal-sensor-cells = <1>;
319		};
320
321		i2c0: i2c@2180000 {
322			compatible = "fsl,vf610-i2c";
323			#address-cells = <1>;
324			#size-cells = <0>;
325			reg = <0x0 0x2180000 0x0 0x10000>;
326			interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
327			clocks = <&clockgen 4 3>;
328			status = "disabled";
329		};
330
331		i2c1: i2c@2190000 {
332			compatible = "fsl,vf610-i2c";
333			#address-cells = <1>;
334			#size-cells = <0>;
335			reg = <0x0 0x2190000 0x0 0x10000>;
336			interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
337			clocks = <&clockgen 4 3>;
338			status = "disabled";
339		};
340
341		dspi: spi@2100000 {
342			compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
343			#address-cells = <1>;
344			#size-cells = <0>;
345			reg = <0x0 0x2100000 0x0 0x10000>;
346			interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
347			clock-names = "dspi";
348			clocks = <&clockgen 4 0>;
349			spi-num-chipselects = <5>;
350			big-endian;
351			status = "disabled";
352		};
353
354		duart0: serial@21c0500 {
355			compatible = "fsl,ns16550", "ns16550a";
356			reg = <0x00 0x21c0500 0x0 0x100>;
357			interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
358			clocks = <&clockgen 4 0>;
359			status = "disabled";
360		};
361
362		duart1: serial@21c0600 {
363			compatible = "fsl,ns16550", "ns16550a";
364			reg = <0x00 0x21c0600 0x0 0x100>;
365			interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
366			clocks = <&clockgen 4 0>;
367			status = "disabled";
368		};
369
370		gpio0: gpio@2300000 {
371			compatible = "fsl,qoriq-gpio";
372			reg = <0x0 0x2300000 0x0 0x10000>;
373			interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
374			gpio-controller;
375			#gpio-cells = <2>;
376			interrupt-controller;
377			#interrupt-cells = <2>;
378		};
379
380		gpio1: gpio@2310000 {
381			compatible = "fsl,qoriq-gpio";
382			reg = <0x0 0x2310000 0x0 0x10000>;
383			interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
384			gpio-controller;
385			#gpio-cells = <2>;
386			interrupt-controller;
387			#interrupt-cells = <2>;
388		};
389
390		wdog0: wdog@2ad0000 {
391			compatible = "fsl,ls1012a-wdt",
392				     "fsl,imx21-wdt";
393			reg = <0x0 0x2ad0000 0x0 0x10000>;
394			interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
395			clocks = <&clockgen 4 0>;
396			big-endian;
397		};
398
399		sai1: sai@2b50000 {
400			#sound-dai-cells = <0>;
401			compatible = "fsl,vf610-sai";
402			reg = <0x0 0x2b50000 0x0 0x10000>;
403			interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
404			clocks = <&clockgen 4 3>, <&clockgen 4 3>,
405				 <&clockgen 4 3>, <&clockgen 4 3>;
406			clock-names = "bus", "mclk1", "mclk2", "mclk3";
407			dma-names = "tx", "rx";
408			dmas = <&edma0 1 47>,
409			       <&edma0 1 46>;
410			status = "disabled";
411		};
412
413		sai2: sai@2b60000 {
414			#sound-dai-cells = <0>;
415			compatible = "fsl,vf610-sai";
416			reg = <0x0 0x2b60000 0x0 0x10000>;
417			interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
418			clocks = <&clockgen 4 3>, <&clockgen 4 3>,
419				 <&clockgen 4 3>, <&clockgen 4 3>;
420			clock-names = "bus", "mclk1", "mclk2", "mclk3";
421			dma-names = "tx", "rx";
422			dmas = <&edma0 1 45>,
423			       <&edma0 1 44>;
424			status = "disabled";
425		};
426
427		edma0: edma@2c00000 {
428			#dma-cells = <2>;
429			compatible = "fsl,vf610-edma";
430			reg = <0x0 0x2c00000 0x0 0x10000>,
431			      <0x0 0x2c10000 0x0 0x10000>,
432			      <0x0 0x2c20000 0x0 0x10000>;
433			interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
434				     <0 103 IRQ_TYPE_LEVEL_HIGH>;
435			interrupt-names = "edma-tx", "edma-err";
436			dma-channels = <32>;
437			big-endian;
438			clock-names = "dmamux0", "dmamux1";
439			clocks = <&clockgen 4 3>,
440				 <&clockgen 4 3>;
441		};
442
443		usb0: usb3@2f00000 {
444			compatible = "snps,dwc3";
445			reg = <0x0 0x2f00000 0x0 0x10000>;
446			interrupts = <0 60 0x4>;
447			dr_mode = "host";
448			snps,quirk-frame-length-adjustment = <0x20>;
449			snps,dis_rxdet_inp3_quirk;
450			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
451		};
452
453		sata: sata@3200000 {
454			compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
455			reg = <0x0 0x3200000 0x0 0x10000>,
456				<0x0 0x20140520 0x0 0x4>;
457			reg-names = "ahci", "sata-ecc";
458			interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
459			clocks = <&clockgen 4 0>;
460			dma-coherent;
461			status = "disabled";
462		};
463
464		usb1: usb2@8600000 {
465			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
466			reg = <0x0 0x8600000 0x0 0x1000>;
467			interrupts = <0 139 0x4>;
468			dr_mode = "host";
469			phy_type = "ulpi";
470		};
471
472		msi: msi-controller1@1572000 {
473			compatible = "fsl,ls1012a-msi";
474			reg = <0x0 0x1572000 0x0 0x8>;
475			msi-controller;
476			interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
477		};
478
479		pcie: pcie@3400000 {
480			compatible = "fsl,ls1012a-pcie";
481			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
482			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
483			reg-names = "regs", "config";
484			interrupts = <0 118 0x4>, /* controller interrupt */
485				     <0 117 0x4>; /* PME interrupt */
486			interrupt-names = "aer", "pme";
487			#address-cells = <3>;
488			#size-cells = <2>;
489			device_type = "pci";
490			num-viewport = <2>;
491			bus-range = <0x0 0xff>;
492			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
493				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
494			msi-parent = <&msi>;
495			#interrupt-cells = <1>;
496			interrupt-map-mask = <0 0 0 7>;
497			interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
498					<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
499					<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
500					<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
501			status = "disabled";
502		};
503	};
504
505	firmware {
506		optee {
507			compatible = "linaro,optee-tz";
508			method = "smc";
509		};
510	};
511};
512