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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4 *
5 * Copyright 2019 NXP.
6 *
7 */
8
9/dts-v1/;
10
11#include "fsl-ls1046a.dtsi"
12
13/ {
14	model = "LS1046A FRWY Board";
15	compatible = "fsl,ls1046a-frwy", "fsl,ls1046a";
16
17	aliases {
18		serial0 = &duart0;
19		serial1 = &duart1;
20		serial2 = &duart2;
21		serial3 = &duart3;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26	};
27
28	sb_3v3: regulator-sb3v3 {
29		compatible = "regulator-fixed";
30		regulator-name = "LT8642SEV-3.3V";
31		regulator-min-microvolt = <3300000>;
32		regulator-max-microvolt = <3300000>;
33		regulator-boot-on;
34		regulator-always-on;
35	};
36};
37
38&duart0 {
39	status = "okay";
40};
41
42&duart1 {
43	status = "okay";
44};
45
46&duart2 {
47	status = "okay";
48};
49
50&duart3 {
51	status = "okay";
52};
53
54&i2c0 {
55	status = "okay";
56
57	i2c-mux@77 {
58		compatible = "nxp,pca9546";
59		reg = <0x77>;
60		#address-cells = <1>;
61		#size-cells = <0>;
62
63		i2c@0 {
64			#address-cells = <1>;
65			#size-cells = <0>;
66			reg = <0>;
67
68			power-monitor@40 {
69				compatible = "ti,ina220";
70				reg = <0x40>;
71				shunt-resistor = <1000>;
72			};
73
74			temperature-sensor@4c {
75				compatible = "nxp,sa56004";
76				reg = <0x4c>;
77				vcc-supply = <&sb_3v3>;
78			};
79
80			rtc@51 {
81				compatible = "nxp,pcf2129";
82				reg = <0x51>;
83			};
84
85			eeprom@52 {
86				compatible = "onnn,cat24c04", "atmel,24c04";
87				reg = <0x52>;
88			};
89		};
90	};
91};
92
93&ifc {
94	#address-cells = <2>;
95	#size-cells = <1>;
96	/* NAND Flash */
97	ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>;
98	status = "okay";
99
100	nand@0,0 {
101		compatible = "fsl,ifc-nand";
102		#address-cells = <1>;
103		#size-cells = <1>;
104		reg = <0x0 0x0 0x10000>;
105	};
106
107};
108
109#include "fsl-ls1046-post.dtsi"
110
111&fman0 {
112	ethernet@e0000 {
113		phy-handle = <&qsgmii_phy4>;
114		phy-connection-type = "qsgmii";
115	};
116
117	ethernet@e8000 {
118		phy-handle = <&qsgmii_phy2>;
119		phy-connection-type = "qsgmii";
120	};
121
122	ethernet@ea000 {
123		phy-handle = <&qsgmii_phy1>;
124		phy-connection-type = "qsgmii";
125	};
126
127	ethernet@f2000 {
128		phy-handle = <&qsgmii_phy3>;
129		phy-connection-type = "qsgmii";
130	};
131
132	mdio@fd000 {
133		qsgmii_phy1: ethernet-phy@1c {
134			reg = <0x1c>;
135		};
136
137		qsgmii_phy2: ethernet-phy@1d {
138			reg = <0x1d>;
139		};
140
141		qsgmii_phy3: ethernet-phy@1e {
142			reg = <0x1e>;
143		};
144
145		qsgmii_phy4: ethernet-phy@1f {
146			reg = <0x1f>;
147		};
148	};
149};
150