1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Freescale Layerscape-1046A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * 7 * Mingkai Hu <mingkai.hu@nxp.com> 8 */ 9 10/dts-v1/; 11 12#include "fsl-ls1046a.dtsi" 13 14/ { 15 model = "LS1046A RDB Board"; 16 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; 17 18 aliases { 19 serial0 = &duart0; 20 serial1 = &duart1; 21 serial2 = &duart2; 22 serial3 = &duart3; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28}; 29 30&duart0 { 31 status = "okay"; 32}; 33 34&duart1 { 35 status = "okay"; 36}; 37 38&esdhc { 39 mmc-hs200-1_8v; 40 sd-uhs-sdr104; 41 sd-uhs-sdr50; 42 sd-uhs-sdr25; 43 sd-uhs-sdr12; 44}; 45 46&i2c0 { 47 status = "okay"; 48 49 ina220@40 { 50 compatible = "ti,ina220"; 51 reg = <0x40>; 52 shunt-resistor = <1000>; 53 }; 54 55 temp-sensor@4c { 56 compatible = "adi,adt7461"; 57 reg = <0x4c>; 58 }; 59 60 eeprom@52 { 61 compatible = "onnn,cat24c05", "atmel,24c04"; 62 reg = <0x52>; 63 }; 64}; 65 66&i2c3 { 67 status = "okay"; 68 69 rtc@51 { 70 compatible = "nxp,pcf2129"; 71 reg = <0x51>; 72 }; 73}; 74 75&ifc { 76 #address-cells = <2>; 77 #size-cells = <1>; 78 /* NAND Flashe and CPLD on board */ 79 ranges = <0x0 0x0 0x0 0x7e800000 0x00010000 80 0x2 0x0 0x0 0x7fb00000 0x00000100>; 81 status = "okay"; 82 83 nand@0,0 { 84 compatible = "fsl,ifc-nand"; 85 #address-cells = <1>; 86 #size-cells = <1>; 87 reg = <0x0 0x0 0x10000>; 88 }; 89 90 cpld: board-control@2,0 { 91 compatible = "fsl,ls1046ardb-cpld"; 92 reg = <0x2 0x0 0x0000100>; 93 }; 94}; 95 96&qspi { 97 status = "okay"; 98 99 qflash0: flash@0 { 100 compatible = "spansion,m25p80"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 spi-max-frequency = <20000000>; 104 spi-rx-bus-width = <4>; 105 spi-tx-bus-width = <4>; 106 reg = <0>; 107 }; 108 109 qflash1: flash@1 { 110 compatible = "spansion,m25p80"; 111 #address-cells = <1>; 112 #size-cells = <1>; 113 spi-max-frequency = <20000000>; 114 spi-rx-bus-width = <4>; 115 spi-tx-bus-width = <4>; 116 reg = <1>; 117 }; 118}; 119 120#include "fsl-ls1046-post.dtsi" 121 122&fman0 { 123 ethernet@e4000 { 124 phy-handle = <&rgmii_phy1>; 125 phy-connection-type = "rgmii-id"; 126 }; 127 128 ethernet@e6000 { 129 phy-handle = <&rgmii_phy2>; 130 phy-connection-type = "rgmii-id"; 131 }; 132 133 ethernet@e8000 { 134 phy-handle = <&sgmii_phy1>; 135 phy-connection-type = "sgmii"; 136 }; 137 138 ethernet@ea000 { 139 phy-handle = <&sgmii_phy2>; 140 phy-connection-type = "sgmii"; 141 }; 142 143 ethernet@f0000 { /* 10GEC1 */ 144 phy-handle = <&aqr106_phy>; 145 phy-connection-type = "xgmii"; 146 }; 147 148 ethernet@f2000 { /* 10GEC2 */ 149 fixed-link = <0 1 1000 0 0>; 150 phy-connection-type = "xgmii"; 151 }; 152 153 mdio@fc000 { 154 rgmii_phy1: ethernet-phy@1 { 155 reg = <0x1>; 156 }; 157 158 rgmii_phy2: ethernet-phy@2 { 159 reg = <0x2>; 160 }; 161 162 sgmii_phy1: ethernet-phy@3 { 163 reg = <0x3>; 164 }; 165 166 sgmii_phy2: ethernet-phy@4 { 167 reg = <0x4>; 168 }; 169 }; 170 171 mdio@fd000 { 172 aqr106_phy: ethernet-phy@0 { 173 compatible = "ethernet-phy-ieee802.3-c45"; 174 interrupts = <0 131 4>; 175 reg = <0x0>; 176 }; 177 }; 178}; 179