1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Freescale Layerscape-1046A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2018 NXP 7 * 8 * Mingkai Hu <mingkai.hu@nxp.com> 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1046a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 crypto = &crypto; 22 fman0 = &fman0; 23 ethernet0 = &enet0; 24 ethernet1 = &enet1; 25 ethernet2 = &enet2; 26 ethernet3 = &enet3; 27 ethernet4 = &enet4; 28 ethernet5 = &enet5; 29 ethernet6 = &enet6; 30 ethernet7 = &enet7; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a72"; 40 reg = <0x0>; 41 clocks = <&clockgen 1 0>; 42 next-level-cache = <&l2>; 43 cpu-idle-states = <&CPU_PH20>; 44 #cooling-cells = <2>; 45 }; 46 47 cpu1: cpu@1 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a72"; 50 reg = <0x1>; 51 clocks = <&clockgen 1 0>; 52 next-level-cache = <&l2>; 53 cpu-idle-states = <&CPU_PH20>; 54 #cooling-cells = <2>; 55 }; 56 57 cpu2: cpu@2 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a72"; 60 reg = <0x2>; 61 clocks = <&clockgen 1 0>; 62 next-level-cache = <&l2>; 63 cpu-idle-states = <&CPU_PH20>; 64 #cooling-cells = <2>; 65 }; 66 67 cpu3: cpu@3 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a72"; 70 reg = <0x3>; 71 clocks = <&clockgen 1 0>; 72 next-level-cache = <&l2>; 73 cpu-idle-states = <&CPU_PH20>; 74 #cooling-cells = <2>; 75 }; 76 77 l2: l2-cache { 78 compatible = "cache"; 79 }; 80 }; 81 82 idle-states { 83 /* 84 * PSCI node is not added default, U-boot will add missing 85 * parts if it determines to use PSCI. 86 */ 87 entry-method = "psci"; 88 89 CPU_PH20: cpu-ph20 { 90 compatible = "arm,idle-state"; 91 idle-state-name = "PH20"; 92 arm,psci-suspend-param = <0x0>; 93 entry-latency-us = <1000>; 94 exit-latency-us = <1000>; 95 min-residency-us = <3000>; 96 }; 97 }; 98 99 memory@80000000 { 100 device_type = "memory"; 101 /* Real size will be filled by bootloader */ 102 reg = <0x0 0x80000000 0x0 0x0>; 103 }; 104 105 sysclk: sysclk { 106 compatible = "fixed-clock"; 107 #clock-cells = <0>; 108 clock-frequency = <100000000>; 109 clock-output-names = "sysclk"; 110 }; 111 112 reboot { 113 compatible ="syscon-reboot"; 114 regmap = <&dcfg>; 115 offset = <0xb0>; 116 mask = <0x02>; 117 }; 118 119 thermal-zones { 120 cpu_thermal: cpu-thermal { 121 polling-delay-passive = <1000>; 122 polling-delay = <5000>; 123 thermal-sensors = <&tmu 3>; 124 125 trips { 126 cpu_alert: cpu-alert { 127 temperature = <85000>; 128 hysteresis = <2000>; 129 type = "passive"; 130 }; 131 132 cpu_crit: cpu-crit { 133 temperature = <95000>; 134 hysteresis = <2000>; 135 type = "critical"; 136 }; 137 }; 138 139 cooling-maps { 140 map0 { 141 trip = <&cpu_alert>; 142 cooling-device = 143 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 144 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 145 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 146 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 147 }; 148 }; 149 }; 150 }; 151 152 timer { 153 compatible = "arm,armv8-timer"; 154 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) | 155 IRQ_TYPE_LEVEL_LOW)>, 156 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) | 157 IRQ_TYPE_LEVEL_LOW)>, 158 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) | 159 IRQ_TYPE_LEVEL_LOW)>, 160 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) | 161 IRQ_TYPE_LEVEL_LOW)>; 162 }; 163 164 pmu { 165 compatible = "arm,cortex-a72-pmu"; 166 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 170 interrupt-affinity = <&cpu0>, 171 <&cpu1>, 172 <&cpu2>, 173 <&cpu3>; 174 }; 175 176 gic: interrupt-controller@1400000 { 177 compatible = "arm,gic-400"; 178 #interrupt-cells = <3>; 179 interrupt-controller; 180 reg = <0x0 0x1410000 0 0x10000>, /* GICD */ 181 <0x0 0x1420000 0 0x20000>, /* GICC */ 182 <0x0 0x1440000 0 0x20000>, /* GICH */ 183 <0x0 0x1460000 0 0x20000>; /* GICV */ 184 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 185 IRQ_TYPE_LEVEL_LOW)>; 186 }; 187 188 soc: soc { 189 compatible = "simple-bus"; 190 #address-cells = <2>; 191 #size-cells = <2>; 192 ranges; 193 194 ddr: memory-controller@1080000 { 195 compatible = "fsl,qoriq-memory-controller"; 196 reg = <0x0 0x1080000 0x0 0x1000>; 197 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 198 big-endian; 199 }; 200 201 ifc: ifc@1530000 { 202 compatible = "fsl,ifc", "simple-bus"; 203 reg = <0x0 0x1530000 0x0 0x10000>; 204 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 205 status = "disabled"; 206 }; 207 208 qspi: spi@1550000 { 209 compatible = "fsl,ls1021a-qspi"; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 reg = <0x0 0x1550000 0x0 0x10000>, 213 <0x0 0x40000000 0x0 0x10000000>; 214 reg-names = "QuadSPI", "QuadSPI-memory"; 215 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 216 clock-names = "qspi_en", "qspi"; 217 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 218 status = "disabled"; 219 }; 220 221 esdhc: esdhc@1560000 { 222 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; 223 reg = <0x0 0x1560000 0x0 0x10000>; 224 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&clockgen 2 1>; 226 voltage-ranges = <1800 1800 3300 3300>; 227 sdhci,auto-cmd12; 228 big-endian; 229 bus-width = <4>; 230 }; 231 232 scfg: scfg@1570000 { 233 compatible = "fsl,ls1046a-scfg", "syscon"; 234 reg = <0x0 0x1570000 0x0 0x10000>; 235 big-endian; 236 }; 237 238 crypto: crypto@1700000 { 239 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 240 "fsl,sec-v4.0"; 241 fsl,sec-era = <8>; 242 #address-cells = <1>; 243 #size-cells = <1>; 244 ranges = <0x0 0x00 0x1700000 0x100000>; 245 reg = <0x00 0x1700000 0x0 0x100000>; 246 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 247 dma-coherent; 248 249 sec_jr0: jr@10000 { 250 compatible = "fsl,sec-v5.4-job-ring", 251 "fsl,sec-v5.0-job-ring", 252 "fsl,sec-v4.0-job-ring"; 253 reg = <0x10000 0x10000>; 254 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 255 }; 256 257 sec_jr1: jr@20000 { 258 compatible = "fsl,sec-v5.4-job-ring", 259 "fsl,sec-v5.0-job-ring", 260 "fsl,sec-v4.0-job-ring"; 261 reg = <0x20000 0x10000>; 262 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 263 }; 264 265 sec_jr2: jr@30000 { 266 compatible = "fsl,sec-v5.4-job-ring", 267 "fsl,sec-v5.0-job-ring", 268 "fsl,sec-v4.0-job-ring"; 269 reg = <0x30000 0x10000>; 270 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 271 }; 272 273 sec_jr3: jr@40000 { 274 compatible = "fsl,sec-v5.4-job-ring", 275 "fsl,sec-v5.0-job-ring", 276 "fsl,sec-v4.0-job-ring"; 277 reg = <0x40000 0x10000>; 278 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 279 }; 280 }; 281 282 qman: qman@1880000 { 283 compatible = "fsl,qman"; 284 reg = <0x0 0x1880000 0x0 0x10000>; 285 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 286 memory-region = <&qman_fqd &qman_pfdr>; 287 288 }; 289 290 bman: bman@1890000 { 291 compatible = "fsl,bman"; 292 reg = <0x0 0x1890000 0x0 0x10000>; 293 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 294 memory-region = <&bman_fbpr>; 295 296 }; 297 298 qportals: qman-portals@500000000 { 299 ranges = <0x0 0x5 0x00000000 0x8000000>; 300 }; 301 302 bportals: bman-portals@508000000 { 303 ranges = <0x0 0x5 0x08000000 0x8000000>; 304 }; 305 306 dcfg: dcfg@1ee0000 { 307 compatible = "fsl,ls1046a-dcfg", "syscon"; 308 reg = <0x0 0x1ee0000 0x0 0x1000>; 309 big-endian; 310 }; 311 312 clockgen: clocking@1ee1000 { 313 compatible = "fsl,ls1046a-clockgen"; 314 reg = <0x0 0x1ee1000 0x0 0x1000>; 315 #clock-cells = <2>; 316 clocks = <&sysclk>; 317 }; 318 319 tmu: tmu@1f00000 { 320 compatible = "fsl,qoriq-tmu"; 321 reg = <0x0 0x1f00000 0x0 0x10000>; 322 interrupts = <0 33 0x4>; 323 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 324 fsl,tmu-calibration = 325 /* Calibration data group 1 */ 326 <0x00000000 0x00000026 327 0x00000001 0x0000002d 328 0x00000002 0x00000032 329 0x00000003 0x00000039 330 0x00000004 0x0000003f 331 0x00000005 0x00000046 332 0x00000006 0x0000004d 333 0x00000007 0x00000054 334 0x00000008 0x0000005a 335 0x00000009 0x00000061 336 0x0000000a 0x0000006a 337 0x0000000b 0x00000071 338 /* Calibration data group 2 */ 339 0x00010000 0x00000025 340 0x00010001 0x0000002c 341 0x00010002 0x00000035 342 0x00010003 0x0000003d 343 0x00010004 0x00000045 344 0x00010005 0x0000004e 345 0x00010006 0x00000057 346 0x00010007 0x00000061 347 0x00010008 0x0000006b 348 0x00010009 0x00000076 349 /* Calibration data group 3 */ 350 0x00020000 0x00000029 351 0x00020001 0x00000033 352 0x00020002 0x0000003d 353 0x00020003 0x00000049 354 0x00020004 0x00000056 355 0x00020005 0x00000061 356 0x00020006 0x0000006d 357 /* Calibration data group 4 */ 358 0x00030000 0x00000021 359 0x00030001 0x0000002a 360 0x00030002 0x0000003c 361 0x00030003 0x0000004e>; 362 big-endian; 363 #thermal-sensor-cells = <1>; 364 }; 365 366 dspi: spi@2100000 { 367 compatible = "fsl,ls1021a-v1.0-dspi"; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 reg = <0x0 0x2100000 0x0 0x10000>; 371 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 372 clock-names = "dspi"; 373 clocks = <&clockgen 4 1>; 374 spi-num-chipselects = <5>; 375 big-endian; 376 status = "disabled"; 377 }; 378 379 i2c0: i2c@2180000 { 380 compatible = "fsl,vf610-i2c"; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 reg = <0x0 0x2180000 0x0 0x10000>; 384 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&clockgen 4 1>; 386 dmas = <&edma0 1 39>, 387 <&edma0 1 38>; 388 dma-names = "tx", "rx"; 389 status = "disabled"; 390 }; 391 392 i2c1: i2c@2190000 { 393 compatible = "fsl,vf610-i2c"; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 reg = <0x0 0x2190000 0x0 0x10000>; 397 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&clockgen 4 1>; 399 status = "disabled"; 400 }; 401 402 i2c2: i2c@21a0000 { 403 compatible = "fsl,vf610-i2c"; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 reg = <0x0 0x21a0000 0x0 0x10000>; 407 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&clockgen 4 1>; 409 status = "disabled"; 410 }; 411 412 i2c3: i2c@21b0000 { 413 compatible = "fsl,vf610-i2c"; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 reg = <0x0 0x21b0000 0x0 0x10000>; 417 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&clockgen 4 1>; 419 status = "disabled"; 420 }; 421 422 duart0: serial@21c0500 { 423 compatible = "fsl,ns16550", "ns16550a"; 424 reg = <0x00 0x21c0500 0x0 0x100>; 425 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&clockgen 4 1>; 427 status = "disabled"; 428 }; 429 430 duart1: serial@21c0600 { 431 compatible = "fsl,ns16550", "ns16550a"; 432 reg = <0x00 0x21c0600 0x0 0x100>; 433 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&clockgen 4 1>; 435 status = "disabled"; 436 }; 437 438 duart2: serial@21d0500 { 439 compatible = "fsl,ns16550", "ns16550a"; 440 reg = <0x0 0x21d0500 0x0 0x100>; 441 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&clockgen 4 1>; 443 status = "disabled"; 444 }; 445 446 duart3: serial@21d0600 { 447 compatible = "fsl,ns16550", "ns16550a"; 448 reg = <0x0 0x21d0600 0x0 0x100>; 449 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&clockgen 4 1>; 451 status = "disabled"; 452 }; 453 454 gpio0: gpio@2300000 { 455 compatible = "fsl,qoriq-gpio"; 456 reg = <0x0 0x2300000 0x0 0x10000>; 457 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 458 gpio-controller; 459 #gpio-cells = <2>; 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 }; 463 464 gpio1: gpio@2310000 { 465 compatible = "fsl,qoriq-gpio"; 466 reg = <0x0 0x2310000 0x0 0x10000>; 467 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 468 gpio-controller; 469 #gpio-cells = <2>; 470 interrupt-controller; 471 #interrupt-cells = <2>; 472 }; 473 474 gpio2: gpio@2320000 { 475 compatible = "fsl,qoriq-gpio"; 476 reg = <0x0 0x2320000 0x0 0x10000>; 477 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 478 gpio-controller; 479 #gpio-cells = <2>; 480 interrupt-controller; 481 #interrupt-cells = <2>; 482 }; 483 484 gpio3: gpio@2330000 { 485 compatible = "fsl,qoriq-gpio"; 486 reg = <0x0 0x2330000 0x0 0x10000>; 487 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 488 gpio-controller; 489 #gpio-cells = <2>; 490 interrupt-controller; 491 #interrupt-cells = <2>; 492 }; 493 494 lpuart0: serial@2950000 { 495 compatible = "fsl,ls1021a-lpuart"; 496 reg = <0x0 0x2950000 0x0 0x1000>; 497 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&clockgen 4 0>; 499 clock-names = "ipg"; 500 status = "disabled"; 501 }; 502 503 lpuart1: serial@2960000 { 504 compatible = "fsl,ls1021a-lpuart"; 505 reg = <0x0 0x2960000 0x0 0x1000>; 506 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&clockgen 4 1>; 508 clock-names = "ipg"; 509 status = "disabled"; 510 }; 511 512 lpuart2: serial@2970000 { 513 compatible = "fsl,ls1021a-lpuart"; 514 reg = <0x0 0x2970000 0x0 0x1000>; 515 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&clockgen 4 1>; 517 clock-names = "ipg"; 518 status = "disabled"; 519 }; 520 521 lpuart3: serial@2980000 { 522 compatible = "fsl,ls1021a-lpuart"; 523 reg = <0x0 0x2980000 0x0 0x1000>; 524 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&clockgen 4 1>; 526 clock-names = "ipg"; 527 status = "disabled"; 528 }; 529 530 lpuart4: serial@2990000 { 531 compatible = "fsl,ls1021a-lpuart"; 532 reg = <0x0 0x2990000 0x0 0x1000>; 533 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&clockgen 4 1>; 535 clock-names = "ipg"; 536 status = "disabled"; 537 }; 538 539 lpuart5: serial@29a0000 { 540 compatible = "fsl,ls1021a-lpuart"; 541 reg = <0x0 0x29a0000 0x0 0x1000>; 542 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&clockgen 4 1>; 544 clock-names = "ipg"; 545 status = "disabled"; 546 }; 547 548 wdog0: watchdog@2ad0000 { 549 compatible = "fsl,imx21-wdt"; 550 reg = <0x0 0x2ad0000 0x0 0x10000>; 551 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&clockgen 4 1>; 553 big-endian; 554 }; 555 556 edma0: edma@2c00000 { 557 #dma-cells = <2>; 558 compatible = "fsl,vf610-edma"; 559 reg = <0x0 0x2c00000 0x0 0x10000>, 560 <0x0 0x2c10000 0x0 0x10000>, 561 <0x0 0x2c20000 0x0 0x10000>; 562 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 564 interrupt-names = "edma-tx", "edma-err"; 565 dma-channels = <32>; 566 big-endian; 567 clock-names = "dmamux0", "dmamux1"; 568 clocks = <&clockgen 4 1>, 569 <&clockgen 4 1>; 570 }; 571 572 usb0: usb@2f00000 { 573 compatible = "snps,dwc3"; 574 reg = <0x0 0x2f00000 0x0 0x10000>; 575 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 576 dr_mode = "host"; 577 snps,quirk-frame-length-adjustment = <0x20>; 578 snps,dis_rxdet_inp3_quirk; 579 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 580 }; 581 582 usb1: usb@3000000 { 583 compatible = "snps,dwc3"; 584 reg = <0x0 0x3000000 0x0 0x10000>; 585 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 586 dr_mode = "host"; 587 snps,quirk-frame-length-adjustment = <0x20>; 588 snps,dis_rxdet_inp3_quirk; 589 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 590 }; 591 592 usb2: usb@3100000 { 593 compatible = "snps,dwc3"; 594 reg = <0x0 0x3100000 0x0 0x10000>; 595 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 596 dr_mode = "host"; 597 snps,quirk-frame-length-adjustment = <0x20>; 598 snps,dis_rxdet_inp3_quirk; 599 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 600 }; 601 602 sata: sata@3200000 { 603 compatible = "fsl,ls1046a-ahci"; 604 reg = <0x0 0x3200000 0x0 0x10000>, 605 <0x0 0x20140520 0x0 0x4>; 606 reg-names = "ahci", "sata-ecc"; 607 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&clockgen 4 1>; 609 }; 610 611 msi1: msi-controller@1580000 { 612 compatible = "fsl,ls1046a-msi"; 613 msi-controller; 614 reg = <0x0 0x1580000 0x0 0x10000>; 615 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 619 }; 620 621 msi2: msi-controller@1590000 { 622 compatible = "fsl,ls1046a-msi"; 623 msi-controller; 624 reg = <0x0 0x1590000 0x0 0x10000>; 625 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 629 }; 630 631 msi3: msi-controller@15a0000 { 632 compatible = "fsl,ls1046a-msi"; 633 msi-controller; 634 reg = <0x0 0x15a0000 0x0 0x10000>; 635 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 639 }; 640 641 pcie@3400000 { 642 compatible = "fsl,ls1046a-pcie"; 643 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 644 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 645 reg-names = "regs", "config"; 646 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 647 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 648 interrupt-names = "aer", "pme"; 649 #address-cells = <3>; 650 #size-cells = <2>; 651 device_type = "pci"; 652 dma-coherent; 653 num-viewport = <8>; 654 bus-range = <0x0 0xff>; 655 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 656 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 657 msi-parent = <&msi1>, <&msi2>, <&msi3>; 658 #interrupt-cells = <1>; 659 interrupt-map-mask = <0 0 0 7>; 660 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 661 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 662 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 663 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 664 status = "disabled"; 665 }; 666 667 pcie_ep@3400000 { 668 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 669 reg = <0x00 0x03400000 0x0 0x00100000 670 0x40 0x00000000 0x8 0x00000000>; 671 reg-names = "regs", "addr_space"; 672 num-ib-windows = <6>; 673 num-ob-windows = <8>; 674 status = "disabled"; 675 }; 676 677 pcie@3500000 { 678 compatible = "fsl,ls1046a-pcie"; 679 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 680 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 681 reg-names = "regs", "config"; 682 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 683 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 684 interrupt-names = "aer", "pme"; 685 #address-cells = <3>; 686 #size-cells = <2>; 687 device_type = "pci"; 688 dma-coherent; 689 num-viewport = <8>; 690 bus-range = <0x0 0xff>; 691 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 692 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 693 msi-parent = <&msi2>, <&msi3>, <&msi1>; 694 #interrupt-cells = <1>; 695 interrupt-map-mask = <0 0 0 7>; 696 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 697 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 698 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 699 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 700 status = "disabled"; 701 }; 702 703 pcie_ep@3500000 { 704 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 705 reg = <0x00 0x03500000 0x0 0x00100000 706 0x48 0x00000000 0x8 0x00000000>; 707 reg-names = "regs", "addr_space"; 708 num-ib-windows = <6>; 709 num-ob-windows = <8>; 710 status = "disabled"; 711 }; 712 713 pcie@3600000 { 714 compatible = "fsl,ls1046a-pcie"; 715 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 716 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 717 reg-names = "regs", "config"; 718 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 719 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 720 interrupt-names = "aer", "pme"; 721 #address-cells = <3>; 722 #size-cells = <2>; 723 device_type = "pci"; 724 dma-coherent; 725 num-viewport = <8>; 726 bus-range = <0x0 0xff>; 727 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 728 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 729 msi-parent = <&msi3>, <&msi1>, <&msi2>; 730 #interrupt-cells = <1>; 731 interrupt-map-mask = <0 0 0 7>; 732 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 733 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 734 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 735 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 736 status = "disabled"; 737 }; 738 739 pcie_ep@3600000 { 740 compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; 741 reg = <0x00 0x03600000 0x0 0x00100000 742 0x50 0x00000000 0x8 0x00000000>; 743 reg-names = "regs", "addr_space"; 744 num-ib-windows = <6>; 745 num-ob-windows = <8>; 746 status = "disabled"; 747 }; 748 749 qdma: dma-controller@8380000 { 750 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; 751 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 752 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 753 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 754 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 759 interrupt-names = "qdma-error", "qdma-queue0", 760 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 761 dma-channels = <8>; 762 block-number = <1>; 763 block-offset = <0x10000>; 764 fsl,dma-queues = <2>; 765 status-sizes = <64>; 766 queue-sizes = <64 64>; 767 big-endian; 768 }; 769 }; 770 771 reserved-memory { 772 #address-cells = <2>; 773 #size-cells = <2>; 774 ranges; 775 776 bman_fbpr: bman-fbpr { 777 compatible = "shared-dma-pool"; 778 size = <0 0x1000000>; 779 alignment = <0 0x1000000>; 780 no-map; 781 }; 782 783 qman_fqd: qman-fqd { 784 compatible = "shared-dma-pool"; 785 size = <0 0x800000>; 786 alignment = <0 0x800000>; 787 no-map; 788 }; 789 790 qman_pfdr: qman-pfdr { 791 compatible = "shared-dma-pool"; 792 size = <0 0x2000000>; 793 alignment = <0 0x2000000>; 794 no-map; 795 }; 796 }; 797 798 firmware { 799 optee { 800 compatible = "linaro,optee-tz"; 801 method = "smc"; 802 }; 803 }; 804}; 805 806#include "qoriq-qman-portals.dtsi" 807#include "qoriq-bman-portals.dtsi" 808