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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for Globalscale Marvell ESPRESSOBin Board
4 * Copyright (C) 2016 Marvell
5 *
6 * Romain Perier <romain.perier@free-electrons.com>
7 *
8 */
9/*
10 * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
11 */
12
13/dts-v1/;
14
15#include <dt-bindings/gpio/gpio.h>
16#include "armada-372x.dtsi"
17
18/ {
19	model = "Globalscale Marvell ESPRESSOBin Board";
20	compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
21
22	aliases {
23		ethernet0 = &eth0;
24		/* for dsa slave device */
25		ethernet1 = &switch0port1;
26		ethernet2 = &switch0port2;
27		ethernet3 = &switch0port3;
28		serial0 = &uart0;
29		serial1 = &uart1;
30	};
31
32	chosen {
33		stdout-path = "serial0:115200n8";
34	};
35
36	memory@0 {
37		device_type = "memory";
38		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
39	};
40
41	vcc_sd_reg1: regulator {
42		compatible = "regulator-gpio";
43		regulator-name = "vcc_sd1";
44		regulator-min-microvolt = <1800000>;
45		regulator-max-microvolt = <3300000>;
46		regulator-boot-on;
47
48		gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
49		gpios-states = <0>;
50		states = <1800000 0x1
51			  3300000 0x0>;
52		enable-active-high;
53	};
54};
55
56/* J9 */
57&pcie0 {
58	status = "okay";
59	phys = <&comphy1 0>;
60	pinctrl-names = "default";
61	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
62	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
63};
64
65/* J6 */
66&sata {
67	status = "okay";
68	phys = <&comphy2 0>;
69	phy-names = "sata-phy";
70};
71
72/* J1 */
73&sdhci1 {
74	wp-inverted;
75	bus-width = <4>;
76	cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
77	marvell,pad-type = "sd";
78	vqmmc-supply = <&vcc_sd_reg1>;
79
80	pinctrl-names = "default";
81	pinctrl-0 = <&sdio_pins>;
82	status = "okay";
83};
84
85/* U11 */
86&sdhci0 {
87	non-removable;
88	bus-width = <8>;
89	mmc-ddr-1_8v;
90	mmc-hs400-1_8v;
91	marvell,xenon-emmc;
92	marvell,xenon-tun-count = <9>;
93	marvell,pad-type = "fixed-1-8v";
94
95	pinctrl-names = "default";
96	pinctrl-0 = <&mmc_pins>;
97/*
98 * This eMMC is not populated on all boards, so disable it by
99 * default and let the bootloader enable it, if it is present
100 */
101	status = "disabled";
102};
103
104&spi0 {
105	status = "okay";
106
107	flash@0 {
108		reg = <0>;
109		compatible = "jedec,spi-nor";
110		spi-max-frequency = <104000000>;
111		m25p,fast-read;
112	};
113};
114
115/* Exported on the micro USB connector J5 through an FTDI */
116&uart0 {
117	pinctrl-names = "default";
118	pinctrl-0 = <&uart1_pins>;
119	status = "okay";
120};
121
122/*
123 * Connector J17 and J18 expose a number of different features. Some pins are
124 * multiplexed. This is the case for instance for the following features:
125 * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
126 *   how to enable it. Beware that the signals are 1.8V TTL.
127 * - I2C
128 * - SPI
129 * - MMC
130 */
131
132/* J7 */
133&usb3 {
134	status = "okay";
135};
136
137/* J8 */
138&usb2 {
139	status = "okay";
140};
141
142&mdio {
143	switch0: switch0@1 {
144		compatible = "marvell,mv88e6085";
145		#address-cells = <1>;
146		#size-cells = <0>;
147		reg = <1>;
148
149		dsa,member = <0 0>;
150
151		ports {
152			#address-cells = <1>;
153			#size-cells = <0>;
154
155			switch0port0: port@0 {
156				reg = <0>;
157				label = "cpu";
158				ethernet = <&eth0>;
159				phy-mode = "rgmii-id";
160				fixed-link {
161					speed = <1000>;
162					full-duplex;
163				};
164			};
165
166			switch0port1: port@1 {
167				reg = <1>;
168				label = "wan";
169				phy-handle = <&switch0phy0>;
170			};
171
172			switch0port2: port@2 {
173				reg = <2>;
174				label = "lan0";
175				phy-handle = <&switch0phy1>;
176			};
177
178			switch0port3: port@3 {
179				reg = <3>;
180				label = "lan1";
181				phy-handle = <&switch0phy2>;
182			};
183
184		};
185
186		mdio {
187			#address-cells = <1>;
188			#size-cells = <0>;
189
190			switch0phy0: switch0phy0@11 {
191				reg = <0x11>;
192			};
193			switch0phy1: switch0phy1@12 {
194				reg = <0x12>;
195			};
196			switch0phy2: switch0phy2@13 {
197				reg = <0x13>;
198			};
199		};
200	};
201};
202
203&eth0 {
204	pinctrl-names = "default";
205	pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
206	phy-mode = "rgmii-id";
207	status = "okay";
208
209	fixed-link {
210		speed = <1000>;
211		full-duplex;
212	};
213};
214