1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 iommus = <&smmu TEGRA186_SID_EQOS>; 64 status = "disabled"; 65 66 snps,write-requests = <1>; 67 snps,read-requests = <3>; 68 snps,burst-map = <0x7>; 69 snps,txpbl = <32>; 70 snps,rxpbl = <8>; 71 }; 72 73 aconnect { 74 compatible = "nvidia,tegra186-aconnect", 75 "nvidia,tegra210-aconnect"; 76 clocks = <&bpmp TEGRA186_CLK_APE>, 77 <&bpmp TEGRA186_CLK_APB2APE>; 78 clock-names = "ape", "apb2ape"; 79 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 80 #address-cells = <1>; 81 #size-cells = <1>; 82 ranges = <0x02900000 0x0 0x02900000 0x200000>; 83 status = "disabled"; 84 85 dma-controller@2930000 { 86 compatible = "nvidia,tegra186-adma"; 87 reg = <0x02930000 0x20000>; 88 interrupt-parent = <&agic>; 89 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 121 #dma-cells = <1>; 122 clocks = <&bpmp TEGRA186_CLK_AHUB>; 123 clock-names = "d_audio"; 124 status = "disabled"; 125 }; 126 127 agic: interrupt-controller@2a40000 { 128 compatible = "nvidia,tegra186-agic", 129 "nvidia,tegra210-agic"; 130 #interrupt-cells = <3>; 131 interrupt-controller; 132 reg = <0x02a41000 0x1000>, 133 <0x02a42000 0x2000>; 134 interrupts = <GIC_SPI 145 135 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 136 clocks = <&bpmp TEGRA186_CLK_APE>; 137 clock-names = "clk"; 138 status = "disabled"; 139 }; 140 }; 141 142 memory-controller@2c00000 { 143 compatible = "nvidia,tegra186-mc"; 144 reg = <0x0 0x02c00000 0x0 0xb0000>; 145 status = "disabled"; 146 }; 147 148 uarta: serial@3100000 { 149 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 150 reg = <0x0 0x03100000 0x0 0x40>; 151 reg-shift = <2>; 152 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&bpmp TEGRA186_CLK_UARTA>; 154 clock-names = "serial"; 155 resets = <&bpmp TEGRA186_RESET_UARTA>; 156 reset-names = "serial"; 157 status = "disabled"; 158 }; 159 160 uartb: serial@3110000 { 161 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 162 reg = <0x0 0x03110000 0x0 0x40>; 163 reg-shift = <2>; 164 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&bpmp TEGRA186_CLK_UARTB>; 166 clock-names = "serial"; 167 resets = <&bpmp TEGRA186_RESET_UARTB>; 168 reset-names = "serial"; 169 status = "disabled"; 170 }; 171 172 uartd: serial@3130000 { 173 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 174 reg = <0x0 0x03130000 0x0 0x40>; 175 reg-shift = <2>; 176 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&bpmp TEGRA186_CLK_UARTD>; 178 clock-names = "serial"; 179 resets = <&bpmp TEGRA186_RESET_UARTD>; 180 reset-names = "serial"; 181 status = "disabled"; 182 }; 183 184 uarte: serial@3140000 { 185 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 186 reg = <0x0 0x03140000 0x0 0x40>; 187 reg-shift = <2>; 188 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&bpmp TEGRA186_CLK_UARTE>; 190 clock-names = "serial"; 191 resets = <&bpmp TEGRA186_RESET_UARTE>; 192 reset-names = "serial"; 193 status = "disabled"; 194 }; 195 196 uartf: serial@3150000 { 197 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 198 reg = <0x0 0x03150000 0x0 0x40>; 199 reg-shift = <2>; 200 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 201 clocks = <&bpmp TEGRA186_CLK_UARTF>; 202 clock-names = "serial"; 203 resets = <&bpmp TEGRA186_RESET_UARTF>; 204 reset-names = "serial"; 205 status = "disabled"; 206 }; 207 208 gen1_i2c: i2c@3160000 { 209 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 210 reg = <0x0 0x03160000 0x0 0x10000>; 211 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 clocks = <&bpmp TEGRA186_CLK_I2C1>; 215 clock-names = "div-clk"; 216 resets = <&bpmp TEGRA186_RESET_I2C1>; 217 reset-names = "i2c"; 218 status = "disabled"; 219 }; 220 221 cam_i2c: i2c@3180000 { 222 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 223 reg = <0x0 0x03180000 0x0 0x10000>; 224 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 clocks = <&bpmp TEGRA186_CLK_I2C3>; 228 clock-names = "div-clk"; 229 resets = <&bpmp TEGRA186_RESET_I2C3>; 230 reset-names = "i2c"; 231 status = "disabled"; 232 }; 233 234 /* shares pads with dpaux1 */ 235 dp_aux_ch1_i2c: i2c@3190000 { 236 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 237 reg = <0x0 0x03190000 0x0 0x10000>; 238 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 clocks = <&bpmp TEGRA186_CLK_I2C4>; 242 clock-names = "div-clk"; 243 resets = <&bpmp TEGRA186_RESET_I2C4>; 244 reset-names = "i2c"; 245 pinctrl-names = "default", "idle"; 246 pinctrl-0 = <&state_dpaux1_i2c>; 247 pinctrl-1 = <&state_dpaux1_off>; 248 status = "disabled"; 249 }; 250 251 /* controlled by BPMP, should not be enabled */ 252 pwr_i2c: i2c@31a0000 { 253 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 254 reg = <0x0 0x031a0000 0x0 0x10000>; 255 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 clocks = <&bpmp TEGRA186_CLK_I2C5>; 259 clock-names = "div-clk"; 260 resets = <&bpmp TEGRA186_RESET_I2C5>; 261 reset-names = "i2c"; 262 status = "disabled"; 263 }; 264 265 /* shares pads with dpaux0 */ 266 dp_aux_ch0_i2c: i2c@31b0000 { 267 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 268 reg = <0x0 0x031b0000 0x0 0x10000>; 269 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 clocks = <&bpmp TEGRA186_CLK_I2C6>; 273 clock-names = "div-clk"; 274 resets = <&bpmp TEGRA186_RESET_I2C6>; 275 reset-names = "i2c"; 276 pinctrl-names = "default", "idle"; 277 pinctrl-0 = <&state_dpaux_i2c>; 278 pinctrl-1 = <&state_dpaux_off>; 279 status = "disabled"; 280 }; 281 282 gen7_i2c: i2c@31c0000 { 283 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 284 reg = <0x0 0x031c0000 0x0 0x10000>; 285 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 clocks = <&bpmp TEGRA186_CLK_I2C7>; 289 clock-names = "div-clk"; 290 resets = <&bpmp TEGRA186_RESET_I2C7>; 291 reset-names = "i2c"; 292 status = "disabled"; 293 }; 294 295 gen9_i2c: i2c@31e0000 { 296 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 297 reg = <0x0 0x031e0000 0x0 0x10000>; 298 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 clocks = <&bpmp TEGRA186_CLK_I2C9>; 302 clock-names = "div-clk"; 303 resets = <&bpmp TEGRA186_RESET_I2C9>; 304 reset-names = "i2c"; 305 status = "disabled"; 306 }; 307 308 sdmmc1: sdhci@3400000 { 309 compatible = "nvidia,tegra186-sdhci"; 310 reg = <0x0 0x03400000 0x0 0x10000>; 311 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 313 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 314 clock-names = "sdhci", "tmclk"; 315 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 316 reset-names = "sdhci"; 317 iommus = <&smmu TEGRA186_SID_SDMMC1>; 318 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 319 pinctrl-0 = <&sdmmc1_3v3>; 320 pinctrl-1 = <&sdmmc1_1v8>; 321 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 322 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 323 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 324 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 325 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 326 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 327 nvidia,default-tap = <0x5>; 328 nvidia,default-trim = <0xb>; 329 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 330 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 331 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 332 status = "disabled"; 333 }; 334 335 sdmmc2: sdhci@3420000 { 336 compatible = "nvidia,tegra186-sdhci"; 337 reg = <0x0 0x03420000 0x0 0x10000>; 338 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 340 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 341 clock-names = "sdhci", "tmclk"; 342 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 343 reset-names = "sdhci"; 344 iommus = <&smmu TEGRA186_SID_SDMMC2>; 345 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 346 pinctrl-0 = <&sdmmc2_3v3>; 347 pinctrl-1 = <&sdmmc2_1v8>; 348 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 349 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 350 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 351 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 352 nvidia,default-tap = <0x5>; 353 nvidia,default-trim = <0xb>; 354 status = "disabled"; 355 }; 356 357 sdmmc3: sdhci@3440000 { 358 compatible = "nvidia,tegra186-sdhci"; 359 reg = <0x0 0x03440000 0x0 0x10000>; 360 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 362 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 363 clock-names = "sdhci", "tmclk"; 364 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 365 reset-names = "sdhci"; 366 iommus = <&smmu TEGRA186_SID_SDMMC3>; 367 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 368 pinctrl-0 = <&sdmmc3_3v3>; 369 pinctrl-1 = <&sdmmc3_1v8>; 370 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 371 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 372 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 373 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 374 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 375 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 376 nvidia,default-tap = <0x5>; 377 nvidia,default-trim = <0xb>; 378 status = "disabled"; 379 }; 380 381 sdmmc4: sdhci@3460000 { 382 compatible = "nvidia,tegra186-sdhci"; 383 reg = <0x0 0x03460000 0x0 0x10000>; 384 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 386 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 387 clock-names = "sdhci", "tmclk"; 388 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 389 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 390 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 391 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 392 reset-names = "sdhci"; 393 iommus = <&smmu TEGRA186_SID_SDMMC4>; 394 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 395 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 396 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 397 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 398 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 399 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 400 nvidia,default-tap = <0x9>; 401 nvidia,default-trim = <0x5>; 402 nvidia,dqs-trim = <63>; 403 mmc-hs400-1_8v; 404 supports-cqe; 405 status = "disabled"; 406 }; 407 408 hda@3510000 { 409 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 410 reg = <0x0 0x03510000 0x0 0x10000>; 411 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&bpmp TEGRA186_CLK_HDA>, 413 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 414 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 415 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 416 resets = <&bpmp TEGRA186_RESET_HDA>, 417 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 418 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 419 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 420 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 421 iommus = <&smmu TEGRA186_SID_HDA>; 422 status = "disabled"; 423 }; 424 425 padctl: padctl@3520000 { 426 compatible = "nvidia,tegra186-xusb-padctl"; 427 reg = <0x0 0x03520000 0x0 0x1000>, 428 <0x0 0x03540000 0x0 0x1000>; 429 reg-names = "padctl", "ao"; 430 431 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 432 reset-names = "padctl"; 433 434 status = "disabled"; 435 436 pads { 437 usb2 { 438 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 439 clock-names = "trk"; 440 status = "disabled"; 441 442 lanes { 443 usb2-0 { 444 status = "disabled"; 445 #phy-cells = <0>; 446 }; 447 448 usb2-1 { 449 status = "disabled"; 450 #phy-cells = <0>; 451 }; 452 453 usb2-2 { 454 status = "disabled"; 455 #phy-cells = <0>; 456 }; 457 }; 458 }; 459 460 hsic { 461 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 462 clock-names = "trk"; 463 status = "disabled"; 464 465 lanes { 466 hsic-0 { 467 status = "disabled"; 468 #phy-cells = <0>; 469 }; 470 }; 471 }; 472 473 usb3 { 474 status = "disabled"; 475 476 lanes { 477 usb3-0 { 478 status = "disabled"; 479 #phy-cells = <0>; 480 }; 481 482 usb3-1 { 483 status = "disabled"; 484 #phy-cells = <0>; 485 }; 486 487 usb3-2 { 488 status = "disabled"; 489 #phy-cells = <0>; 490 }; 491 }; 492 }; 493 }; 494 495 ports { 496 usb2-0 { 497 status = "disabled"; 498 }; 499 500 usb2-1 { 501 status = "disabled"; 502 }; 503 504 usb2-2 { 505 status = "disabled"; 506 }; 507 508 hsic-0 { 509 status = "disabled"; 510 }; 511 512 usb3-0 { 513 status = "disabled"; 514 }; 515 516 usb3-1 { 517 status = "disabled"; 518 }; 519 520 usb3-2 { 521 status = "disabled"; 522 }; 523 }; 524 }; 525 526 usb@3530000 { 527 compatible = "nvidia,tegra186-xusb"; 528 reg = <0x0 0x03530000 0x0 0x8000>, 529 <0x0 0x03538000 0x0 0x1000>; 530 reg-names = "hcd", "fpci"; 531 532 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 535 536 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 537 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 538 <&bpmp TEGRA186_CLK_XUSB_SS>, 539 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 540 <&bpmp TEGRA186_CLK_CLK_M>, 541 <&bpmp TEGRA186_CLK_XUSB_FS>, 542 <&bpmp TEGRA186_CLK_PLLU>, 543 <&bpmp TEGRA186_CLK_CLK_M>, 544 <&bpmp TEGRA186_CLK_PLLE>; 545 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 546 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 547 "pll_u_480m", "clk_m", "pll_e"; 548 549 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 550 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 551 power-domain-names = "xusb_host", "xusb_ss"; 552 nvidia,xusb-padctl = <&padctl>; 553 554 status = "disabled"; 555 556 #address-cells = <1>; 557 #size-cells = <0>; 558 }; 559 560 fuse@3820000 { 561 compatible = "nvidia,tegra186-efuse"; 562 reg = <0x0 0x03820000 0x0 0x10000>; 563 clocks = <&bpmp TEGRA186_CLK_FUSE>; 564 clock-names = "fuse"; 565 }; 566 567 gic: interrupt-controller@3881000 { 568 compatible = "arm,gic-400"; 569 #interrupt-cells = <3>; 570 interrupt-controller; 571 reg = <0x0 0x03881000 0x0 0x1000>, 572 <0x0 0x03882000 0x0 0x2000>; 573 interrupts = <GIC_PPI 9 574 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 575 interrupt-parent = <&gic>; 576 }; 577 578 cec@3960000 { 579 compatible = "nvidia,tegra186-cec"; 580 reg = <0x0 0x03960000 0x0 0x10000>; 581 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&bpmp TEGRA186_CLK_CEC>; 583 clock-names = "cec"; 584 status = "disabled"; 585 }; 586 587 hsp_top0: hsp@3c00000 { 588 compatible = "nvidia,tegra186-hsp"; 589 reg = <0x0 0x03c00000 0x0 0xa0000>; 590 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 591 interrupt-names = "doorbell"; 592 #mbox-cells = <2>; 593 status = "disabled"; 594 }; 595 596 gen2_i2c: i2c@c240000 { 597 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 598 reg = <0x0 0x0c240000 0x0 0x10000>; 599 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 clocks = <&bpmp TEGRA186_CLK_I2C2>; 603 clock-names = "div-clk"; 604 resets = <&bpmp TEGRA186_RESET_I2C2>; 605 reset-names = "i2c"; 606 status = "disabled"; 607 }; 608 609 gen8_i2c: i2c@c250000 { 610 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 611 reg = <0x0 0x0c250000 0x0 0x10000>; 612 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 clocks = <&bpmp TEGRA186_CLK_I2C8>; 616 clock-names = "div-clk"; 617 resets = <&bpmp TEGRA186_RESET_I2C8>; 618 reset-names = "i2c"; 619 status = "disabled"; 620 }; 621 622 uartc: serial@c280000 { 623 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 624 reg = <0x0 0x0c280000 0x0 0x40>; 625 reg-shift = <2>; 626 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&bpmp TEGRA186_CLK_UARTC>; 628 clock-names = "serial"; 629 resets = <&bpmp TEGRA186_RESET_UARTC>; 630 reset-names = "serial"; 631 status = "disabled"; 632 }; 633 634 uartg: serial@c290000 { 635 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 636 reg = <0x0 0x0c290000 0x0 0x40>; 637 reg-shift = <2>; 638 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&bpmp TEGRA186_CLK_UARTG>; 640 clock-names = "serial"; 641 resets = <&bpmp TEGRA186_RESET_UARTG>; 642 reset-names = "serial"; 643 status = "disabled"; 644 }; 645 646 rtc: rtc@c2a0000 { 647 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 648 reg = <0 0x0c2a0000 0 0x10000>; 649 interrupt-parent = <&pmc>; 650 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 652 clock-names = "rtc"; 653 status = "disabled"; 654 }; 655 656 gpio_aon: gpio@c2f0000 { 657 compatible = "nvidia,tegra186-gpio-aon"; 658 reg-names = "security", "gpio"; 659 reg = <0x0 0xc2f0000 0x0 0x1000>, 660 <0x0 0xc2f1000 0x0 0x1000>; 661 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 662 gpio-controller; 663 #gpio-cells = <2>; 664 interrupt-controller; 665 #interrupt-cells = <2>; 666 }; 667 668 pmc: pmc@c360000 { 669 compatible = "nvidia,tegra186-pmc"; 670 reg = <0 0x0c360000 0 0x10000>, 671 <0 0x0c370000 0 0x10000>, 672 <0 0x0c380000 0 0x10000>, 673 <0 0x0c390000 0 0x10000>; 674 reg-names = "pmc", "wake", "aotag", "scratch"; 675 676 #interrupt-cells = <2>; 677 interrupt-controller; 678 679 sdmmc1_3v3: sdmmc1-3v3 { 680 pins = "sdmmc1-hv"; 681 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 682 }; 683 684 sdmmc1_1v8: sdmmc1-1v8 { 685 pins = "sdmmc1-hv"; 686 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 687 }; 688 689 sdmmc2_3v3: sdmmc2-3v3 { 690 pins = "sdmmc2-hv"; 691 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 692 }; 693 694 sdmmc2_1v8: sdmmc2-1v8 { 695 pins = "sdmmc2-hv"; 696 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 697 }; 698 699 sdmmc3_3v3: sdmmc3-3v3 { 700 pins = "sdmmc3-hv"; 701 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 702 }; 703 704 sdmmc3_1v8: sdmmc3-1v8 { 705 pins = "sdmmc3-hv"; 706 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 707 }; 708 }; 709 710 ccplex@e000000 { 711 compatible = "nvidia,tegra186-ccplex-cluster"; 712 reg = <0x0 0x0e000000 0x0 0x400000>; 713 714 nvidia,bpmp = <&bpmp>; 715 }; 716 717 pcie@10003000 { 718 compatible = "nvidia,tegra186-pcie"; 719 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 720 device_type = "pci"; 721 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 722 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 723 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 724 reg-names = "pads", "afi", "cs"; 725 726 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 727 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 728 interrupt-names = "intr", "msi"; 729 730 #interrupt-cells = <1>; 731 interrupt-map-mask = <0 0 0 0>; 732 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 733 734 bus-range = <0x00 0xff>; 735 #address-cells = <3>; 736 #size-cells = <2>; 737 738 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 739 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 740 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 741 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 742 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 743 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 744 745 clocks = <&bpmp TEGRA186_CLK_AFI>, 746 <&bpmp TEGRA186_CLK_PCIE>, 747 <&bpmp TEGRA186_CLK_PLLE>; 748 clock-names = "afi", "pex", "pll_e"; 749 750 resets = <&bpmp TEGRA186_RESET_AFI>, 751 <&bpmp TEGRA186_RESET_PCIE>, 752 <&bpmp TEGRA186_RESET_PCIEXCLK>; 753 reset-names = "afi", "pex", "pcie_x"; 754 755 iommus = <&smmu TEGRA186_SID_AFI>; 756 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 757 iommu-map-mask = <0x0>; 758 759 status = "disabled"; 760 761 pci@1,0 { 762 device_type = "pci"; 763 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 764 reg = <0x000800 0 0 0 0>; 765 status = "disabled"; 766 767 #address-cells = <3>; 768 #size-cells = <2>; 769 ranges; 770 771 nvidia,num-lanes = <2>; 772 }; 773 774 pci@2,0 { 775 device_type = "pci"; 776 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 777 reg = <0x001000 0 0 0 0>; 778 status = "disabled"; 779 780 #address-cells = <3>; 781 #size-cells = <2>; 782 ranges; 783 784 nvidia,num-lanes = <1>; 785 }; 786 787 pci@3,0 { 788 device_type = "pci"; 789 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 790 reg = <0x001800 0 0 0 0>; 791 status = "disabled"; 792 793 #address-cells = <3>; 794 #size-cells = <2>; 795 ranges; 796 797 nvidia,num-lanes = <1>; 798 }; 799 }; 800 801 smmu: iommu@12000000 { 802 compatible = "arm,mmu-500"; 803 reg = <0 0x12000000 0 0x800000>; 804 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 869 stream-match-mask = <0x7f80>; 870 #global-interrupts = <1>; 871 #iommu-cells = <1>; 872 }; 873 874 host1x@13e00000 { 875 compatible = "nvidia,tegra186-host1x", "simple-bus"; 876 reg = <0x0 0x13e00000 0x0 0x10000>, 877 <0x0 0x13e10000 0x0 0x10000>; 878 reg-names = "hypervisor", "vm"; 879 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 882 clock-names = "host1x"; 883 resets = <&bpmp TEGRA186_RESET_HOST1X>; 884 reset-names = "host1x"; 885 886 #address-cells = <1>; 887 #size-cells = <1>; 888 889 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 890 iommus = <&smmu TEGRA186_SID_HOST1X>; 891 892 dpaux1: dpaux@15040000 { 893 compatible = "nvidia,tegra186-dpaux"; 894 reg = <0x15040000 0x10000>; 895 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 897 <&bpmp TEGRA186_CLK_PLLDP>; 898 clock-names = "dpaux", "parent"; 899 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 900 reset-names = "dpaux"; 901 status = "disabled"; 902 903 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 904 905 state_dpaux1_aux: pinmux-aux { 906 groups = "dpaux-io"; 907 function = "aux"; 908 }; 909 910 state_dpaux1_i2c: pinmux-i2c { 911 groups = "dpaux-io"; 912 function = "i2c"; 913 }; 914 915 state_dpaux1_off: pinmux-off { 916 groups = "dpaux-io"; 917 function = "off"; 918 }; 919 920 i2c-bus { 921 #address-cells = <1>; 922 #size-cells = <0>; 923 }; 924 }; 925 926 display-hub@15200000 { 927 compatible = "nvidia,tegra186-display", "simple-bus"; 928 reg = <0x15200000 0x00040000>; 929 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 930 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 931 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 932 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 933 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 934 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 935 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 936 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 937 "wgrp3", "wgrp4", "wgrp5"; 938 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 939 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 940 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 941 clock-names = "disp", "dsc", "hub"; 942 status = "disabled"; 943 944 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 945 946 #address-cells = <1>; 947 #size-cells = <1>; 948 949 ranges = <0x15200000 0x15200000 0x40000>; 950 951 display@15200000 { 952 compatible = "nvidia,tegra186-dc"; 953 reg = <0x15200000 0x10000>; 954 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 956 clock-names = "dc"; 957 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 958 reset-names = "dc"; 959 960 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 961 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 962 963 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 964 nvidia,head = <0>; 965 }; 966 967 display@15210000 { 968 compatible = "nvidia,tegra186-dc"; 969 reg = <0x15210000 0x10000>; 970 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 972 clock-names = "dc"; 973 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 974 reset-names = "dc"; 975 976 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 977 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 978 979 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 980 nvidia,head = <1>; 981 }; 982 983 display@15220000 { 984 compatible = "nvidia,tegra186-dc"; 985 reg = <0x15220000 0x10000>; 986 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 988 clock-names = "dc"; 989 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 990 reset-names = "dc"; 991 992 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 993 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 994 995 nvidia,outputs = <&sor0 &sor1>; 996 nvidia,head = <2>; 997 }; 998 }; 999 1000 dsia: dsi@15300000 { 1001 compatible = "nvidia,tegra186-dsi"; 1002 reg = <0x15300000 0x10000>; 1003 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&bpmp TEGRA186_CLK_DSI>, 1005 <&bpmp TEGRA186_CLK_DSIA_LP>, 1006 <&bpmp TEGRA186_CLK_PLLD>; 1007 clock-names = "dsi", "lp", "parent"; 1008 resets = <&bpmp TEGRA186_RESET_DSI>; 1009 reset-names = "dsi"; 1010 status = "disabled"; 1011 1012 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1013 }; 1014 1015 vic@15340000 { 1016 compatible = "nvidia,tegra186-vic"; 1017 reg = <0x15340000 0x40000>; 1018 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&bpmp TEGRA186_CLK_VIC>; 1020 clock-names = "vic"; 1021 resets = <&bpmp TEGRA186_RESET_VIC>; 1022 reset-names = "vic"; 1023 1024 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1025 }; 1026 1027 dsib: dsi@15400000 { 1028 compatible = "nvidia,tegra186-dsi"; 1029 reg = <0x15400000 0x10000>; 1030 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1032 <&bpmp TEGRA186_CLK_DSIB_LP>, 1033 <&bpmp TEGRA186_CLK_PLLD>; 1034 clock-names = "dsi", "lp", "parent"; 1035 resets = <&bpmp TEGRA186_RESET_DSIB>; 1036 reset-names = "dsi"; 1037 status = "disabled"; 1038 1039 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1040 }; 1041 1042 sor0: sor@15540000 { 1043 compatible = "nvidia,tegra186-sor"; 1044 reg = <0x15540000 0x10000>; 1045 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1046 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1047 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1048 <&bpmp TEGRA186_CLK_PLLD2>, 1049 <&bpmp TEGRA186_CLK_PLLDP>, 1050 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1051 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1052 clock-names = "sor", "out", "parent", "dp", "safe", 1053 "pad"; 1054 resets = <&bpmp TEGRA186_RESET_SOR0>; 1055 reset-names = "sor"; 1056 pinctrl-0 = <&state_dpaux_aux>; 1057 pinctrl-1 = <&state_dpaux_i2c>; 1058 pinctrl-2 = <&state_dpaux_off>; 1059 pinctrl-names = "aux", "i2c", "off"; 1060 status = "disabled"; 1061 1062 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1063 nvidia,interface = <0>; 1064 }; 1065 1066 sor1: sor@15580000 { 1067 compatible = "nvidia,tegra186-sor1"; 1068 reg = <0x15580000 0x10000>; 1069 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1071 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1072 <&bpmp TEGRA186_CLK_PLLD3>, 1073 <&bpmp TEGRA186_CLK_PLLDP>, 1074 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1075 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1076 clock-names = "sor", "out", "parent", "dp", "safe", 1077 "pad"; 1078 resets = <&bpmp TEGRA186_RESET_SOR1>; 1079 reset-names = "sor"; 1080 pinctrl-0 = <&state_dpaux1_aux>; 1081 pinctrl-1 = <&state_dpaux1_i2c>; 1082 pinctrl-2 = <&state_dpaux1_off>; 1083 pinctrl-names = "aux", "i2c", "off"; 1084 status = "disabled"; 1085 1086 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1087 nvidia,interface = <1>; 1088 }; 1089 1090 dpaux: dpaux@155c0000 { 1091 compatible = "nvidia,tegra186-dpaux"; 1092 reg = <0x155c0000 0x10000>; 1093 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1094 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1095 <&bpmp TEGRA186_CLK_PLLDP>; 1096 clock-names = "dpaux", "parent"; 1097 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1098 reset-names = "dpaux"; 1099 status = "disabled"; 1100 1101 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1102 1103 state_dpaux_aux: pinmux-aux { 1104 groups = "dpaux-io"; 1105 function = "aux"; 1106 }; 1107 1108 state_dpaux_i2c: pinmux-i2c { 1109 groups = "dpaux-io"; 1110 function = "i2c"; 1111 }; 1112 1113 state_dpaux_off: pinmux-off { 1114 groups = "dpaux-io"; 1115 function = "off"; 1116 }; 1117 1118 i2c-bus { 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 }; 1122 }; 1123 1124 padctl@15880000 { 1125 compatible = "nvidia,tegra186-dsi-padctl"; 1126 reg = <0x15880000 0x10000>; 1127 resets = <&bpmp TEGRA186_RESET_DSI>; 1128 reset-names = "dsi"; 1129 status = "disabled"; 1130 }; 1131 1132 dsic: dsi@15900000 { 1133 compatible = "nvidia,tegra186-dsi"; 1134 reg = <0x15900000 0x10000>; 1135 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1137 <&bpmp TEGRA186_CLK_DSIC_LP>, 1138 <&bpmp TEGRA186_CLK_PLLD>; 1139 clock-names = "dsi", "lp", "parent"; 1140 resets = <&bpmp TEGRA186_RESET_DSIC>; 1141 reset-names = "dsi"; 1142 status = "disabled"; 1143 1144 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1145 }; 1146 1147 dsid: dsi@15940000 { 1148 compatible = "nvidia,tegra186-dsi"; 1149 reg = <0x15940000 0x10000>; 1150 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1151 clocks = <&bpmp TEGRA186_CLK_DSID>, 1152 <&bpmp TEGRA186_CLK_DSID_LP>, 1153 <&bpmp TEGRA186_CLK_PLLD>; 1154 clock-names = "dsi", "lp", "parent"; 1155 resets = <&bpmp TEGRA186_RESET_DSID>; 1156 reset-names = "dsi"; 1157 status = "disabled"; 1158 1159 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1160 }; 1161 }; 1162 1163 gpu@17000000 { 1164 compatible = "nvidia,gp10b"; 1165 reg = <0x0 0x17000000 0x0 0x1000000>, 1166 <0x0 0x18000000 0x0 0x1000000>; 1167 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 1168 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1169 interrupt-names = "stall", "nonstall"; 1170 1171 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1172 <&bpmp TEGRA186_CLK_GPU>; 1173 clock-names = "gpu", "pwr"; 1174 resets = <&bpmp TEGRA186_RESET_GPU>; 1175 reset-names = "gpu"; 1176 status = "disabled"; 1177 1178 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1179 }; 1180 1181 sysram@30000000 { 1182 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1183 reg = <0x0 0x30000000 0x0 0x50000>; 1184 #address-cells = <2>; 1185 #size-cells = <2>; 1186 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 1187 1188 cpu_bpmp_tx: shmem@4e000 { 1189 compatible = "nvidia,tegra186-bpmp-shmem"; 1190 reg = <0x0 0x4e000 0x0 0x1000>; 1191 label = "cpu-bpmp-tx"; 1192 pool; 1193 }; 1194 1195 cpu_bpmp_rx: shmem@4f000 { 1196 compatible = "nvidia,tegra186-bpmp-shmem"; 1197 reg = <0x0 0x4f000 0x0 0x1000>; 1198 label = "cpu-bpmp-rx"; 1199 pool; 1200 }; 1201 }; 1202 1203 bpmp: bpmp { 1204 compatible = "nvidia,tegra186-bpmp"; 1205 iommus = <&smmu TEGRA186_SID_BPMP>; 1206 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1207 TEGRA_HSP_DB_MASTER_BPMP>; 1208 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1209 #clock-cells = <1>; 1210 #reset-cells = <1>; 1211 #power-domain-cells = <1>; 1212 1213 bpmp_i2c: i2c { 1214 compatible = "nvidia,tegra186-bpmp-i2c"; 1215 nvidia,bpmp-bus-id = <5>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 status = "disabled"; 1219 }; 1220 1221 bpmp_thermal: thermal { 1222 compatible = "nvidia,tegra186-bpmp-thermal"; 1223 #thermal-sensor-cells = <1>; 1224 }; 1225 }; 1226 1227 cpus { 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 1231 cpu@0 { 1232 compatible = "nvidia,tegra186-denver"; 1233 device_type = "cpu"; 1234 i-cache-size = <0x20000>; 1235 i-cache-line-size = <64>; 1236 i-cache-sets = <512>; 1237 d-cache-size = <0x10000>; 1238 d-cache-line-size = <64>; 1239 d-cache-sets = <256>; 1240 next-level-cache = <&L2_DENVER>; 1241 reg = <0x000>; 1242 }; 1243 1244 cpu@1 { 1245 compatible = "nvidia,tegra186-denver"; 1246 device_type = "cpu"; 1247 i-cache-size = <0x20000>; 1248 i-cache-line-size = <64>; 1249 i-cache-sets = <512>; 1250 d-cache-size = <0x10000>; 1251 d-cache-line-size = <64>; 1252 d-cache-sets = <256>; 1253 next-level-cache = <&L2_DENVER>; 1254 reg = <0x001>; 1255 }; 1256 1257 cpu@2 { 1258 compatible = "arm,cortex-a57"; 1259 device_type = "cpu"; 1260 i-cache-size = <0xC000>; 1261 i-cache-line-size = <64>; 1262 i-cache-sets = <256>; 1263 d-cache-size = <0x8000>; 1264 d-cache-line-size = <64>; 1265 d-cache-sets = <256>; 1266 next-level-cache = <&L2_A57>; 1267 reg = <0x100>; 1268 }; 1269 1270 cpu@3 { 1271 compatible = "arm,cortex-a57"; 1272 device_type = "cpu"; 1273 i-cache-size = <0xC000>; 1274 i-cache-line-size = <64>; 1275 i-cache-sets = <256>; 1276 d-cache-size = <0x8000>; 1277 d-cache-line-size = <64>; 1278 d-cache-sets = <256>; 1279 next-level-cache = <&L2_A57>; 1280 reg = <0x101>; 1281 }; 1282 1283 cpu@4 { 1284 compatible = "arm,cortex-a57"; 1285 device_type = "cpu"; 1286 i-cache-size = <0xC000>; 1287 i-cache-line-size = <64>; 1288 i-cache-sets = <256>; 1289 d-cache-size = <0x8000>; 1290 d-cache-line-size = <64>; 1291 d-cache-sets = <256>; 1292 next-level-cache = <&L2_A57>; 1293 reg = <0x102>; 1294 }; 1295 1296 cpu@5 { 1297 compatible = "arm,cortex-a57"; 1298 device_type = "cpu"; 1299 i-cache-size = <0xC000>; 1300 i-cache-line-size = <64>; 1301 i-cache-sets = <256>; 1302 d-cache-size = <0x8000>; 1303 d-cache-line-size = <64>; 1304 d-cache-sets = <256>; 1305 next-level-cache = <&L2_A57>; 1306 reg = <0x103>; 1307 }; 1308 1309 L2_DENVER: l2-cache0 { 1310 compatible = "cache"; 1311 cache-unified; 1312 cache-level = <2>; 1313 cache-size = <0x200000>; 1314 cache-line-size = <64>; 1315 cache-sets = <2048>; 1316 }; 1317 1318 L2_A57: l2-cache1 { 1319 compatible = "cache"; 1320 cache-unified; 1321 cache-level = <2>; 1322 cache-size = <0x200000>; 1323 cache-line-size = <64>; 1324 cache-sets = <2048>; 1325 }; 1326 }; 1327 1328 thermal-zones { 1329 a57 { 1330 polling-delay = <0>; 1331 polling-delay-passive = <1000>; 1332 1333 thermal-sensors = 1334 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1335 1336 trips { 1337 critical { 1338 temperature = <101000>; 1339 hysteresis = <0>; 1340 type = "critical"; 1341 }; 1342 }; 1343 1344 cooling-maps { 1345 }; 1346 }; 1347 1348 denver { 1349 polling-delay = <0>; 1350 polling-delay-passive = <1000>; 1351 1352 thermal-sensors = 1353 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1354 1355 trips { 1356 critical { 1357 temperature = <101000>; 1358 hysteresis = <0>; 1359 type = "critical"; 1360 }; 1361 }; 1362 1363 cooling-maps { 1364 }; 1365 }; 1366 1367 gpu { 1368 polling-delay = <0>; 1369 polling-delay-passive = <1000>; 1370 1371 thermal-sensors = 1372 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1373 1374 trips { 1375 critical { 1376 temperature = <101000>; 1377 hysteresis = <0>; 1378 type = "critical"; 1379 }; 1380 }; 1381 1382 cooling-maps { 1383 }; 1384 }; 1385 1386 pll { 1387 polling-delay = <0>; 1388 polling-delay-passive = <1000>; 1389 1390 thermal-sensors = 1391 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1392 1393 trips { 1394 critical { 1395 temperature = <101000>; 1396 hysteresis = <0>; 1397 type = "critical"; 1398 }; 1399 }; 1400 1401 cooling-maps { 1402 }; 1403 }; 1404 1405 always_on { 1406 polling-delay = <0>; 1407 polling-delay-passive = <1000>; 1408 1409 thermal-sensors = 1410 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1411 1412 trips { 1413 critical { 1414 temperature = <101000>; 1415 hysteresis = <0>; 1416 type = "critical"; 1417 }; 1418 }; 1419 1420 cooling-maps { 1421 }; 1422 }; 1423 }; 1424 1425 timer { 1426 compatible = "arm,armv8-timer"; 1427 interrupts = <GIC_PPI 13 1428 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1429 <GIC_PPI 14 1430 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1431 <GIC_PPI 11 1432 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1433 <GIC_PPI 10 1434 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1435 interrupt-parent = <&gic>; 1436 always-on; 1437 }; 1438}; 1439