1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * HD audio interface patch for Creative CA0132 chip
4 *
5 * Copyright (c) 2011, Creative Technology Ltd.
6 *
7 * Based on patch_ca0110.c
8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
9 */
10
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/mutex.h>
15 #include <linux/module.h>
16 #include <linux/firmware.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/io.h>
20 #include <linux/pci.h>
21 #include <asm/io.h>
22 #include <sound/core.h>
23 #include <sound/hda_codec.h>
24 #include "hda_local.h"
25 #include "hda_auto_parser.h"
26 #include "hda_jack.h"
27
28 #include "ca0132_regs.h"
29
30 /* Enable this to see controls for tuning purpose. */
31 /*#define ENABLE_TUNING_CONTROLS*/
32
33 #ifdef ENABLE_TUNING_CONTROLS
34 #include <sound/tlv.h>
35 #endif
36
37 #define FLOAT_ZERO 0x00000000
38 #define FLOAT_ONE 0x3f800000
39 #define FLOAT_TWO 0x40000000
40 #define FLOAT_THREE 0x40400000
41 #define FLOAT_EIGHT 0x41000000
42 #define FLOAT_MINUS_5 0xc0a00000
43
44 #define UNSOL_TAG_DSP 0x16
45
46 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
47 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
48
49 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
50 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
51 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
52
53 #define MASTERCONTROL 0x80
54 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
55 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
56
57 #define WIDGET_CHIP_CTRL 0x15
58 #define WIDGET_DSP_CTRL 0x16
59
60 #define MEM_CONNID_MICIN1 3
61 #define MEM_CONNID_MICIN2 5
62 #define MEM_CONNID_MICOUT1 12
63 #define MEM_CONNID_MICOUT2 14
64 #define MEM_CONNID_WUH 10
65 #define MEM_CONNID_DSP 16
66 #define MEM_CONNID_DMIC 100
67
68 #define SCP_SET 0
69 #define SCP_GET 1
70
71 #define EFX_FILE "ctefx.bin"
72 #define DESKTOP_EFX_FILE "ctefx-desktop.bin"
73 #define R3DI_EFX_FILE "ctefx-r3di.bin"
74
75 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
76 MODULE_FIRMWARE(EFX_FILE);
77 MODULE_FIRMWARE(DESKTOP_EFX_FILE);
78 MODULE_FIRMWARE(R3DI_EFX_FILE);
79 #endif
80
81 static const char *const dirstr[2] = { "Playback", "Capture" };
82
83 #define NUM_OF_OUTPUTS 3
84 enum {
85 SPEAKER_OUT,
86 HEADPHONE_OUT,
87 SURROUND_OUT
88 };
89
90 enum {
91 DIGITAL_MIC,
92 LINE_MIC_IN
93 };
94
95 /* Strings for Input Source Enum Control */
96 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
97 #define IN_SRC_NUM_OF_INPUTS 3
98 enum {
99 REAR_MIC,
100 REAR_LINE_IN,
101 FRONT_MIC,
102 };
103
104 enum {
105 #define VNODE_START_NID 0x80
106 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
107 VNID_MIC,
108 VNID_HP_SEL,
109 VNID_AMIC1_SEL,
110 VNID_HP_ASEL,
111 VNID_AMIC1_ASEL,
112 VNODE_END_NID,
113 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
114
115 #define EFFECT_START_NID 0x90
116 #define OUT_EFFECT_START_NID EFFECT_START_NID
117 SURROUND = OUT_EFFECT_START_NID,
118 CRYSTALIZER,
119 DIALOG_PLUS,
120 SMART_VOLUME,
121 X_BASS,
122 EQUALIZER,
123 OUT_EFFECT_END_NID,
124 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
125
126 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
127 ECHO_CANCELLATION = IN_EFFECT_START_NID,
128 VOICE_FOCUS,
129 MIC_SVM,
130 NOISE_REDUCTION,
131 IN_EFFECT_END_NID,
132 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
133
134 VOICEFX = IN_EFFECT_END_NID,
135 PLAY_ENHANCEMENT,
136 CRYSTAL_VOICE,
137 EFFECT_END_NID,
138 OUTPUT_SOURCE_ENUM,
139 INPUT_SOURCE_ENUM,
140 XBASS_XOVER,
141 EQ_PRESET_ENUM,
142 SMART_VOLUME_ENUM,
143 MIC_BOOST_ENUM,
144 AE5_HEADPHONE_GAIN_ENUM,
145 AE5_SOUND_FILTER_ENUM,
146 ZXR_HEADPHONE_GAIN
147 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
148 };
149
150 /* Effects values size*/
151 #define EFFECT_VALS_MAX_COUNT 12
152
153 /*
154 * Default values for the effect slider controls, they are in order of their
155 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
156 * X-bass.
157 */
158 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
159 /* Amount of effect level sliders for ca0132_alt controls. */
160 #define EFFECT_LEVEL_SLIDERS 5
161
162 /* Latency introduced by DSP blocks in milliseconds. */
163 #define DSP_CAPTURE_INIT_LATENCY 0
164 #define DSP_CRYSTAL_VOICE_LATENCY 124
165 #define DSP_PLAYBACK_INIT_LATENCY 13
166 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
167 #define DSP_SPEAKER_OUT_LATENCY 7
168
169 struct ct_effect {
170 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
171 hda_nid_t nid;
172 int mid; /*effect module ID*/
173 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
174 int direct; /* 0:output; 1:input*/
175 int params; /* number of default non-on/off params */
176 /*effect default values, 1st is on/off. */
177 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
178 };
179
180 #define EFX_DIR_OUT 0
181 #define EFX_DIR_IN 1
182
183 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
184 { .name = "Surround",
185 .nid = SURROUND,
186 .mid = 0x96,
187 .reqs = {0, 1},
188 .direct = EFX_DIR_OUT,
189 .params = 1,
190 .def_vals = {0x3F800000, 0x3F2B851F}
191 },
192 { .name = "Crystalizer",
193 .nid = CRYSTALIZER,
194 .mid = 0x96,
195 .reqs = {7, 8},
196 .direct = EFX_DIR_OUT,
197 .params = 1,
198 .def_vals = {0x3F800000, 0x3F266666}
199 },
200 { .name = "Dialog Plus",
201 .nid = DIALOG_PLUS,
202 .mid = 0x96,
203 .reqs = {2, 3},
204 .direct = EFX_DIR_OUT,
205 .params = 1,
206 .def_vals = {0x00000000, 0x3F000000}
207 },
208 { .name = "Smart Volume",
209 .nid = SMART_VOLUME,
210 .mid = 0x96,
211 .reqs = {4, 5, 6},
212 .direct = EFX_DIR_OUT,
213 .params = 2,
214 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
215 },
216 { .name = "X-Bass",
217 .nid = X_BASS,
218 .mid = 0x96,
219 .reqs = {24, 23, 25},
220 .direct = EFX_DIR_OUT,
221 .params = 2,
222 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
223 },
224 { .name = "Equalizer",
225 .nid = EQUALIZER,
226 .mid = 0x96,
227 .reqs = {9, 10, 11, 12, 13, 14,
228 15, 16, 17, 18, 19, 20},
229 .direct = EFX_DIR_OUT,
230 .params = 11,
231 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
232 0x00000000, 0x00000000, 0x00000000, 0x00000000,
233 0x00000000, 0x00000000, 0x00000000, 0x00000000}
234 },
235 { .name = "Echo Cancellation",
236 .nid = ECHO_CANCELLATION,
237 .mid = 0x95,
238 .reqs = {0, 1, 2, 3},
239 .direct = EFX_DIR_IN,
240 .params = 3,
241 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
242 },
243 { .name = "Voice Focus",
244 .nid = VOICE_FOCUS,
245 .mid = 0x95,
246 .reqs = {6, 7, 8, 9},
247 .direct = EFX_DIR_IN,
248 .params = 3,
249 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
250 },
251 { .name = "Mic SVM",
252 .nid = MIC_SVM,
253 .mid = 0x95,
254 .reqs = {44, 45},
255 .direct = EFX_DIR_IN,
256 .params = 1,
257 .def_vals = {0x00000000, 0x3F3D70A4}
258 },
259 { .name = "Noise Reduction",
260 .nid = NOISE_REDUCTION,
261 .mid = 0x95,
262 .reqs = {4, 5},
263 .direct = EFX_DIR_IN,
264 .params = 1,
265 .def_vals = {0x3F800000, 0x3F000000}
266 },
267 { .name = "VoiceFX",
268 .nid = VOICEFX,
269 .mid = 0x95,
270 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
271 .direct = EFX_DIR_IN,
272 .params = 8,
273 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
274 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
275 0x00000000}
276 }
277 };
278
279 /* Tuning controls */
280 #ifdef ENABLE_TUNING_CONTROLS
281
282 enum {
283 #define TUNING_CTL_START_NID 0xC0
284 WEDGE_ANGLE = TUNING_CTL_START_NID,
285 SVM_LEVEL,
286 EQUALIZER_BAND_0,
287 EQUALIZER_BAND_1,
288 EQUALIZER_BAND_2,
289 EQUALIZER_BAND_3,
290 EQUALIZER_BAND_4,
291 EQUALIZER_BAND_5,
292 EQUALIZER_BAND_6,
293 EQUALIZER_BAND_7,
294 EQUALIZER_BAND_8,
295 EQUALIZER_BAND_9,
296 TUNING_CTL_END_NID
297 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
298 };
299
300 struct ct_tuning_ctl {
301 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
302 hda_nid_t parent_nid;
303 hda_nid_t nid;
304 int mid; /*effect module ID*/
305 int req; /*effect module request*/
306 int direct; /* 0:output; 1:input*/
307 unsigned int def_val;/*effect default values*/
308 };
309
310 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
311 { .name = "Wedge Angle",
312 .parent_nid = VOICE_FOCUS,
313 .nid = WEDGE_ANGLE,
314 .mid = 0x95,
315 .req = 8,
316 .direct = EFX_DIR_IN,
317 .def_val = 0x41F00000
318 },
319 { .name = "SVM Level",
320 .parent_nid = MIC_SVM,
321 .nid = SVM_LEVEL,
322 .mid = 0x95,
323 .req = 45,
324 .direct = EFX_DIR_IN,
325 .def_val = 0x3F3D70A4
326 },
327 { .name = "EQ Band0",
328 .parent_nid = EQUALIZER,
329 .nid = EQUALIZER_BAND_0,
330 .mid = 0x96,
331 .req = 11,
332 .direct = EFX_DIR_OUT,
333 .def_val = 0x00000000
334 },
335 { .name = "EQ Band1",
336 .parent_nid = EQUALIZER,
337 .nid = EQUALIZER_BAND_1,
338 .mid = 0x96,
339 .req = 12,
340 .direct = EFX_DIR_OUT,
341 .def_val = 0x00000000
342 },
343 { .name = "EQ Band2",
344 .parent_nid = EQUALIZER,
345 .nid = EQUALIZER_BAND_2,
346 .mid = 0x96,
347 .req = 13,
348 .direct = EFX_DIR_OUT,
349 .def_val = 0x00000000
350 },
351 { .name = "EQ Band3",
352 .parent_nid = EQUALIZER,
353 .nid = EQUALIZER_BAND_3,
354 .mid = 0x96,
355 .req = 14,
356 .direct = EFX_DIR_OUT,
357 .def_val = 0x00000000
358 },
359 { .name = "EQ Band4",
360 .parent_nid = EQUALIZER,
361 .nid = EQUALIZER_BAND_4,
362 .mid = 0x96,
363 .req = 15,
364 .direct = EFX_DIR_OUT,
365 .def_val = 0x00000000
366 },
367 { .name = "EQ Band5",
368 .parent_nid = EQUALIZER,
369 .nid = EQUALIZER_BAND_5,
370 .mid = 0x96,
371 .req = 16,
372 .direct = EFX_DIR_OUT,
373 .def_val = 0x00000000
374 },
375 { .name = "EQ Band6",
376 .parent_nid = EQUALIZER,
377 .nid = EQUALIZER_BAND_6,
378 .mid = 0x96,
379 .req = 17,
380 .direct = EFX_DIR_OUT,
381 .def_val = 0x00000000
382 },
383 { .name = "EQ Band7",
384 .parent_nid = EQUALIZER,
385 .nid = EQUALIZER_BAND_7,
386 .mid = 0x96,
387 .req = 18,
388 .direct = EFX_DIR_OUT,
389 .def_val = 0x00000000
390 },
391 { .name = "EQ Band8",
392 .parent_nid = EQUALIZER,
393 .nid = EQUALIZER_BAND_8,
394 .mid = 0x96,
395 .req = 19,
396 .direct = EFX_DIR_OUT,
397 .def_val = 0x00000000
398 },
399 { .name = "EQ Band9",
400 .parent_nid = EQUALIZER,
401 .nid = EQUALIZER_BAND_9,
402 .mid = 0x96,
403 .req = 20,
404 .direct = EFX_DIR_OUT,
405 .def_val = 0x00000000
406 }
407 };
408 #endif
409
410 /* Voice FX Presets */
411 #define VOICEFX_MAX_PARAM_COUNT 9
412
413 struct ct_voicefx {
414 char *name;
415 hda_nid_t nid;
416 int mid;
417 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
418 };
419
420 struct ct_voicefx_preset {
421 char *name; /*preset name*/
422 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
423 };
424
425 static const struct ct_voicefx ca0132_voicefx = {
426 .name = "VoiceFX Capture Switch",
427 .nid = VOICEFX,
428 .mid = 0x95,
429 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
430 };
431
432 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
433 { .name = "Neutral",
434 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
435 0x44FA0000, 0x3F800000, 0x3F800000,
436 0x3F800000, 0x00000000, 0x00000000 }
437 },
438 { .name = "Female2Male",
439 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
440 0x44FA0000, 0x3F19999A, 0x3F866666,
441 0x3F800000, 0x00000000, 0x00000000 }
442 },
443 { .name = "Male2Female",
444 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
445 0x450AC000, 0x4017AE14, 0x3F6B851F,
446 0x3F800000, 0x00000000, 0x00000000 }
447 },
448 { .name = "ScrappyKid",
449 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
450 0x44FA0000, 0x40400000, 0x3F28F5C3,
451 0x3F800000, 0x00000000, 0x00000000 }
452 },
453 { .name = "Elderly",
454 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
455 0x44E10000, 0x3FB33333, 0x3FB9999A,
456 0x3F800000, 0x3E3A2E43, 0x00000000 }
457 },
458 { .name = "Orc",
459 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
460 0x45098000, 0x3F266666, 0x3FC00000,
461 0x3F800000, 0x00000000, 0x00000000 }
462 },
463 { .name = "Elf",
464 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
465 0x45193000, 0x3F8E147B, 0x3F75C28F,
466 0x3F800000, 0x00000000, 0x00000000 }
467 },
468 { .name = "Dwarf",
469 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
470 0x45007000, 0x3F451EB8, 0x3F7851EC,
471 0x3F800000, 0x00000000, 0x00000000 }
472 },
473 { .name = "AlienBrute",
474 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
475 0x451F6000, 0x3F266666, 0x3FA7D945,
476 0x3F800000, 0x3CF5C28F, 0x00000000 }
477 },
478 { .name = "Robot",
479 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
480 0x44FA0000, 0x3FB2718B, 0x3F800000,
481 0xBC07010E, 0x00000000, 0x00000000 }
482 },
483 { .name = "Marine",
484 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
485 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
486 0x3F0A3D71, 0x00000000, 0x00000000 }
487 },
488 { .name = "Emo",
489 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
490 0x44FA0000, 0x3F800000, 0x3F800000,
491 0x3E4CCCCD, 0x00000000, 0x00000000 }
492 },
493 { .name = "DeepVoice",
494 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
495 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
496 0x3F800000, 0x00000000, 0x00000000 }
497 },
498 { .name = "Munchkin",
499 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
500 0x44FA0000, 0x3F800000, 0x3F1A043C,
501 0x3F800000, 0x00000000, 0x00000000 }
502 }
503 };
504
505 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
506
507 #define EQ_PRESET_MAX_PARAM_COUNT 11
508
509 struct ct_eq {
510 char *name;
511 hda_nid_t nid;
512 int mid;
513 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
514 };
515
516 struct ct_eq_preset {
517 char *name; /*preset name*/
518 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
519 };
520
521 static const struct ct_eq ca0132_alt_eq_enum = {
522 .name = "FX: Equalizer Preset Switch",
523 .nid = EQ_PRESET_ENUM,
524 .mid = 0x96,
525 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
526 };
527
528
529 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
530 { .name = "Flat",
531 .vals = { 0x00000000, 0x00000000, 0x00000000,
532 0x00000000, 0x00000000, 0x00000000,
533 0x00000000, 0x00000000, 0x00000000,
534 0x00000000, 0x00000000 }
535 },
536 { .name = "Acoustic",
537 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
538 0x40000000, 0x00000000, 0x00000000,
539 0x00000000, 0x00000000, 0x40000000,
540 0x40000000, 0x40000000 }
541 },
542 { .name = "Classical",
543 .vals = { 0x00000000, 0x00000000, 0x40C00000,
544 0x40C00000, 0x40466666, 0x00000000,
545 0x00000000, 0x00000000, 0x00000000,
546 0x40466666, 0x40466666 }
547 },
548 { .name = "Country",
549 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
550 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
551 0x00000000, 0x00000000, 0x40000000,
552 0x40466666, 0x40800000 }
553 },
554 { .name = "Dance",
555 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
556 0x40466666, 0x40866666, 0xBF99999A,
557 0xBF99999A, 0x00000000, 0x00000000,
558 0x40800000, 0x40800000 }
559 },
560 { .name = "Jazz",
561 .vals = { 0x00000000, 0x00000000, 0x00000000,
562 0x3F8CCCCD, 0x40800000, 0x40800000,
563 0x40800000, 0x00000000, 0x3F8CCCCD,
564 0x40466666, 0x40466666 }
565 },
566 { .name = "New Age",
567 .vals = { 0x00000000, 0x00000000, 0x40000000,
568 0x40000000, 0x00000000, 0x00000000,
569 0x00000000, 0x3F8CCCCD, 0x40000000,
570 0x40000000, 0x40000000 }
571 },
572 { .name = "Pop",
573 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
574 0x40000000, 0x40000000, 0x00000000,
575 0xBF99999A, 0xBF99999A, 0x00000000,
576 0x40466666, 0x40C00000 }
577 },
578 { .name = "Rock",
579 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
580 0x3F8CCCCD, 0x40000000, 0xBF99999A,
581 0xBF99999A, 0x00000000, 0x00000000,
582 0x40800000, 0x40800000 }
583 },
584 { .name = "Vocal",
585 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
586 0xBF99999A, 0x00000000, 0x40466666,
587 0x40800000, 0x40466666, 0x00000000,
588 0x00000000, 0x3F8CCCCD }
589 }
590 };
591
592 /* DSP command sequences for ca0132_alt_select_out */
593 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
594 struct ca0132_alt_out_set {
595 char *name; /*preset name*/
596 unsigned char commands;
597 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
598 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
599 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
600 };
601
602 static const struct ca0132_alt_out_set alt_out_presets[] = {
603 { .name = "Line Out",
604 .commands = 7,
605 .mids = { 0x96, 0x96, 0x96, 0x8F,
606 0x96, 0x96, 0x96 },
607 .reqs = { 0x19, 0x17, 0x18, 0x01,
608 0x1F, 0x15, 0x3A },
609 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
610 0x00000000, 0x00000000, 0x00000000,
611 0x00000000 }
612 },
613 { .name = "Headphone",
614 .commands = 7,
615 .mids = { 0x96, 0x96, 0x96, 0x8F,
616 0x96, 0x96, 0x96 },
617 .reqs = { 0x19, 0x17, 0x18, 0x01,
618 0x1F, 0x15, 0x3A },
619 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
620 0x00000000, 0x00000000, 0x00000000,
621 0x00000000 }
622 },
623 { .name = "Surround",
624 .commands = 8,
625 .mids = { 0x96, 0x8F, 0x96, 0x96,
626 0x96, 0x96, 0x96, 0x96 },
627 .reqs = { 0x18, 0x01, 0x1F, 0x15,
628 0x3A, 0x1A, 0x1B, 0x1C },
629 .vals = { 0x00000000, 0x00000000, 0x00000000,
630 0x00000000, 0x00000000, 0x00000000,
631 0x00000000, 0x00000000 }
632 }
633 };
634
635 /*
636 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
637 * and I don't know what the third req is, but it's always zero. I assume it's
638 * some sort of update or set command to tell the DSP there's new volume info.
639 */
640 #define DSP_VOL_OUT 0
641 #define DSP_VOL_IN 1
642
643 struct ct_dsp_volume_ctl {
644 hda_nid_t vnid;
645 int mid; /* module ID*/
646 unsigned int reqs[3]; /* scp req ID */
647 };
648
649 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
650 { .vnid = VNID_SPK,
651 .mid = 0x32,
652 .reqs = {3, 4, 2}
653 },
654 { .vnid = VNID_MIC,
655 .mid = 0x37,
656 .reqs = {2, 3, 1}
657 }
658 };
659
660 /* Values for ca0113_mmio_command_set for selecting output. */
661 #define AE5_CA0113_OUT_SET_COMMANDS 6
662 struct ae5_ca0113_output_set {
663 unsigned int group[AE5_CA0113_OUT_SET_COMMANDS];
664 unsigned int target[AE5_CA0113_OUT_SET_COMMANDS];
665 unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS];
666 };
667
668 static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = {
669 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
670 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
671 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
672 },
673 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
674 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
675 .vals = { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 }
676 },
677 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
678 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
679 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
680 }
681 };
682
683 /* ae5 ca0113 command sequences to set headphone gain levels. */
684 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
685 struct ae5_headphone_gain_set {
686 char *name;
687 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
688 };
689
690 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
691 { .name = "Low (16-31",
692 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
693 },
694 { .name = "Medium (32-149",
695 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
696 },
697 { .name = "High (150-600",
698 .vals = { 0xff, 0xff, 0xff, 0x7f }
699 }
700 };
701
702 struct ae5_filter_set {
703 char *name;
704 unsigned int val;
705 };
706
707 static const struct ae5_filter_set ae5_filter_presets[] = {
708 { .name = "Slow Roll Off",
709 .val = 0xa0
710 },
711 { .name = "Minimum Phase",
712 .val = 0xc0
713 },
714 { .name = "Fast Roll Off",
715 .val = 0x80
716 }
717 };
718
719 enum hda_cmd_vendor_io {
720 /* for DspIO node */
721 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
722 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
723
724 VENDOR_DSPIO_STATUS = 0xF01,
725 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
726 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
727 VENDOR_DSPIO_DSP_INIT = 0x703,
728 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
729 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
730
731 /* for ChipIO node */
732 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
733 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
734 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
735 VENDOR_CHIPIO_DATA_LOW = 0x300,
736 VENDOR_CHIPIO_DATA_HIGH = 0x400,
737
738 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
739 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
740
741 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
742 VENDOR_CHIPIO_STATUS = 0xF01,
743 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
744 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
745
746 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
747 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
748 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
749 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
750 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
751
752 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
753 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
754
755 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
756 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
757 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
758 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
759 VENDOR_CHIPIO_FLAG_SET = 0x70F,
760 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
761 VENDOR_CHIPIO_PARAM_SET = 0x710,
762 VENDOR_CHIPIO_PARAM_GET = 0xF10,
763
764 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
765 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
766 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
767 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
768
769 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
770 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
771 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
772 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
773
774 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
775 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
776 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
777 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
778 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
779 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
780
781 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
782 };
783
784 /*
785 * Control flag IDs
786 */
787 enum control_flag_id {
788 /* Connection manager stream setup is bypassed/enabled */
789 CONTROL_FLAG_C_MGR = 0,
790 /* DSP DMA is bypassed/enabled */
791 CONTROL_FLAG_DMA = 1,
792 /* 8051 'idle' mode is disabled/enabled */
793 CONTROL_FLAG_IDLE_ENABLE = 2,
794 /* Tracker for the SPDIF-in path is bypassed/enabled */
795 CONTROL_FLAG_TRACKER = 3,
796 /* DigitalOut to Spdif2Out connection is disabled/enabled */
797 CONTROL_FLAG_SPDIF2OUT = 4,
798 /* Digital Microphone is disabled/enabled */
799 CONTROL_FLAG_DMIC = 5,
800 /* ADC_B rate is 48 kHz/96 kHz */
801 CONTROL_FLAG_ADC_B_96KHZ = 6,
802 /* ADC_C rate is 48 kHz/96 kHz */
803 CONTROL_FLAG_ADC_C_96KHZ = 7,
804 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
805 CONTROL_FLAG_DAC_96KHZ = 8,
806 /* DSP rate is 48 kHz/96 kHz */
807 CONTROL_FLAG_DSP_96KHZ = 9,
808 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
809 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
810 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
811 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
812 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
813 CONTROL_FLAG_DECODE_LOOP = 12,
814 /* De-emphasis filter on DAC-1 disabled/enabled */
815 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
816 /* De-emphasis filter on DAC-2 disabled/enabled */
817 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
818 /* De-emphasis filter on DAC-3 disabled/enabled */
819 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
820 /* High-pass filter on ADC_B disabled/enabled */
821 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
822 /* High-pass filter on ADC_C disabled/enabled */
823 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
824 /* Common mode on Port_A disabled/enabled */
825 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
826 /* Common mode on Port_D disabled/enabled */
827 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
828 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
829 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
830 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
831 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
832 /* ASI rate is 48kHz/96kHz */
833 CONTROL_FLAG_ASI_96KHZ = 22,
834 /* DAC power settings able to control attached ports no/yes */
835 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
836 /* Clock Stop OK reporting is disabled/enabled */
837 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
838 /* Number of control flags */
839 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
840 };
841
842 /*
843 * Control parameter IDs
844 */
845 enum control_param_id {
846 /* 0: None, 1: Mic1In*/
847 CONTROL_PARAM_VIP_SOURCE = 1,
848 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
849 CONTROL_PARAM_SPDIF1_SOURCE = 2,
850 /* Port A output stage gain setting to use when 16 Ohm output
851 * impedance is selected*/
852 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
853 /* Port D output stage gain setting to use when 16 Ohm output
854 * impedance is selected*/
855 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
856
857 /*
858 * This control param name was found in the 8051 memory, and makes
859 * sense given the fact the AE-5 uses it and has the ASI flag set.
860 */
861 CONTROL_PARAM_ASI = 23,
862
863 /* Stream Control */
864
865 /* Select stream with the given ID */
866 CONTROL_PARAM_STREAM_ID = 24,
867 /* Source connection point for the selected stream */
868 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
869 /* Destination connection point for the selected stream */
870 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
871 /* Number of audio channels in the selected stream */
872 CONTROL_PARAM_STREAMS_CHANNELS = 27,
873 /*Enable control for the selected stream */
874 CONTROL_PARAM_STREAM_CONTROL = 28,
875
876 /* Connection Point Control */
877
878 /* Select connection point with the given ID */
879 CONTROL_PARAM_CONN_POINT_ID = 29,
880 /* Connection point sample rate */
881 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
882
883 /* Node Control */
884
885 /* Select HDA node with the given ID */
886 CONTROL_PARAM_NODE_ID = 31
887 };
888
889 /*
890 * Dsp Io Status codes
891 */
892 enum hda_vendor_status_dspio {
893 /* Success */
894 VENDOR_STATUS_DSPIO_OK = 0x00,
895 /* Busy, unable to accept new command, the host must retry */
896 VENDOR_STATUS_DSPIO_BUSY = 0x01,
897 /* SCP command queue is full */
898 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
899 /* SCP response queue is empty */
900 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
901 };
902
903 /*
904 * Chip Io Status codes
905 */
906 enum hda_vendor_status_chipio {
907 /* Success */
908 VENDOR_STATUS_CHIPIO_OK = 0x00,
909 /* Busy, unable to accept new command, the host must retry */
910 VENDOR_STATUS_CHIPIO_BUSY = 0x01
911 };
912
913 /*
914 * CA0132 sample rate
915 */
916 enum ca0132_sample_rate {
917 SR_6_000 = 0x00,
918 SR_8_000 = 0x01,
919 SR_9_600 = 0x02,
920 SR_11_025 = 0x03,
921 SR_16_000 = 0x04,
922 SR_22_050 = 0x05,
923 SR_24_000 = 0x06,
924 SR_32_000 = 0x07,
925 SR_44_100 = 0x08,
926 SR_48_000 = 0x09,
927 SR_88_200 = 0x0A,
928 SR_96_000 = 0x0B,
929 SR_144_000 = 0x0C,
930 SR_176_400 = 0x0D,
931 SR_192_000 = 0x0E,
932 SR_384_000 = 0x0F,
933
934 SR_COUNT = 0x10,
935
936 SR_RATE_UNKNOWN = 0x1F
937 };
938
939 enum dsp_download_state {
940 DSP_DOWNLOAD_FAILED = -1,
941 DSP_DOWNLOAD_INIT = 0,
942 DSP_DOWNLOADING = 1,
943 DSP_DOWNLOADED = 2
944 };
945
946 /* retrieve parameters from hda format */
947 #define get_hdafmt_chs(fmt) (fmt & 0xf)
948 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
949 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
950 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
951
952 /*
953 * CA0132 specific
954 */
955
956 struct ca0132_spec {
957 const struct snd_kcontrol_new *mixers[5];
958 unsigned int num_mixers;
959 const struct hda_verb *base_init_verbs;
960 const struct hda_verb *base_exit_verbs;
961 const struct hda_verb *chip_init_verbs;
962 const struct hda_verb *desktop_init_verbs;
963 struct hda_verb *spec_init_verbs;
964 struct auto_pin_cfg autocfg;
965
966 /* Nodes configurations */
967 struct hda_multi_out multiout;
968 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
969 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
970 unsigned int num_outputs;
971 hda_nid_t input_pins[AUTO_PIN_LAST];
972 hda_nid_t adcs[AUTO_PIN_LAST];
973 hda_nid_t dig_out;
974 hda_nid_t dig_in;
975 unsigned int num_inputs;
976 hda_nid_t shared_mic_nid;
977 hda_nid_t shared_out_nid;
978 hda_nid_t unsol_tag_hp;
979 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
980 hda_nid_t unsol_tag_amic1;
981
982 /* chip access */
983 struct mutex chipio_mutex; /* chip access mutex */
984 u32 curr_chip_addx;
985
986 /* DSP download related */
987 enum dsp_download_state dsp_state;
988 unsigned int dsp_stream_id;
989 unsigned int wait_scp;
990 unsigned int wait_scp_header;
991 unsigned int wait_num_data;
992 unsigned int scp_resp_header;
993 unsigned int scp_resp_data[4];
994 unsigned int scp_resp_count;
995 bool startup_check_entered;
996 bool dsp_reload;
997
998 /* mixer and effects related */
999 unsigned char dmic_ctl;
1000 int cur_out_type;
1001 int cur_mic_type;
1002 long vnode_lvol[VNODES_COUNT];
1003 long vnode_rvol[VNODES_COUNT];
1004 long vnode_lswitch[VNODES_COUNT];
1005 long vnode_rswitch[VNODES_COUNT];
1006 long effects_switch[EFFECTS_COUNT];
1007 long voicefx_val;
1008 long cur_mic_boost;
1009 /* ca0132_alt control related values */
1010 unsigned char in_enum_val;
1011 unsigned char out_enum_val;
1012 unsigned char mic_boost_enum_val;
1013 unsigned char smart_volume_setting;
1014 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1015 long xbass_xover_freq;
1016 long eq_preset_val;
1017 unsigned int tlv[4];
1018 struct hda_vmaster_mute_hook vmaster_mute;
1019 /* AE-5 Control values */
1020 unsigned char ae5_headphone_gain_val;
1021 unsigned char ae5_filter_val;
1022 /* ZxR Control Values */
1023 unsigned char zxr_gain_set;
1024
1025 struct hda_codec *codec;
1026 struct delayed_work unsol_hp_work;
1027 int quirk;
1028
1029 #ifdef ENABLE_TUNING_CONTROLS
1030 long cur_ctl_vals[TUNING_CTLS_COUNT];
1031 #endif
1032 /*
1033 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1034 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1035 * things.
1036 */
1037 bool use_pci_mmio;
1038 void __iomem *mem_base;
1039
1040 /*
1041 * Whether or not to use the alt functions like alt_select_out,
1042 * alt_select_in, etc. Only used on desktop codecs for now, because of
1043 * surround sound support.
1044 */
1045 bool use_alt_functions;
1046
1047 /*
1048 * Whether or not to use alt controls: volume effect sliders, EQ
1049 * presets, smart volume presets, and new control names with FX prefix.
1050 * Renames PlayEnhancement and CrystalVoice too.
1051 */
1052 bool use_alt_controls;
1053 };
1054
1055 /*
1056 * CA0132 quirks table
1057 */
1058 enum {
1059 QUIRK_NONE,
1060 QUIRK_ALIENWARE,
1061 QUIRK_ALIENWARE_M17XR4,
1062 QUIRK_SBZ,
1063 QUIRK_ZXR,
1064 QUIRK_ZXR_DBPRO,
1065 QUIRK_R3DI,
1066 QUIRK_R3D,
1067 QUIRK_AE5,
1068 QUIRK_AE7,
1069 };
1070
1071 #ifdef CONFIG_PCI
1072 #define ca0132_quirk(spec) ((spec)->quirk)
1073 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio)
1074 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions)
1075 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls)
1076 #else
1077 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; })
1078 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; })
1079 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; })
1080 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; })
1081 #endif
1082
1083 static const struct hda_pintbl alienware_pincfgs[] = {
1084 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1085 { 0x0c, 0x411111f0 }, /* N/A */
1086 { 0x0d, 0x411111f0 }, /* N/A */
1087 { 0x0e, 0x411111f0 }, /* N/A */
1088 { 0x0f, 0x0321101f }, /* HP */
1089 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1090 { 0x11, 0x03a11021 }, /* Mic */
1091 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1092 { 0x13, 0x411111f0 }, /* N/A */
1093 { 0x18, 0x411111f0 }, /* N/A */
1094 {}
1095 };
1096
1097 /* Sound Blaster Z pin configs taken from Windows Driver */
1098 static const struct hda_pintbl sbz_pincfgs[] = {
1099 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1100 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1101 { 0x0d, 0x014510f0 }, /* Digital Out */
1102 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1103 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1104 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1105 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1106 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1107 { 0x13, 0x908700f0 }, /* What U Hear In*/
1108 { 0x18, 0x50d000f0 }, /* N/A */
1109 {}
1110 };
1111
1112 /* Sound Blaster ZxR pin configs taken from Windows Driver */
1113 static const struct hda_pintbl zxr_pincfgs[] = {
1114 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1115 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1116 { 0x0d, 0x014510f0 }, /* Digital Out */
1117 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1118 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1119 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1120 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1121 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1122 { 0x13, 0x908700f0 }, /* What U Hear In*/
1123 { 0x18, 0x50d000f0 }, /* N/A */
1124 {}
1125 };
1126
1127 /* Recon3D pin configs taken from Windows Driver */
1128 static const struct hda_pintbl r3d_pincfgs[] = {
1129 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1130 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1131 { 0x0d, 0x014510f0 }, /* Digital Out */
1132 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1133 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1134 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1135 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1136 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1137 { 0x13, 0x908700f0 }, /* What U Hear In*/
1138 { 0x18, 0x50d000f0 }, /* N/A */
1139 {}
1140 };
1141
1142 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1143 static const struct hda_pintbl ae5_pincfgs[] = {
1144 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1145 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1146 { 0x0d, 0x014510f0 }, /* Digital Out */
1147 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1148 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1149 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1150 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1151 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1152 { 0x13, 0x908700f0 }, /* What U Hear In*/
1153 { 0x18, 0x50d000f0 }, /* N/A */
1154 {}
1155 };
1156
1157 /* Recon3D integrated pin configs taken from Windows Driver */
1158 static const struct hda_pintbl r3di_pincfgs[] = {
1159 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1160 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1161 { 0x0d, 0x014510f0 }, /* Digital Out */
1162 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1163 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1164 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1165 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1166 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1167 { 0x13, 0x908700f0 }, /* What U Hear In*/
1168 { 0x18, 0x500000f0 }, /* N/A */
1169 {}
1170 };
1171
1172 static const struct snd_pci_quirk ca0132_quirks[] = {
1173 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1174 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1175 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1176 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1177 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1178 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1179 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1180 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1181 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1182 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1183 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1184 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1185 SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI),
1186 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1187 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1188 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1189 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1190 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1191 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1192 {}
1193 };
1194
1195 /*
1196 * CA0132 codec access
1197 */
codec_send_command(struct hda_codec * codec,hda_nid_t nid,unsigned int verb,unsigned int parm,unsigned int * res)1198 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1199 unsigned int verb, unsigned int parm, unsigned int *res)
1200 {
1201 unsigned int response;
1202 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1203 *res = response;
1204
1205 return ((response == -1) ? -1 : 0);
1206 }
1207
codec_set_converter_format(struct hda_codec * codec,hda_nid_t nid,unsigned short converter_format,unsigned int * res)1208 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1209 unsigned short converter_format, unsigned int *res)
1210 {
1211 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1212 converter_format & 0xffff, res);
1213 }
1214
codec_set_converter_stream_channel(struct hda_codec * codec,hda_nid_t nid,unsigned char stream,unsigned char channel,unsigned int * res)1215 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1216 hda_nid_t nid, unsigned char stream,
1217 unsigned char channel, unsigned int *res)
1218 {
1219 unsigned char converter_stream_channel = 0;
1220
1221 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1222 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1223 converter_stream_channel, res);
1224 }
1225
1226 /* Chip access helper function */
chipio_send(struct hda_codec * codec,unsigned int reg,unsigned int data)1227 static int chipio_send(struct hda_codec *codec,
1228 unsigned int reg,
1229 unsigned int data)
1230 {
1231 unsigned int res;
1232 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1233
1234 /* send bits of data specified by reg */
1235 do {
1236 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1237 reg, data);
1238 if (res == VENDOR_STATUS_CHIPIO_OK)
1239 return 0;
1240 msleep(20);
1241 } while (time_before(jiffies, timeout));
1242
1243 return -EIO;
1244 }
1245
1246 /*
1247 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1248 */
chipio_write_address(struct hda_codec * codec,unsigned int chip_addx)1249 static int chipio_write_address(struct hda_codec *codec,
1250 unsigned int chip_addx)
1251 {
1252 struct ca0132_spec *spec = codec->spec;
1253 int res;
1254
1255 if (spec->curr_chip_addx == chip_addx)
1256 return 0;
1257
1258 /* send low 16 bits of the address */
1259 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1260 chip_addx & 0xffff);
1261
1262 if (res != -EIO) {
1263 /* send high 16 bits of the address */
1264 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1265 chip_addx >> 16);
1266 }
1267
1268 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1269
1270 return res;
1271 }
1272
1273 /*
1274 * Write data through the vendor widget -- NOT protected by the Mutex!
1275 */
chipio_write_data(struct hda_codec * codec,unsigned int data)1276 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1277 {
1278 struct ca0132_spec *spec = codec->spec;
1279 int res;
1280
1281 /* send low 16 bits of the data */
1282 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1283
1284 if (res != -EIO) {
1285 /* send high 16 bits of the data */
1286 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1287 data >> 16);
1288 }
1289
1290 /*If no error encountered, automatically increment the address
1291 as per chip behaviour*/
1292 spec->curr_chip_addx = (res != -EIO) ?
1293 (spec->curr_chip_addx + 4) : ~0U;
1294 return res;
1295 }
1296
1297 /*
1298 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1299 */
chipio_write_data_multiple(struct hda_codec * codec,const u32 * data,unsigned int count)1300 static int chipio_write_data_multiple(struct hda_codec *codec,
1301 const u32 *data,
1302 unsigned int count)
1303 {
1304 int status = 0;
1305
1306 if (data == NULL) {
1307 codec_dbg(codec, "chipio_write_data null ptr\n");
1308 return -EINVAL;
1309 }
1310
1311 while ((count-- != 0) && (status == 0))
1312 status = chipio_write_data(codec, *data++);
1313
1314 return status;
1315 }
1316
1317
1318 /*
1319 * Read data through the vendor widget -- NOT protected by the Mutex!
1320 */
chipio_read_data(struct hda_codec * codec,unsigned int * data)1321 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1322 {
1323 struct ca0132_spec *spec = codec->spec;
1324 int res;
1325
1326 /* post read */
1327 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1328
1329 if (res != -EIO) {
1330 /* read status */
1331 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1332 }
1333
1334 if (res != -EIO) {
1335 /* read data */
1336 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1337 VENDOR_CHIPIO_HIC_READ_DATA,
1338 0);
1339 }
1340
1341 /*If no error encountered, automatically increment the address
1342 as per chip behaviour*/
1343 spec->curr_chip_addx = (res != -EIO) ?
1344 (spec->curr_chip_addx + 4) : ~0U;
1345 return res;
1346 }
1347
1348 /*
1349 * Write given value to the given address through the chip I/O widget.
1350 * protected by the Mutex
1351 */
chipio_write(struct hda_codec * codec,unsigned int chip_addx,const unsigned int data)1352 static int chipio_write(struct hda_codec *codec,
1353 unsigned int chip_addx, const unsigned int data)
1354 {
1355 struct ca0132_spec *spec = codec->spec;
1356 int err;
1357
1358 mutex_lock(&spec->chipio_mutex);
1359
1360 /* write the address, and if successful proceed to write data */
1361 err = chipio_write_address(codec, chip_addx);
1362 if (err < 0)
1363 goto exit;
1364
1365 err = chipio_write_data(codec, data);
1366 if (err < 0)
1367 goto exit;
1368
1369 exit:
1370 mutex_unlock(&spec->chipio_mutex);
1371 return err;
1372 }
1373
1374 /*
1375 * Write given value to the given address through the chip I/O widget.
1376 * not protected by the Mutex
1377 */
chipio_write_no_mutex(struct hda_codec * codec,unsigned int chip_addx,const unsigned int data)1378 static int chipio_write_no_mutex(struct hda_codec *codec,
1379 unsigned int chip_addx, const unsigned int data)
1380 {
1381 int err;
1382
1383
1384 /* write the address, and if successful proceed to write data */
1385 err = chipio_write_address(codec, chip_addx);
1386 if (err < 0)
1387 goto exit;
1388
1389 err = chipio_write_data(codec, data);
1390 if (err < 0)
1391 goto exit;
1392
1393 exit:
1394 return err;
1395 }
1396
1397 /*
1398 * Write multiple values to the given address through the chip I/O widget.
1399 * protected by the Mutex
1400 */
chipio_write_multiple(struct hda_codec * codec,u32 chip_addx,const u32 * data,unsigned int count)1401 static int chipio_write_multiple(struct hda_codec *codec,
1402 u32 chip_addx,
1403 const u32 *data,
1404 unsigned int count)
1405 {
1406 struct ca0132_spec *spec = codec->spec;
1407 int status;
1408
1409 mutex_lock(&spec->chipio_mutex);
1410 status = chipio_write_address(codec, chip_addx);
1411 if (status < 0)
1412 goto error;
1413
1414 status = chipio_write_data_multiple(codec, data, count);
1415 error:
1416 mutex_unlock(&spec->chipio_mutex);
1417
1418 return status;
1419 }
1420
1421 /*
1422 * Read the given address through the chip I/O widget
1423 * protected by the Mutex
1424 */
chipio_read(struct hda_codec * codec,unsigned int chip_addx,unsigned int * data)1425 static int chipio_read(struct hda_codec *codec,
1426 unsigned int chip_addx, unsigned int *data)
1427 {
1428 struct ca0132_spec *spec = codec->spec;
1429 int err;
1430
1431 mutex_lock(&spec->chipio_mutex);
1432
1433 /* write the address, and if successful proceed to write data */
1434 err = chipio_write_address(codec, chip_addx);
1435 if (err < 0)
1436 goto exit;
1437
1438 err = chipio_read_data(codec, data);
1439 if (err < 0)
1440 goto exit;
1441
1442 exit:
1443 mutex_unlock(&spec->chipio_mutex);
1444 return err;
1445 }
1446
1447 /*
1448 * Set chip control flags through the chip I/O widget.
1449 */
chipio_set_control_flag(struct hda_codec * codec,enum control_flag_id flag_id,bool flag_state)1450 static void chipio_set_control_flag(struct hda_codec *codec,
1451 enum control_flag_id flag_id,
1452 bool flag_state)
1453 {
1454 unsigned int val;
1455 unsigned int flag_bit;
1456
1457 flag_bit = (flag_state ? 1 : 0);
1458 val = (flag_bit << 7) | (flag_id);
1459 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1460 VENDOR_CHIPIO_FLAG_SET, val);
1461 }
1462
1463 /*
1464 * Set chip parameters through the chip I/O widget.
1465 */
chipio_set_control_param(struct hda_codec * codec,enum control_param_id param_id,int param_val)1466 static void chipio_set_control_param(struct hda_codec *codec,
1467 enum control_param_id param_id, int param_val)
1468 {
1469 struct ca0132_spec *spec = codec->spec;
1470 int val;
1471
1472 if ((param_id < 32) && (param_val < 8)) {
1473 val = (param_val << 5) | (param_id);
1474 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1475 VENDOR_CHIPIO_PARAM_SET, val);
1476 } else {
1477 mutex_lock(&spec->chipio_mutex);
1478 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1479 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1480 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1481 param_id);
1482 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1483 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1484 param_val);
1485 }
1486 mutex_unlock(&spec->chipio_mutex);
1487 }
1488 }
1489
1490 /*
1491 * Set chip parameters through the chip I/O widget. NO MUTEX.
1492 */
chipio_set_control_param_no_mutex(struct hda_codec * codec,enum control_param_id param_id,int param_val)1493 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1494 enum control_param_id param_id, int param_val)
1495 {
1496 int val;
1497
1498 if ((param_id < 32) && (param_val < 8)) {
1499 val = (param_val << 5) | (param_id);
1500 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1501 VENDOR_CHIPIO_PARAM_SET, val);
1502 } else {
1503 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1504 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1505 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1506 param_id);
1507 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1508 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1509 param_val);
1510 }
1511 }
1512 }
1513 /*
1514 * Connect stream to a source point, and then connect
1515 * that source point to a destination point.
1516 */
chipio_set_stream_source_dest(struct hda_codec * codec,int streamid,int source_point,int dest_point)1517 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1518 int streamid, int source_point, int dest_point)
1519 {
1520 chipio_set_control_param_no_mutex(codec,
1521 CONTROL_PARAM_STREAM_ID, streamid);
1522 chipio_set_control_param_no_mutex(codec,
1523 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1524 chipio_set_control_param_no_mutex(codec,
1525 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1526 }
1527
1528 /*
1529 * Set number of channels in the selected stream.
1530 */
chipio_set_stream_channels(struct hda_codec * codec,int streamid,unsigned int channels)1531 static void chipio_set_stream_channels(struct hda_codec *codec,
1532 int streamid, unsigned int channels)
1533 {
1534 chipio_set_control_param_no_mutex(codec,
1535 CONTROL_PARAM_STREAM_ID, streamid);
1536 chipio_set_control_param_no_mutex(codec,
1537 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1538 }
1539
1540 /*
1541 * Enable/Disable audio stream.
1542 */
chipio_set_stream_control(struct hda_codec * codec,int streamid,int enable)1543 static void chipio_set_stream_control(struct hda_codec *codec,
1544 int streamid, int enable)
1545 {
1546 chipio_set_control_param_no_mutex(codec,
1547 CONTROL_PARAM_STREAM_ID, streamid);
1548 chipio_set_control_param_no_mutex(codec,
1549 CONTROL_PARAM_STREAM_CONTROL, enable);
1550 }
1551
1552
1553 /*
1554 * Set sampling rate of the connection point. NO MUTEX.
1555 */
chipio_set_conn_rate_no_mutex(struct hda_codec * codec,int connid,enum ca0132_sample_rate rate)1556 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1557 int connid, enum ca0132_sample_rate rate)
1558 {
1559 chipio_set_control_param_no_mutex(codec,
1560 CONTROL_PARAM_CONN_POINT_ID, connid);
1561 chipio_set_control_param_no_mutex(codec,
1562 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1563 }
1564
1565 /*
1566 * Set sampling rate of the connection point.
1567 */
chipio_set_conn_rate(struct hda_codec * codec,int connid,enum ca0132_sample_rate rate)1568 static void chipio_set_conn_rate(struct hda_codec *codec,
1569 int connid, enum ca0132_sample_rate rate)
1570 {
1571 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1572 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1573 rate);
1574 }
1575
1576 /*
1577 * Writes to the 8051's internal address space directly instead of indirectly,
1578 * giving access to the special function registers located at addresses
1579 * 0x80-0xFF.
1580 */
chipio_8051_write_direct(struct hda_codec * codec,unsigned int addr,unsigned int data)1581 static void chipio_8051_write_direct(struct hda_codec *codec,
1582 unsigned int addr, unsigned int data)
1583 {
1584 unsigned int verb;
1585
1586 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1587 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1588 }
1589
1590 /*
1591 * Enable clocks.
1592 */
chipio_enable_clocks(struct hda_codec * codec)1593 static void chipio_enable_clocks(struct hda_codec *codec)
1594 {
1595 struct ca0132_spec *spec = codec->spec;
1596
1597 mutex_lock(&spec->chipio_mutex);
1598 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1599 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1600 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1601 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1602 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1603 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1604 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1605 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1606 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1607 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1608 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1609 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1610 mutex_unlock(&spec->chipio_mutex);
1611 }
1612
1613 /*
1614 * CA0132 DSP IO stuffs
1615 */
dspio_send(struct hda_codec * codec,unsigned int reg,unsigned int data)1616 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1617 unsigned int data)
1618 {
1619 int res;
1620 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1621
1622 /* send bits of data specified by reg to dsp */
1623 do {
1624 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1625 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1626 return res;
1627 msleep(20);
1628 } while (time_before(jiffies, timeout));
1629
1630 return -EIO;
1631 }
1632
1633 /*
1634 * Wait for DSP to be ready for commands
1635 */
dspio_write_wait(struct hda_codec * codec)1636 static void dspio_write_wait(struct hda_codec *codec)
1637 {
1638 int status;
1639 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1640
1641 do {
1642 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1643 VENDOR_DSPIO_STATUS, 0);
1644 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1645 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1646 break;
1647 msleep(1);
1648 } while (time_before(jiffies, timeout));
1649 }
1650
1651 /*
1652 * Write SCP data to DSP
1653 */
dspio_write(struct hda_codec * codec,unsigned int scp_data)1654 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1655 {
1656 struct ca0132_spec *spec = codec->spec;
1657 int status;
1658
1659 dspio_write_wait(codec);
1660
1661 mutex_lock(&spec->chipio_mutex);
1662 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1663 scp_data & 0xffff);
1664 if (status < 0)
1665 goto error;
1666
1667 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1668 scp_data >> 16);
1669 if (status < 0)
1670 goto error;
1671
1672 /* OK, now check if the write itself has executed*/
1673 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1674 VENDOR_DSPIO_STATUS, 0);
1675 error:
1676 mutex_unlock(&spec->chipio_mutex);
1677
1678 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1679 -EIO : 0;
1680 }
1681
1682 /*
1683 * Write multiple SCP data to DSP
1684 */
dspio_write_multiple(struct hda_codec * codec,unsigned int * buffer,unsigned int size)1685 static int dspio_write_multiple(struct hda_codec *codec,
1686 unsigned int *buffer, unsigned int size)
1687 {
1688 int status = 0;
1689 unsigned int count;
1690
1691 if (buffer == NULL)
1692 return -EINVAL;
1693
1694 count = 0;
1695 while (count < size) {
1696 status = dspio_write(codec, *buffer++);
1697 if (status != 0)
1698 break;
1699 count++;
1700 }
1701
1702 return status;
1703 }
1704
dspio_read(struct hda_codec * codec,unsigned int * data)1705 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1706 {
1707 int status;
1708
1709 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1710 if (status == -EIO)
1711 return status;
1712
1713 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1714 if (status == -EIO ||
1715 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1716 return -EIO;
1717
1718 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1719 VENDOR_DSPIO_SCP_READ_DATA, 0);
1720
1721 return 0;
1722 }
1723
dspio_read_multiple(struct hda_codec * codec,unsigned int * buffer,unsigned int * buf_size,unsigned int size_count)1724 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1725 unsigned int *buf_size, unsigned int size_count)
1726 {
1727 int status = 0;
1728 unsigned int size = *buf_size;
1729 unsigned int count;
1730 unsigned int skip_count;
1731 unsigned int dummy;
1732
1733 if (buffer == NULL)
1734 return -1;
1735
1736 count = 0;
1737 while (count < size && count < size_count) {
1738 status = dspio_read(codec, buffer++);
1739 if (status != 0)
1740 break;
1741 count++;
1742 }
1743
1744 skip_count = count;
1745 if (status == 0) {
1746 while (skip_count < size) {
1747 status = dspio_read(codec, &dummy);
1748 if (status != 0)
1749 break;
1750 skip_count++;
1751 }
1752 }
1753 *buf_size = count;
1754
1755 return status;
1756 }
1757
1758 /*
1759 * Construct the SCP header using corresponding fields
1760 */
1761 static inline unsigned int
make_scp_header(unsigned int target_id,unsigned int source_id,unsigned int get_flag,unsigned int req,unsigned int device_flag,unsigned int resp_flag,unsigned int error_flag,unsigned int data_size)1762 make_scp_header(unsigned int target_id, unsigned int source_id,
1763 unsigned int get_flag, unsigned int req,
1764 unsigned int device_flag, unsigned int resp_flag,
1765 unsigned int error_flag, unsigned int data_size)
1766 {
1767 unsigned int header = 0;
1768
1769 header = (data_size & 0x1f) << 27;
1770 header |= (error_flag & 0x01) << 26;
1771 header |= (resp_flag & 0x01) << 25;
1772 header |= (device_flag & 0x01) << 24;
1773 header |= (req & 0x7f) << 17;
1774 header |= (get_flag & 0x01) << 16;
1775 header |= (source_id & 0xff) << 8;
1776 header |= target_id & 0xff;
1777
1778 return header;
1779 }
1780
1781 /*
1782 * Extract corresponding fields from SCP header
1783 */
1784 static inline void
extract_scp_header(unsigned int header,unsigned int * target_id,unsigned int * source_id,unsigned int * get_flag,unsigned int * req,unsigned int * device_flag,unsigned int * resp_flag,unsigned int * error_flag,unsigned int * data_size)1785 extract_scp_header(unsigned int header,
1786 unsigned int *target_id, unsigned int *source_id,
1787 unsigned int *get_flag, unsigned int *req,
1788 unsigned int *device_flag, unsigned int *resp_flag,
1789 unsigned int *error_flag, unsigned int *data_size)
1790 {
1791 if (data_size)
1792 *data_size = (header >> 27) & 0x1f;
1793 if (error_flag)
1794 *error_flag = (header >> 26) & 0x01;
1795 if (resp_flag)
1796 *resp_flag = (header >> 25) & 0x01;
1797 if (device_flag)
1798 *device_flag = (header >> 24) & 0x01;
1799 if (req)
1800 *req = (header >> 17) & 0x7f;
1801 if (get_flag)
1802 *get_flag = (header >> 16) & 0x01;
1803 if (source_id)
1804 *source_id = (header >> 8) & 0xff;
1805 if (target_id)
1806 *target_id = header & 0xff;
1807 }
1808
1809 #define SCP_MAX_DATA_WORDS (16)
1810
1811 /* Structure to contain any SCP message */
1812 struct scp_msg {
1813 unsigned int hdr;
1814 unsigned int data[SCP_MAX_DATA_WORDS];
1815 };
1816
dspio_clear_response_queue(struct hda_codec * codec)1817 static void dspio_clear_response_queue(struct hda_codec *codec)
1818 {
1819 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1820 unsigned int dummy = 0;
1821 int status;
1822
1823 /* clear all from the response queue */
1824 do {
1825 status = dspio_read(codec, &dummy);
1826 } while (status == 0 && time_before(jiffies, timeout));
1827 }
1828
dspio_get_response_data(struct hda_codec * codec)1829 static int dspio_get_response_data(struct hda_codec *codec)
1830 {
1831 struct ca0132_spec *spec = codec->spec;
1832 unsigned int data = 0;
1833 unsigned int count;
1834
1835 if (dspio_read(codec, &data) < 0)
1836 return -EIO;
1837
1838 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1839 spec->scp_resp_header = data;
1840 spec->scp_resp_count = data >> 27;
1841 count = spec->wait_num_data;
1842 dspio_read_multiple(codec, spec->scp_resp_data,
1843 &spec->scp_resp_count, count);
1844 return 0;
1845 }
1846
1847 return -EIO;
1848 }
1849
1850 /*
1851 * Send SCP message to DSP
1852 */
dspio_send_scp_message(struct hda_codec * codec,unsigned char * send_buf,unsigned int send_buf_size,unsigned char * return_buf,unsigned int return_buf_size,unsigned int * bytes_returned)1853 static int dspio_send_scp_message(struct hda_codec *codec,
1854 unsigned char *send_buf,
1855 unsigned int send_buf_size,
1856 unsigned char *return_buf,
1857 unsigned int return_buf_size,
1858 unsigned int *bytes_returned)
1859 {
1860 struct ca0132_spec *spec = codec->spec;
1861 int status = -1;
1862 unsigned int scp_send_size = 0;
1863 unsigned int total_size;
1864 bool waiting_for_resp = false;
1865 unsigned int header;
1866 struct scp_msg *ret_msg;
1867 unsigned int resp_src_id, resp_target_id;
1868 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1869
1870 if (bytes_returned)
1871 *bytes_returned = 0;
1872
1873 /* get scp header from buffer */
1874 header = *((unsigned int *)send_buf);
1875 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1876 &device_flag, NULL, NULL, &data_size);
1877 scp_send_size = data_size + 1;
1878 total_size = (scp_send_size * 4);
1879
1880 if (send_buf_size < total_size)
1881 return -EINVAL;
1882
1883 if (get_flag || device_flag) {
1884 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1885 return -EINVAL;
1886
1887 spec->wait_scp_header = *((unsigned int *)send_buf);
1888
1889 /* swap source id with target id */
1890 resp_target_id = src_id;
1891 resp_src_id = target_id;
1892 spec->wait_scp_header &= 0xffff0000;
1893 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1894 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1895 spec->wait_scp = 1;
1896 waiting_for_resp = true;
1897 }
1898
1899 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1900 scp_send_size);
1901 if (status < 0) {
1902 spec->wait_scp = 0;
1903 return status;
1904 }
1905
1906 if (waiting_for_resp) {
1907 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1908 memset(return_buf, 0, return_buf_size);
1909 do {
1910 msleep(20);
1911 } while (spec->wait_scp && time_before(jiffies, timeout));
1912 waiting_for_resp = false;
1913 if (!spec->wait_scp) {
1914 ret_msg = (struct scp_msg *)return_buf;
1915 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1916 memcpy(&ret_msg->data, spec->scp_resp_data,
1917 spec->wait_num_data);
1918 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1919 status = 0;
1920 } else {
1921 status = -EIO;
1922 }
1923 spec->wait_scp = 0;
1924 }
1925
1926 return status;
1927 }
1928
1929 /**
1930 * Prepare and send the SCP message to DSP
1931 * @codec: the HDA codec
1932 * @mod_id: ID of the DSP module to send the command
1933 * @req: ID of request to send to the DSP module
1934 * @dir: SET or GET
1935 * @data: pointer to the data to send with the request, request specific
1936 * @len: length of the data, in bytes
1937 * @reply: point to the buffer to hold data returned for a reply
1938 * @reply_len: length of the reply buffer returned from GET
1939 *
1940 * Returns zero or a negative error code.
1941 */
dspio_scp(struct hda_codec * codec,int mod_id,int src_id,int req,int dir,const void * data,unsigned int len,void * reply,unsigned int * reply_len)1942 static int dspio_scp(struct hda_codec *codec,
1943 int mod_id, int src_id, int req, int dir, const void *data,
1944 unsigned int len, void *reply, unsigned int *reply_len)
1945 {
1946 int status = 0;
1947 struct scp_msg scp_send, scp_reply;
1948 unsigned int ret_bytes, send_size, ret_size;
1949 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1950 unsigned int reply_data_size;
1951
1952 memset(&scp_send, 0, sizeof(scp_send));
1953 memset(&scp_reply, 0, sizeof(scp_reply));
1954
1955 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1956 return -EINVAL;
1957
1958 if (dir == SCP_GET && reply == NULL) {
1959 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1960 return -EINVAL;
1961 }
1962
1963 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1964 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1965 return -EINVAL;
1966 }
1967
1968 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
1969 0, 0, 0, len/sizeof(unsigned int));
1970 if (data != NULL && len > 0) {
1971 len = min((unsigned int)(sizeof(scp_send.data)), len);
1972 memcpy(scp_send.data, data, len);
1973 }
1974
1975 ret_bytes = 0;
1976 send_size = sizeof(unsigned int) + len;
1977 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1978 send_size, (unsigned char *)&scp_reply,
1979 sizeof(scp_reply), &ret_bytes);
1980
1981 if (status < 0) {
1982 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1983 return status;
1984 }
1985
1986 /* extract send and reply headers members */
1987 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1988 NULL, NULL, NULL, NULL, NULL);
1989 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1990 &reply_resp_flag, &reply_error_flag,
1991 &reply_data_size);
1992
1993 if (!send_get_flag)
1994 return 0;
1995
1996 if (reply_resp_flag && !reply_error_flag) {
1997 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1998 / sizeof(unsigned int);
1999
2000 if (*reply_len < ret_size*sizeof(unsigned int)) {
2001 codec_dbg(codec, "reply too long for buf\n");
2002 return -EINVAL;
2003 } else if (ret_size != reply_data_size) {
2004 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2005 return -EINVAL;
2006 } else if (!reply) {
2007 codec_dbg(codec, "NULL reply\n");
2008 return -EINVAL;
2009 } else {
2010 *reply_len = ret_size*sizeof(unsigned int);
2011 memcpy(reply, scp_reply.data, *reply_len);
2012 }
2013 } else {
2014 codec_dbg(codec, "reply ill-formed or errflag set\n");
2015 return -EIO;
2016 }
2017
2018 return status;
2019 }
2020
2021 /*
2022 * Set DSP parameters
2023 */
dspio_set_param(struct hda_codec * codec,int mod_id,int src_id,int req,const void * data,unsigned int len)2024 static int dspio_set_param(struct hda_codec *codec, int mod_id,
2025 int src_id, int req, const void *data, unsigned int len)
2026 {
2027 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2028 NULL);
2029 }
2030
dspio_set_uint_param(struct hda_codec * codec,int mod_id,int req,const unsigned int data)2031 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2032 int req, const unsigned int data)
2033 {
2034 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2035 sizeof(unsigned int));
2036 }
2037
dspio_set_uint_param_no_source(struct hda_codec * codec,int mod_id,int req,const unsigned int data)2038 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
2039 int req, const unsigned int data)
2040 {
2041 return dspio_set_param(codec, mod_id, 0x00, req, &data,
2042 sizeof(unsigned int));
2043 }
2044
2045 /*
2046 * Allocate a DSP DMA channel via an SCP message
2047 */
dspio_alloc_dma_chan(struct hda_codec * codec,unsigned int * dma_chan)2048 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2049 {
2050 int status = 0;
2051 unsigned int size = sizeof(*dma_chan);
2052
2053 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
2054 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2055 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2056 dma_chan, &size);
2057
2058 if (status < 0) {
2059 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2060 return status;
2061 }
2062
2063 if ((*dma_chan + 1) == 0) {
2064 codec_dbg(codec, "no free dma channels to allocate\n");
2065 return -EBUSY;
2066 }
2067
2068 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2069 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
2070
2071 return status;
2072 }
2073
2074 /*
2075 * Free a DSP DMA via an SCP message
2076 */
dspio_free_dma_chan(struct hda_codec * codec,unsigned int dma_chan)2077 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2078 {
2079 int status = 0;
2080 unsigned int dummy = 0;
2081
2082 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2083 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2084
2085 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2086 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2087 sizeof(dma_chan), NULL, &dummy);
2088
2089 if (status < 0) {
2090 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2091 return status;
2092 }
2093
2094 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
2095
2096 return status;
2097 }
2098
2099 /*
2100 * (Re)start the DSP
2101 */
dsp_set_run_state(struct hda_codec * codec)2102 static int dsp_set_run_state(struct hda_codec *codec)
2103 {
2104 unsigned int dbg_ctrl_reg;
2105 unsigned int halt_state;
2106 int err;
2107
2108 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2109 if (err < 0)
2110 return err;
2111
2112 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2113 DSP_DBGCNTL_STATE_LOBIT;
2114
2115 if (halt_state != 0) {
2116 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2117 DSP_DBGCNTL_SS_MASK);
2118 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2119 dbg_ctrl_reg);
2120 if (err < 0)
2121 return err;
2122
2123 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2124 DSP_DBGCNTL_EXEC_MASK;
2125 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2126 dbg_ctrl_reg);
2127 if (err < 0)
2128 return err;
2129 }
2130
2131 return 0;
2132 }
2133
2134 /*
2135 * Reset the DSP
2136 */
dsp_reset(struct hda_codec * codec)2137 static int dsp_reset(struct hda_codec *codec)
2138 {
2139 unsigned int res;
2140 int retry = 20;
2141
2142 codec_dbg(codec, "dsp_reset\n");
2143 do {
2144 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2145 retry--;
2146 } while (res == -EIO && retry);
2147
2148 if (!retry) {
2149 codec_dbg(codec, "dsp_reset timeout\n");
2150 return -EIO;
2151 }
2152
2153 return 0;
2154 }
2155
2156 /*
2157 * Convert chip address to DSP address
2158 */
dsp_chip_to_dsp_addx(unsigned int chip_addx,bool * code,bool * yram)2159 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2160 bool *code, bool *yram)
2161 {
2162 *code = *yram = false;
2163
2164 if (UC_RANGE(chip_addx, 1)) {
2165 *code = true;
2166 return UC_OFF(chip_addx);
2167 } else if (X_RANGE_ALL(chip_addx, 1)) {
2168 return X_OFF(chip_addx);
2169 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2170 *yram = true;
2171 return Y_OFF(chip_addx);
2172 }
2173
2174 return INVALID_CHIP_ADDRESS;
2175 }
2176
2177 /*
2178 * Check if the DSP DMA is active
2179 */
dsp_is_dma_active(struct hda_codec * codec,unsigned int dma_chan)2180 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2181 {
2182 unsigned int dma_chnlstart_reg;
2183
2184 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2185
2186 return ((dma_chnlstart_reg & (1 <<
2187 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2188 }
2189
dsp_dma_setup_common(struct hda_codec * codec,unsigned int chip_addx,unsigned int dma_chan,unsigned int port_map_mask,bool ovly)2190 static int dsp_dma_setup_common(struct hda_codec *codec,
2191 unsigned int chip_addx,
2192 unsigned int dma_chan,
2193 unsigned int port_map_mask,
2194 bool ovly)
2195 {
2196 int status = 0;
2197 unsigned int chnl_prop;
2198 unsigned int dsp_addx;
2199 unsigned int active;
2200 bool code, yram;
2201
2202 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2203
2204 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2205 codec_dbg(codec, "dma chan num invalid\n");
2206 return -EINVAL;
2207 }
2208
2209 if (dsp_is_dma_active(codec, dma_chan)) {
2210 codec_dbg(codec, "dma already active\n");
2211 return -EBUSY;
2212 }
2213
2214 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2215
2216 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2217 codec_dbg(codec, "invalid chip addr\n");
2218 return -ENXIO;
2219 }
2220
2221 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2222 active = 0;
2223
2224 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
2225
2226 if (ovly) {
2227 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2228 &chnl_prop);
2229
2230 if (status < 0) {
2231 codec_dbg(codec, "read CHNLPROP Reg fail\n");
2232 return status;
2233 }
2234 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2235 }
2236
2237 if (!code)
2238 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2239 else
2240 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2241
2242 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2243
2244 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2245 if (status < 0) {
2246 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2247 return status;
2248 }
2249 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
2250
2251 if (ovly) {
2252 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2253 &active);
2254
2255 if (status < 0) {
2256 codec_dbg(codec, "read ACTIVE Reg fail\n");
2257 return status;
2258 }
2259 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2260 }
2261
2262 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2263 DSPDMAC_ACTIVE_AAR_MASK;
2264
2265 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2266 if (status < 0) {
2267 codec_dbg(codec, "write ACTIVE Reg fail\n");
2268 return status;
2269 }
2270
2271 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
2272
2273 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2274 port_map_mask);
2275 if (status < 0) {
2276 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2277 return status;
2278 }
2279 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
2280
2281 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2282 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2283 if (status < 0) {
2284 codec_dbg(codec, "write IRQCNT Reg fail\n");
2285 return status;
2286 }
2287 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
2288
2289 codec_dbg(codec,
2290 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2291 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2292 chip_addx, dsp_addx, dma_chan,
2293 port_map_mask, chnl_prop, active);
2294
2295 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2296
2297 return 0;
2298 }
2299
2300 /*
2301 * Setup the DSP DMA per-transfer-specific registers
2302 */
dsp_dma_setup(struct hda_codec * codec,unsigned int chip_addx,unsigned int count,unsigned int dma_chan)2303 static int dsp_dma_setup(struct hda_codec *codec,
2304 unsigned int chip_addx,
2305 unsigned int count,
2306 unsigned int dma_chan)
2307 {
2308 int status = 0;
2309 bool code, yram;
2310 unsigned int dsp_addx;
2311 unsigned int addr_field;
2312 unsigned int incr_field;
2313 unsigned int base_cnt;
2314 unsigned int cur_cnt;
2315 unsigned int dma_cfg = 0;
2316 unsigned int adr_ofs = 0;
2317 unsigned int xfr_cnt = 0;
2318 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2319 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2320
2321 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2322
2323 if (count > max_dma_count) {
2324 codec_dbg(codec, "count too big\n");
2325 return -EINVAL;
2326 }
2327
2328 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2329 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2330 codec_dbg(codec, "invalid chip addr\n");
2331 return -ENXIO;
2332 }
2333
2334 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
2335
2336 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2337 incr_field = 0;
2338
2339 if (!code) {
2340 addr_field <<= 1;
2341 if (yram)
2342 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2343
2344 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2345 }
2346
2347 dma_cfg = addr_field + incr_field;
2348 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2349 dma_cfg);
2350 if (status < 0) {
2351 codec_dbg(codec, "write DMACFG Reg fail\n");
2352 return status;
2353 }
2354 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
2355
2356 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2357 (code ? 0 : 1));
2358
2359 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2360 adr_ofs);
2361 if (status < 0) {
2362 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2363 return status;
2364 }
2365 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
2366
2367 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2368
2369 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2370
2371 xfr_cnt = base_cnt | cur_cnt;
2372
2373 status = chipio_write(codec,
2374 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2375 if (status < 0) {
2376 codec_dbg(codec, "write XFRCNT Reg fail\n");
2377 return status;
2378 }
2379 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
2380
2381 codec_dbg(codec,
2382 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2383 "ADROFS=0x%x, XFRCNT=0x%x\n",
2384 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2385
2386 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2387
2388 return 0;
2389 }
2390
2391 /*
2392 * Start the DSP DMA
2393 */
dsp_dma_start(struct hda_codec * codec,unsigned int dma_chan,bool ovly)2394 static int dsp_dma_start(struct hda_codec *codec,
2395 unsigned int dma_chan, bool ovly)
2396 {
2397 unsigned int reg = 0;
2398 int status = 0;
2399
2400 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2401
2402 if (ovly) {
2403 status = chipio_read(codec,
2404 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
2405
2406 if (status < 0) {
2407 codec_dbg(codec, "read CHNLSTART reg fail\n");
2408 return status;
2409 }
2410 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
2411
2412 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2413 DSPDMAC_CHNLSTART_DIS_MASK);
2414 }
2415
2416 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2417 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2418 if (status < 0) {
2419 codec_dbg(codec, "write CHNLSTART reg fail\n");
2420 return status;
2421 }
2422 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2423
2424 return status;
2425 }
2426
2427 /*
2428 * Stop the DSP DMA
2429 */
dsp_dma_stop(struct hda_codec * codec,unsigned int dma_chan,bool ovly)2430 static int dsp_dma_stop(struct hda_codec *codec,
2431 unsigned int dma_chan, bool ovly)
2432 {
2433 unsigned int reg = 0;
2434 int status = 0;
2435
2436 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2437
2438 if (ovly) {
2439 status = chipio_read(codec,
2440 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
2441
2442 if (status < 0) {
2443 codec_dbg(codec, "read CHNLSTART reg fail\n");
2444 return status;
2445 }
2446 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
2447 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2448 DSPDMAC_CHNLSTART_DIS_MASK);
2449 }
2450
2451 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2452 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2453 if (status < 0) {
2454 codec_dbg(codec, "write CHNLSTART reg fail\n");
2455 return status;
2456 }
2457 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2458
2459 return status;
2460 }
2461
2462 /**
2463 * Allocate router ports
2464 *
2465 * @codec: the HDA codec
2466 * @num_chans: number of channels in the stream
2467 * @ports_per_channel: number of ports per channel
2468 * @start_device: start device
2469 * @port_map: pointer to the port list to hold the allocated ports
2470 *
2471 * Returns zero or a negative error code.
2472 */
dsp_allocate_router_ports(struct hda_codec * codec,unsigned int num_chans,unsigned int ports_per_channel,unsigned int start_device,unsigned int * port_map)2473 static int dsp_allocate_router_ports(struct hda_codec *codec,
2474 unsigned int num_chans,
2475 unsigned int ports_per_channel,
2476 unsigned int start_device,
2477 unsigned int *port_map)
2478 {
2479 int status = 0;
2480 int res;
2481 u8 val;
2482
2483 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2484 if (status < 0)
2485 return status;
2486
2487 val = start_device << 6;
2488 val |= (ports_per_channel - 1) << 4;
2489 val |= num_chans - 1;
2490
2491 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2492 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2493 val);
2494
2495 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2496 VENDOR_CHIPIO_PORT_ALLOC_SET,
2497 MEM_CONNID_DSP);
2498
2499 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2500 if (status < 0)
2501 return status;
2502
2503 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2504 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2505
2506 *port_map = res;
2507
2508 return (res < 0) ? res : 0;
2509 }
2510
2511 /*
2512 * Free router ports
2513 */
dsp_free_router_ports(struct hda_codec * codec)2514 static int dsp_free_router_ports(struct hda_codec *codec)
2515 {
2516 int status = 0;
2517
2518 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2519 if (status < 0)
2520 return status;
2521
2522 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2523 VENDOR_CHIPIO_PORT_FREE_SET,
2524 MEM_CONNID_DSP);
2525
2526 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2527
2528 return status;
2529 }
2530
2531 /*
2532 * Allocate DSP ports for the download stream
2533 */
dsp_allocate_ports(struct hda_codec * codec,unsigned int num_chans,unsigned int rate_multi,unsigned int * port_map)2534 static int dsp_allocate_ports(struct hda_codec *codec,
2535 unsigned int num_chans,
2536 unsigned int rate_multi, unsigned int *port_map)
2537 {
2538 int status;
2539
2540 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
2541
2542 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2543 codec_dbg(codec, "bad rate multiple\n");
2544 return -EINVAL;
2545 }
2546
2547 status = dsp_allocate_router_ports(codec, num_chans,
2548 rate_multi, 0, port_map);
2549
2550 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2551
2552 return status;
2553 }
2554
dsp_allocate_ports_format(struct hda_codec * codec,const unsigned short fmt,unsigned int * port_map)2555 static int dsp_allocate_ports_format(struct hda_codec *codec,
2556 const unsigned short fmt,
2557 unsigned int *port_map)
2558 {
2559 int status;
2560 unsigned int num_chans;
2561
2562 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2563 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2564 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2565
2566 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2567 codec_dbg(codec, "bad rate multiple\n");
2568 return -EINVAL;
2569 }
2570
2571 num_chans = get_hdafmt_chs(fmt) + 1;
2572
2573 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2574
2575 return status;
2576 }
2577
2578 /*
2579 * free DSP ports
2580 */
dsp_free_ports(struct hda_codec * codec)2581 static int dsp_free_ports(struct hda_codec *codec)
2582 {
2583 int status;
2584
2585 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2586
2587 status = dsp_free_router_ports(codec);
2588 if (status < 0) {
2589 codec_dbg(codec, "free router ports fail\n");
2590 return status;
2591 }
2592 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2593
2594 return status;
2595 }
2596
2597 /*
2598 * HDA DMA engine stuffs for DSP code download
2599 */
2600 struct dma_engine {
2601 struct hda_codec *codec;
2602 unsigned short m_converter_format;
2603 struct snd_dma_buffer *dmab;
2604 unsigned int buf_size;
2605 };
2606
2607
2608 enum dma_state {
2609 DMA_STATE_STOP = 0,
2610 DMA_STATE_RUN = 1
2611 };
2612
dma_convert_to_hda_format(struct hda_codec * codec,unsigned int sample_rate,unsigned short channels,unsigned short * hda_format)2613 static int dma_convert_to_hda_format(struct hda_codec *codec,
2614 unsigned int sample_rate,
2615 unsigned short channels,
2616 unsigned short *hda_format)
2617 {
2618 unsigned int format_val;
2619
2620 format_val = snd_hdac_calc_stream_format(sample_rate,
2621 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2622
2623 if (hda_format)
2624 *hda_format = (unsigned short)format_val;
2625
2626 return 0;
2627 }
2628
2629 /*
2630 * Reset DMA for DSP download
2631 */
dma_reset(struct dma_engine * dma)2632 static int dma_reset(struct dma_engine *dma)
2633 {
2634 struct hda_codec *codec = dma->codec;
2635 struct ca0132_spec *spec = codec->spec;
2636 int status;
2637
2638 if (dma->dmab->area)
2639 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2640
2641 status = snd_hda_codec_load_dsp_prepare(codec,
2642 dma->m_converter_format,
2643 dma->buf_size,
2644 dma->dmab);
2645 if (status < 0)
2646 return status;
2647 spec->dsp_stream_id = status;
2648 return 0;
2649 }
2650
dma_set_state(struct dma_engine * dma,enum dma_state state)2651 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2652 {
2653 bool cmd;
2654
2655 switch (state) {
2656 case DMA_STATE_STOP:
2657 cmd = false;
2658 break;
2659 case DMA_STATE_RUN:
2660 cmd = true;
2661 break;
2662 default:
2663 return 0;
2664 }
2665
2666 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2667 return 0;
2668 }
2669
dma_get_buffer_size(struct dma_engine * dma)2670 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2671 {
2672 return dma->dmab->bytes;
2673 }
2674
dma_get_buffer_addr(struct dma_engine * dma)2675 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2676 {
2677 return dma->dmab->area;
2678 }
2679
dma_xfer(struct dma_engine * dma,const unsigned int * data,unsigned int count)2680 static int dma_xfer(struct dma_engine *dma,
2681 const unsigned int *data,
2682 unsigned int count)
2683 {
2684 memcpy(dma->dmab->area, data, count);
2685 return 0;
2686 }
2687
dma_get_converter_format(struct dma_engine * dma,unsigned short * format)2688 static void dma_get_converter_format(
2689 struct dma_engine *dma,
2690 unsigned short *format)
2691 {
2692 if (format)
2693 *format = dma->m_converter_format;
2694 }
2695
dma_get_stream_id(struct dma_engine * dma)2696 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2697 {
2698 struct ca0132_spec *spec = dma->codec->spec;
2699
2700 return spec->dsp_stream_id;
2701 }
2702
2703 struct dsp_image_seg {
2704 u32 magic;
2705 u32 chip_addr;
2706 u32 count;
2707 u32 data[0];
2708 };
2709
2710 static const u32 g_magic_value = 0x4c46584d;
2711 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2712
is_valid(const struct dsp_image_seg * p)2713 static bool is_valid(const struct dsp_image_seg *p)
2714 {
2715 return p->magic == g_magic_value;
2716 }
2717
is_hci_prog_list_seg(const struct dsp_image_seg * p)2718 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2719 {
2720 return g_chip_addr_magic_value == p->chip_addr;
2721 }
2722
is_last(const struct dsp_image_seg * p)2723 static bool is_last(const struct dsp_image_seg *p)
2724 {
2725 return p->count == 0;
2726 }
2727
dsp_sizeof(const struct dsp_image_seg * p)2728 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2729 {
2730 return struct_size(p, data, p->count);
2731 }
2732
get_next_seg_ptr(const struct dsp_image_seg * p)2733 static const struct dsp_image_seg *get_next_seg_ptr(
2734 const struct dsp_image_seg *p)
2735 {
2736 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2737 }
2738
2739 /*
2740 * CA0132 chip DSP transfer stuffs. For DSP download.
2741 */
2742 #define INVALID_DMA_CHANNEL (~0U)
2743
2744 /*
2745 * Program a list of address/data pairs via the ChipIO widget.
2746 * The segment data is in the format of successive pairs of words.
2747 * These are repeated as indicated by the segment's count field.
2748 */
dspxfr_hci_write(struct hda_codec * codec,const struct dsp_image_seg * fls)2749 static int dspxfr_hci_write(struct hda_codec *codec,
2750 const struct dsp_image_seg *fls)
2751 {
2752 int status;
2753 const u32 *data;
2754 unsigned int count;
2755
2756 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2757 codec_dbg(codec, "hci_write invalid params\n");
2758 return -EINVAL;
2759 }
2760
2761 count = fls->count;
2762 data = (u32 *)(fls->data);
2763 while (count >= 2) {
2764 status = chipio_write(codec, data[0], data[1]);
2765 if (status < 0) {
2766 codec_dbg(codec, "hci_write chipio failed\n");
2767 return status;
2768 }
2769 count -= 2;
2770 data += 2;
2771 }
2772 return 0;
2773 }
2774
2775 /**
2776 * Write a block of data into DSP code or data RAM using pre-allocated
2777 * DMA engine.
2778 *
2779 * @codec: the HDA codec
2780 * @fls: pointer to a fast load image
2781 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2782 * no relocation
2783 * @dma_engine: pointer to DMA engine to be used for DSP download
2784 * @dma_chan: The number of DMA channels used for DSP download
2785 * @port_map_mask: port mapping
2786 * @ovly: TRUE if overlay format is required
2787 *
2788 * Returns zero or a negative error code.
2789 */
dspxfr_one_seg(struct hda_codec * codec,const struct dsp_image_seg * fls,unsigned int reloc,struct dma_engine * dma_engine,unsigned int dma_chan,unsigned int port_map_mask,bool ovly)2790 static int dspxfr_one_seg(struct hda_codec *codec,
2791 const struct dsp_image_seg *fls,
2792 unsigned int reloc,
2793 struct dma_engine *dma_engine,
2794 unsigned int dma_chan,
2795 unsigned int port_map_mask,
2796 bool ovly)
2797 {
2798 int status = 0;
2799 bool comm_dma_setup_done = false;
2800 const unsigned int *data;
2801 unsigned int chip_addx;
2802 unsigned int words_to_write;
2803 unsigned int buffer_size_words;
2804 unsigned char *buffer_addx;
2805 unsigned short hda_format;
2806 unsigned int sample_rate_div;
2807 unsigned int sample_rate_mul;
2808 unsigned int num_chans;
2809 unsigned int hda_frame_size_words;
2810 unsigned int remainder_words;
2811 const u32 *data_remainder;
2812 u32 chip_addx_remainder;
2813 unsigned int run_size_words;
2814 const struct dsp_image_seg *hci_write = NULL;
2815 unsigned long timeout;
2816 bool dma_active;
2817
2818 if (fls == NULL)
2819 return -EINVAL;
2820 if (is_hci_prog_list_seg(fls)) {
2821 hci_write = fls;
2822 fls = get_next_seg_ptr(fls);
2823 }
2824
2825 if (hci_write && (!fls || is_last(fls))) {
2826 codec_dbg(codec, "hci_write\n");
2827 return dspxfr_hci_write(codec, hci_write);
2828 }
2829
2830 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2831 codec_dbg(codec, "Invalid Params\n");
2832 return -EINVAL;
2833 }
2834
2835 data = fls->data;
2836 chip_addx = fls->chip_addr,
2837 words_to_write = fls->count;
2838
2839 if (!words_to_write)
2840 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2841 if (reloc)
2842 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2843
2844 if (!UC_RANGE(chip_addx, words_to_write) &&
2845 !X_RANGE_ALL(chip_addx, words_to_write) &&
2846 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2847 codec_dbg(codec, "Invalid chip_addx Params\n");
2848 return -EINVAL;
2849 }
2850
2851 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2852 sizeof(u32);
2853
2854 buffer_addx = dma_get_buffer_addr(dma_engine);
2855
2856 if (buffer_addx == NULL) {
2857 codec_dbg(codec, "dma_engine buffer NULL\n");
2858 return -EINVAL;
2859 }
2860
2861 dma_get_converter_format(dma_engine, &hda_format);
2862 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2863 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2864 num_chans = get_hdafmt_chs(hda_format) + 1;
2865
2866 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2867 (num_chans * sample_rate_mul / sample_rate_div));
2868
2869 if (hda_frame_size_words == 0) {
2870 codec_dbg(codec, "frmsz zero\n");
2871 return -EINVAL;
2872 }
2873
2874 buffer_size_words = min(buffer_size_words,
2875 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2876 65536 : 32768));
2877 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2878 codec_dbg(codec,
2879 "chpadr=0x%08x frmsz=%u nchan=%u "
2880 "rate_mul=%u div=%u bufsz=%u\n",
2881 chip_addx, hda_frame_size_words, num_chans,
2882 sample_rate_mul, sample_rate_div, buffer_size_words);
2883
2884 if (buffer_size_words < hda_frame_size_words) {
2885 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2886 return -EINVAL;
2887 }
2888
2889 remainder_words = words_to_write % hda_frame_size_words;
2890 data_remainder = data;
2891 chip_addx_remainder = chip_addx;
2892
2893 data += remainder_words;
2894 chip_addx += remainder_words*sizeof(u32);
2895 words_to_write -= remainder_words;
2896
2897 while (words_to_write != 0) {
2898 run_size_words = min(buffer_size_words, words_to_write);
2899 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2900 words_to_write, run_size_words, remainder_words);
2901 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2902 if (!comm_dma_setup_done) {
2903 status = dsp_dma_stop(codec, dma_chan, ovly);
2904 if (status < 0)
2905 return status;
2906 status = dsp_dma_setup_common(codec, chip_addx,
2907 dma_chan, port_map_mask, ovly);
2908 if (status < 0)
2909 return status;
2910 comm_dma_setup_done = true;
2911 }
2912
2913 status = dsp_dma_setup(codec, chip_addx,
2914 run_size_words, dma_chan);
2915 if (status < 0)
2916 return status;
2917 status = dsp_dma_start(codec, dma_chan, ovly);
2918 if (status < 0)
2919 return status;
2920 if (!dsp_is_dma_active(codec, dma_chan)) {
2921 codec_dbg(codec, "dspxfr:DMA did not start\n");
2922 return -EIO;
2923 }
2924 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2925 if (status < 0)
2926 return status;
2927 if (remainder_words != 0) {
2928 status = chipio_write_multiple(codec,
2929 chip_addx_remainder,
2930 data_remainder,
2931 remainder_words);
2932 if (status < 0)
2933 return status;
2934 remainder_words = 0;
2935 }
2936 if (hci_write) {
2937 status = dspxfr_hci_write(codec, hci_write);
2938 if (status < 0)
2939 return status;
2940 hci_write = NULL;
2941 }
2942
2943 timeout = jiffies + msecs_to_jiffies(2000);
2944 do {
2945 dma_active = dsp_is_dma_active(codec, dma_chan);
2946 if (!dma_active)
2947 break;
2948 msleep(20);
2949 } while (time_before(jiffies, timeout));
2950 if (dma_active)
2951 break;
2952
2953 codec_dbg(codec, "+++++ DMA complete\n");
2954 dma_set_state(dma_engine, DMA_STATE_STOP);
2955 status = dma_reset(dma_engine);
2956
2957 if (status < 0)
2958 return status;
2959
2960 data += run_size_words;
2961 chip_addx += run_size_words*sizeof(u32);
2962 words_to_write -= run_size_words;
2963 }
2964
2965 if (remainder_words != 0) {
2966 status = chipio_write_multiple(codec, chip_addx_remainder,
2967 data_remainder, remainder_words);
2968 }
2969
2970 return status;
2971 }
2972
2973 /**
2974 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2975 *
2976 * @codec: the HDA codec
2977 * @fls_data: pointer to a fast load image
2978 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2979 * no relocation
2980 * @sample_rate: sampling rate of the stream used for DSP download
2981 * @channels: channels of the stream used for DSP download
2982 * @ovly: TRUE if overlay format is required
2983 *
2984 * Returns zero or a negative error code.
2985 */
dspxfr_image(struct hda_codec * codec,const struct dsp_image_seg * fls_data,unsigned int reloc,unsigned int sample_rate,unsigned short channels,bool ovly)2986 static int dspxfr_image(struct hda_codec *codec,
2987 const struct dsp_image_seg *fls_data,
2988 unsigned int reloc,
2989 unsigned int sample_rate,
2990 unsigned short channels,
2991 bool ovly)
2992 {
2993 struct ca0132_spec *spec = codec->spec;
2994 int status;
2995 unsigned short hda_format = 0;
2996 unsigned int response;
2997 unsigned char stream_id = 0;
2998 struct dma_engine *dma_engine;
2999 unsigned int dma_chan;
3000 unsigned int port_map_mask;
3001
3002 if (fls_data == NULL)
3003 return -EINVAL;
3004
3005 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
3006 if (!dma_engine)
3007 return -ENOMEM;
3008
3009 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3010 if (!dma_engine->dmab) {
3011 kfree(dma_engine);
3012 return -ENOMEM;
3013 }
3014
3015 dma_engine->codec = codec;
3016 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3017 dma_engine->m_converter_format = hda_format;
3018 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3019 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3020
3021 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3022
3023 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3024 hda_format, &response);
3025
3026 if (status < 0) {
3027 codec_dbg(codec, "set converter format fail\n");
3028 goto exit;
3029 }
3030
3031 status = snd_hda_codec_load_dsp_prepare(codec,
3032 dma_engine->m_converter_format,
3033 dma_engine->buf_size,
3034 dma_engine->dmab);
3035 if (status < 0)
3036 goto exit;
3037 spec->dsp_stream_id = status;
3038
3039 if (ovly) {
3040 status = dspio_alloc_dma_chan(codec, &dma_chan);
3041 if (status < 0) {
3042 codec_dbg(codec, "alloc dmachan fail\n");
3043 dma_chan = INVALID_DMA_CHANNEL;
3044 goto exit;
3045 }
3046 }
3047
3048 port_map_mask = 0;
3049 status = dsp_allocate_ports_format(codec, hda_format,
3050 &port_map_mask);
3051 if (status < 0) {
3052 codec_dbg(codec, "alloc ports fail\n");
3053 goto exit;
3054 }
3055
3056 stream_id = dma_get_stream_id(dma_engine);
3057 status = codec_set_converter_stream_channel(codec,
3058 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3059 if (status < 0) {
3060 codec_dbg(codec, "set stream chan fail\n");
3061 goto exit;
3062 }
3063
3064 while ((fls_data != NULL) && !is_last(fls_data)) {
3065 if (!is_valid(fls_data)) {
3066 codec_dbg(codec, "FLS check fail\n");
3067 status = -EINVAL;
3068 goto exit;
3069 }
3070 status = dspxfr_one_seg(codec, fls_data, reloc,
3071 dma_engine, dma_chan,
3072 port_map_mask, ovly);
3073 if (status < 0)
3074 break;
3075
3076 if (is_hci_prog_list_seg(fls_data))
3077 fls_data = get_next_seg_ptr(fls_data);
3078
3079 if ((fls_data != NULL) && !is_last(fls_data))
3080 fls_data = get_next_seg_ptr(fls_data);
3081 }
3082
3083 if (port_map_mask != 0)
3084 status = dsp_free_ports(codec);
3085
3086 if (status < 0)
3087 goto exit;
3088
3089 status = codec_set_converter_stream_channel(codec,
3090 WIDGET_CHIP_CTRL, 0, 0, &response);
3091
3092 exit:
3093 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3094 dspio_free_dma_chan(codec, dma_chan);
3095
3096 if (dma_engine->dmab->area)
3097 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3098 kfree(dma_engine->dmab);
3099 kfree(dma_engine);
3100
3101 return status;
3102 }
3103
3104 /*
3105 * CA0132 DSP download stuffs.
3106 */
dspload_post_setup(struct hda_codec * codec)3107 static void dspload_post_setup(struct hda_codec *codec)
3108 {
3109 struct ca0132_spec *spec = codec->spec;
3110 codec_dbg(codec, "---- dspload_post_setup ------\n");
3111 if (!ca0132_use_alt_functions(spec)) {
3112 /*set DSP speaker to 2.0 configuration*/
3113 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3114 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3115
3116 /*update write pointer*/
3117 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3118 }
3119 }
3120
3121 /**
3122 * dspload_image - Download DSP from a DSP Image Fast Load structure.
3123 *
3124 * @codec: the HDA codec
3125 * @fls: pointer to a fast load image
3126 * @ovly: TRUE if overlay format is required
3127 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3128 * no relocation
3129 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3130 * @router_chans: number of audio router channels to be allocated (0 means use
3131 * internal defaults; max is 32)
3132 *
3133 * Download DSP from a DSP Image Fast Load structure. This structure is a
3134 * linear, non-constant sized element array of structures, each of which
3135 * contain the count of the data to be loaded, the data itself, and the
3136 * corresponding starting chip address of the starting data location.
3137 * Returns zero or a negative error code.
3138 */
dspload_image(struct hda_codec * codec,const struct dsp_image_seg * fls,bool ovly,unsigned int reloc,bool autostart,int router_chans)3139 static int dspload_image(struct hda_codec *codec,
3140 const struct dsp_image_seg *fls,
3141 bool ovly,
3142 unsigned int reloc,
3143 bool autostart,
3144 int router_chans)
3145 {
3146 int status = 0;
3147 unsigned int sample_rate;
3148 unsigned short channels;
3149
3150 codec_dbg(codec, "---- dspload_image begin ------\n");
3151 if (router_chans == 0) {
3152 if (!ovly)
3153 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3154 else
3155 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3156 }
3157
3158 sample_rate = 48000;
3159 channels = (unsigned short)router_chans;
3160
3161 while (channels > 16) {
3162 sample_rate *= 2;
3163 channels /= 2;
3164 }
3165
3166 do {
3167 codec_dbg(codec, "Ready to program DMA\n");
3168 if (!ovly)
3169 status = dsp_reset(codec);
3170
3171 if (status < 0)
3172 break;
3173
3174 codec_dbg(codec, "dsp_reset() complete\n");
3175 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3176 ovly);
3177
3178 if (status < 0)
3179 break;
3180
3181 codec_dbg(codec, "dspxfr_image() complete\n");
3182 if (autostart && !ovly) {
3183 dspload_post_setup(codec);
3184 status = dsp_set_run_state(codec);
3185 }
3186
3187 codec_dbg(codec, "LOAD FINISHED\n");
3188 } while (0);
3189
3190 return status;
3191 }
3192
3193 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
dspload_is_loaded(struct hda_codec * codec)3194 static bool dspload_is_loaded(struct hda_codec *codec)
3195 {
3196 unsigned int data = 0;
3197 int status = 0;
3198
3199 status = chipio_read(codec, 0x40004, &data);
3200 if ((status < 0) || (data != 1))
3201 return false;
3202
3203 return true;
3204 }
3205 #else
3206 #define dspload_is_loaded(codec) false
3207 #endif
3208
dspload_wait_loaded(struct hda_codec * codec)3209 static bool dspload_wait_loaded(struct hda_codec *codec)
3210 {
3211 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3212
3213 do {
3214 if (dspload_is_loaded(codec)) {
3215 codec_info(codec, "ca0132 DSP downloaded and running\n");
3216 return true;
3217 }
3218 msleep(20);
3219 } while (time_before(jiffies, timeout));
3220
3221 codec_err(codec, "ca0132 failed to download DSP\n");
3222 return false;
3223 }
3224
3225 /*
3226 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3227 * based cards, and has a second mmio region, region2, that's used for special
3228 * commands.
3229 */
3230
3231 /*
3232 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3233 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3234 * The first eight bits are just the number of the pin. So far, I've only seen
3235 * this number go to 7.
3236 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3237 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3238 * then off to send that bit.
3239 */
ca0113_mmio_gpio_set(struct hda_codec * codec,unsigned int gpio_pin,bool enable)3240 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3241 bool enable)
3242 {
3243 struct ca0132_spec *spec = codec->spec;
3244 unsigned short gpio_data;
3245
3246 gpio_data = gpio_pin & 0xF;
3247 gpio_data |= ((enable << 8) & 0x100);
3248
3249 writew(gpio_data, spec->mem_base + 0x320);
3250 }
3251
3252 /*
3253 * Special pci region2 commands that are only used by the AE-5. They follow
3254 * a set format, and require reads at certain points to seemingly 'clear'
3255 * the response data. My first tests didn't do these reads, and would cause
3256 * the card to get locked up until the memory was read. These commands
3257 * seem to work with three distinct values that I've taken to calling group,
3258 * target-id, and value.
3259 */
ca0113_mmio_command_set(struct hda_codec * codec,unsigned int group,unsigned int target,unsigned int value)3260 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3261 unsigned int target, unsigned int value)
3262 {
3263 struct ca0132_spec *spec = codec->spec;
3264 unsigned int write_val;
3265
3266 writel(0x0000007e, spec->mem_base + 0x210);
3267 readl(spec->mem_base + 0x210);
3268 writel(0x0000005a, spec->mem_base + 0x210);
3269 readl(spec->mem_base + 0x210);
3270 readl(spec->mem_base + 0x210);
3271
3272 writel(0x00800005, spec->mem_base + 0x20c);
3273 writel(group, spec->mem_base + 0x804);
3274
3275 writel(0x00800005, spec->mem_base + 0x20c);
3276 write_val = (target & 0xff);
3277 write_val |= (value << 8);
3278
3279
3280 writel(write_val, spec->mem_base + 0x204);
3281 /*
3282 * Need delay here or else it goes too fast and works inconsistently.
3283 */
3284 msleep(20);
3285
3286 readl(spec->mem_base + 0x860);
3287 readl(spec->mem_base + 0x854);
3288 readl(spec->mem_base + 0x840);
3289
3290 writel(0x00800004, spec->mem_base + 0x20c);
3291 writel(0x00000000, spec->mem_base + 0x210);
3292 readl(spec->mem_base + 0x210);
3293 readl(spec->mem_base + 0x210);
3294 }
3295
3296 /*
3297 * This second type of command is used for setting the sound filter type.
3298 */
ca0113_mmio_command_set_type2(struct hda_codec * codec,unsigned int group,unsigned int target,unsigned int value)3299 static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3300 unsigned int group, unsigned int target, unsigned int value)
3301 {
3302 struct ca0132_spec *spec = codec->spec;
3303 unsigned int write_val;
3304
3305 writel(0x0000007e, spec->mem_base + 0x210);
3306 readl(spec->mem_base + 0x210);
3307 writel(0x0000005a, spec->mem_base + 0x210);
3308 readl(spec->mem_base + 0x210);
3309 readl(spec->mem_base + 0x210);
3310
3311 writel(0x00800003, spec->mem_base + 0x20c);
3312 writel(group, spec->mem_base + 0x804);
3313
3314 writel(0x00800005, spec->mem_base + 0x20c);
3315 write_val = (target & 0xff);
3316 write_val |= (value << 8);
3317
3318
3319 writel(write_val, spec->mem_base + 0x204);
3320 msleep(20);
3321 readl(spec->mem_base + 0x860);
3322 readl(spec->mem_base + 0x854);
3323 readl(spec->mem_base + 0x840);
3324
3325 writel(0x00800004, spec->mem_base + 0x20c);
3326 writel(0x00000000, spec->mem_base + 0x210);
3327 readl(spec->mem_base + 0x210);
3328 readl(spec->mem_base + 0x210);
3329 }
3330
3331 /*
3332 * Setup GPIO for the other variants of Core3D.
3333 */
3334
3335 /*
3336 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3337 * the card shows as having no GPIO pins.
3338 */
ca0132_gpio_init(struct hda_codec * codec)3339 static void ca0132_gpio_init(struct hda_codec *codec)
3340 {
3341 struct ca0132_spec *spec = codec->spec;
3342
3343 switch (ca0132_quirk(spec)) {
3344 case QUIRK_SBZ:
3345 case QUIRK_AE5:
3346 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3347 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3348 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3349 break;
3350 case QUIRK_R3DI:
3351 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3352 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3353 break;
3354 default:
3355 break;
3356 }
3357
3358 }
3359
3360 /* Sets the GPIO for audio output. */
ca0132_gpio_setup(struct hda_codec * codec)3361 static void ca0132_gpio_setup(struct hda_codec *codec)
3362 {
3363 struct ca0132_spec *spec = codec->spec;
3364
3365 switch (ca0132_quirk(spec)) {
3366 case QUIRK_SBZ:
3367 snd_hda_codec_write(codec, 0x01, 0,
3368 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3369 snd_hda_codec_write(codec, 0x01, 0,
3370 AC_VERB_SET_GPIO_MASK, 0x07);
3371 snd_hda_codec_write(codec, 0x01, 0,
3372 AC_VERB_SET_GPIO_DATA, 0x04);
3373 snd_hda_codec_write(codec, 0x01, 0,
3374 AC_VERB_SET_GPIO_DATA, 0x06);
3375 break;
3376 case QUIRK_R3DI:
3377 snd_hda_codec_write(codec, 0x01, 0,
3378 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3379 snd_hda_codec_write(codec, 0x01, 0,
3380 AC_VERB_SET_GPIO_MASK, 0x1F);
3381 snd_hda_codec_write(codec, 0x01, 0,
3382 AC_VERB_SET_GPIO_DATA, 0x0C);
3383 break;
3384 default:
3385 break;
3386 }
3387 }
3388
3389 /*
3390 * GPIO control functions for the Recon3D integrated.
3391 */
3392
3393 enum r3di_gpio_bit {
3394 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3395 R3DI_MIC_SELECT_BIT = 1,
3396 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3397 R3DI_OUT_SELECT_BIT = 2,
3398 /*
3399 * I dunno what this actually does, but it stays on until the dsp
3400 * is downloaded.
3401 */
3402 R3DI_GPIO_DSP_DOWNLOADING = 3,
3403 /*
3404 * Same as above, no clue what it does, but it comes on after the dsp
3405 * is downloaded.
3406 */
3407 R3DI_GPIO_DSP_DOWNLOADED = 4
3408 };
3409
3410 enum r3di_mic_select {
3411 /* Set GPIO bit 1 to 0 for rear mic */
3412 R3DI_REAR_MIC = 0,
3413 /* Set GPIO bit 1 to 1 for front microphone*/
3414 R3DI_FRONT_MIC = 1
3415 };
3416
3417 enum r3di_out_select {
3418 /* Set GPIO bit 2 to 0 for headphone */
3419 R3DI_HEADPHONE_OUT = 0,
3420 /* Set GPIO bit 2 to 1 for speaker */
3421 R3DI_LINE_OUT = 1
3422 };
3423 enum r3di_dsp_status {
3424 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3425 R3DI_DSP_DOWNLOADING = 0,
3426 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3427 R3DI_DSP_DOWNLOADED = 1
3428 };
3429
3430
r3di_gpio_mic_set(struct hda_codec * codec,enum r3di_mic_select cur_mic)3431 static void r3di_gpio_mic_set(struct hda_codec *codec,
3432 enum r3di_mic_select cur_mic)
3433 {
3434 unsigned int cur_gpio;
3435
3436 /* Get the current GPIO Data setup */
3437 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3438
3439 switch (cur_mic) {
3440 case R3DI_REAR_MIC:
3441 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3442 break;
3443 case R3DI_FRONT_MIC:
3444 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3445 break;
3446 }
3447 snd_hda_codec_write(codec, codec->core.afg, 0,
3448 AC_VERB_SET_GPIO_DATA, cur_gpio);
3449 }
3450
r3di_gpio_out_set(struct hda_codec * codec,enum r3di_out_select cur_out)3451 static void r3di_gpio_out_set(struct hda_codec *codec,
3452 enum r3di_out_select cur_out)
3453 {
3454 unsigned int cur_gpio;
3455
3456 /* Get the current GPIO Data setup */
3457 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3458
3459 switch (cur_out) {
3460 case R3DI_HEADPHONE_OUT:
3461 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3462 break;
3463 case R3DI_LINE_OUT:
3464 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3465 break;
3466 }
3467 snd_hda_codec_write(codec, codec->core.afg, 0,
3468 AC_VERB_SET_GPIO_DATA, cur_gpio);
3469 }
3470
r3di_gpio_dsp_status_set(struct hda_codec * codec,enum r3di_dsp_status dsp_status)3471 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3472 enum r3di_dsp_status dsp_status)
3473 {
3474 unsigned int cur_gpio;
3475
3476 /* Get the current GPIO Data setup */
3477 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3478
3479 switch (dsp_status) {
3480 case R3DI_DSP_DOWNLOADING:
3481 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3482 snd_hda_codec_write(codec, codec->core.afg, 0,
3483 AC_VERB_SET_GPIO_DATA, cur_gpio);
3484 break;
3485 case R3DI_DSP_DOWNLOADED:
3486 /* Set DOWNLOADING bit to 0. */
3487 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3488
3489 snd_hda_codec_write(codec, codec->core.afg, 0,
3490 AC_VERB_SET_GPIO_DATA, cur_gpio);
3491
3492 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3493 break;
3494 }
3495
3496 snd_hda_codec_write(codec, codec->core.afg, 0,
3497 AC_VERB_SET_GPIO_DATA, cur_gpio);
3498 }
3499
3500 /*
3501 * PCM callbacks
3502 */
ca0132_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3503 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3504 struct hda_codec *codec,
3505 unsigned int stream_tag,
3506 unsigned int format,
3507 struct snd_pcm_substream *substream)
3508 {
3509 struct ca0132_spec *spec = codec->spec;
3510
3511 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3512
3513 return 0;
3514 }
3515
ca0132_playback_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3516 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3517 struct hda_codec *codec,
3518 struct snd_pcm_substream *substream)
3519 {
3520 struct ca0132_spec *spec = codec->spec;
3521
3522 if (spec->dsp_state == DSP_DOWNLOADING)
3523 return 0;
3524
3525 /*If Playback effects are on, allow stream some time to flush
3526 *effects tail*/
3527 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3528 msleep(50);
3529
3530 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3531
3532 return 0;
3533 }
3534
ca0132_playback_pcm_delay(struct hda_pcm_stream * info,struct hda_codec * codec,struct snd_pcm_substream * substream)3535 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3536 struct hda_codec *codec,
3537 struct snd_pcm_substream *substream)
3538 {
3539 struct ca0132_spec *spec = codec->spec;
3540 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3541 struct snd_pcm_runtime *runtime = substream->runtime;
3542
3543 if (spec->dsp_state != DSP_DOWNLOADED)
3544 return 0;
3545
3546 /* Add latency if playback enhancement and either effect is enabled. */
3547 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3548 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3549 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3550 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3551 }
3552
3553 /* Applying Speaker EQ adds latency as well. */
3554 if (spec->cur_out_type == SPEAKER_OUT)
3555 latency += DSP_SPEAKER_OUT_LATENCY;
3556
3557 return (latency * runtime->rate) / 1000;
3558 }
3559
3560 /*
3561 * Digital out
3562 */
ca0132_dig_playback_pcm_open(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3563 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3564 struct hda_codec *codec,
3565 struct snd_pcm_substream *substream)
3566 {
3567 struct ca0132_spec *spec = codec->spec;
3568 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3569 }
3570
ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3571 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3572 struct hda_codec *codec,
3573 unsigned int stream_tag,
3574 unsigned int format,
3575 struct snd_pcm_substream *substream)
3576 {
3577 struct ca0132_spec *spec = codec->spec;
3578 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3579 stream_tag, format, substream);
3580 }
3581
ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3582 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3583 struct hda_codec *codec,
3584 struct snd_pcm_substream *substream)
3585 {
3586 struct ca0132_spec *spec = codec->spec;
3587 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3588 }
3589
ca0132_dig_playback_pcm_close(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3590 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3591 struct hda_codec *codec,
3592 struct snd_pcm_substream *substream)
3593 {
3594 struct ca0132_spec *spec = codec->spec;
3595 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3596 }
3597
3598 /*
3599 * Analog capture
3600 */
ca0132_capture_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3601 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3602 struct hda_codec *codec,
3603 unsigned int stream_tag,
3604 unsigned int format,
3605 struct snd_pcm_substream *substream)
3606 {
3607 snd_hda_codec_setup_stream(codec, hinfo->nid,
3608 stream_tag, 0, format);
3609
3610 return 0;
3611 }
3612
ca0132_capture_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3613 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3614 struct hda_codec *codec,
3615 struct snd_pcm_substream *substream)
3616 {
3617 struct ca0132_spec *spec = codec->spec;
3618
3619 if (spec->dsp_state == DSP_DOWNLOADING)
3620 return 0;
3621
3622 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3623 return 0;
3624 }
3625
ca0132_capture_pcm_delay(struct hda_pcm_stream * info,struct hda_codec * codec,struct snd_pcm_substream * substream)3626 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3627 struct hda_codec *codec,
3628 struct snd_pcm_substream *substream)
3629 {
3630 struct ca0132_spec *spec = codec->spec;
3631 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3632 struct snd_pcm_runtime *runtime = substream->runtime;
3633
3634 if (spec->dsp_state != DSP_DOWNLOADED)
3635 return 0;
3636
3637 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3638 latency += DSP_CRYSTAL_VOICE_LATENCY;
3639
3640 return (latency * runtime->rate) / 1000;
3641 }
3642
3643 /*
3644 * Controls stuffs.
3645 */
3646
3647 /*
3648 * Mixer controls helpers.
3649 */
3650 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3651 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3652 .name = xname, \
3653 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3654 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3655 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3656 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3657 .info = ca0132_volume_info, \
3658 .get = ca0132_volume_get, \
3659 .put = ca0132_volume_put, \
3660 .tlv = { .c = ca0132_volume_tlv }, \
3661 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3662
3663 /*
3664 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3665 * volume put, which is used for setting the DSP volume. This was done because
3666 * the ca0132 functions were taking too much time and causing lag.
3667 */
3668 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3669 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3670 .name = xname, \
3671 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3672 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3673 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3674 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3675 .info = snd_hda_mixer_amp_volume_info, \
3676 .get = snd_hda_mixer_amp_volume_get, \
3677 .put = ca0132_alt_volume_put, \
3678 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3679 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3680
3681 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3682 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3683 .name = xname, \
3684 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3685 .info = snd_hda_mixer_amp_switch_info, \
3686 .get = ca0132_switch_get, \
3687 .put = ca0132_switch_put, \
3688 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3689
3690 /* stereo */
3691 #define CA0132_CODEC_VOL(xname, nid, dir) \
3692 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
3693 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3694 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
3695 #define CA0132_CODEC_MUTE(xname, nid, dir) \
3696 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3697
3698 /* lookup tables */
3699 /*
3700 * Lookup table with decibel values for the DSP. When volume is changed in
3701 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3702 * these values have decimal points, probably because the Windows driver
3703 * actually uses floating point. We can't here, so I made a lookup table of
3704 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3705 * DAC's, and 9 is the maximum.
3706 */
3707 static const unsigned int float_vol_db_lookup[] = {
3708 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
3709 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
3710 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
3711 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
3712 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
3713 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
3714 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
3715 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
3716 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
3717 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
3718 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
3719 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3720 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3721 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3722 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3723 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3724 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
3725 };
3726
3727 /*
3728 * This table counts from float 0 to 1 in increments of .01, which is
3729 * useful for a few different sliders.
3730 */
3731 static const unsigned int float_zero_to_one_lookup[] = {
3732 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3733 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3734 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3735 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3736 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3737 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3738 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3739 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3740 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3741 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3742 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3743 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3744 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3745 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3746 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3747 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3748 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3749 };
3750
3751 /*
3752 * This table counts from float 10 to 1000, which is the range of the x-bass
3753 * crossover slider in Windows.
3754 */
3755 static const unsigned int float_xbass_xover_lookup[] = {
3756 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
3757 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
3758 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
3759 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
3760 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
3761 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
3762 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
3763 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
3764 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
3765 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
3766 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
3767 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
3768 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
3769 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
3770 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
3771 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
3772 0x44728000, 0x44750000, 0x44778000, 0x447A0000
3773 };
3774
3775 /* The following are for tuning of products */
3776 #ifdef ENABLE_TUNING_CONTROLS
3777
3778 static unsigned int voice_focus_vals_lookup[] = {
3779 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
3780 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
3781 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
3782 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
3783 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
3784 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
3785 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
3786 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
3787 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
3788 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
3789 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
3790 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
3791 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
3792 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
3793 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
3794 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
3795 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
3796 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
3797 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
3798 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
3799 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
3800 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
3801 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
3802 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
3803 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
3804 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
3805 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3806 };
3807
3808 static unsigned int mic_svm_vals_lookup[] = {
3809 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3810 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3811 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3812 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3813 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3814 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3815 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3816 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3817 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3818 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3819 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3820 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3821 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3822 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3823 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3824 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3825 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3826 };
3827
3828 static unsigned int equalizer_vals_lookup[] = {
3829 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3830 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3831 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3832 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3833 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3834 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
3835 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
3836 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
3837 0x41C00000
3838 };
3839
tuning_ctl_set(struct hda_codec * codec,hda_nid_t nid,unsigned int * lookup,int idx)3840 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3841 unsigned int *lookup, int idx)
3842 {
3843 int i = 0;
3844
3845 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3846 if (nid == ca0132_tuning_ctls[i].nid)
3847 goto found;
3848
3849 return -EINVAL;
3850 found:
3851 snd_hda_power_up(codec);
3852 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
3853 ca0132_tuning_ctls[i].req,
3854 &(lookup[idx]), sizeof(unsigned int));
3855 snd_hda_power_down(codec);
3856
3857 return 1;
3858 }
3859
tuning_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3860 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3861 struct snd_ctl_elem_value *ucontrol)
3862 {
3863 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3864 struct ca0132_spec *spec = codec->spec;
3865 hda_nid_t nid = get_amp_nid(kcontrol);
3866 long *valp = ucontrol->value.integer.value;
3867 int idx = nid - TUNING_CTL_START_NID;
3868
3869 *valp = spec->cur_ctl_vals[idx];
3870 return 0;
3871 }
3872
voice_focus_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3873 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3874 struct snd_ctl_elem_info *uinfo)
3875 {
3876 int chs = get_amp_channels(kcontrol);
3877 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3878 uinfo->count = chs == 3 ? 2 : 1;
3879 uinfo->value.integer.min = 20;
3880 uinfo->value.integer.max = 180;
3881 uinfo->value.integer.step = 1;
3882
3883 return 0;
3884 }
3885
voice_focus_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3886 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3887 struct snd_ctl_elem_value *ucontrol)
3888 {
3889 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3890 struct ca0132_spec *spec = codec->spec;
3891 hda_nid_t nid = get_amp_nid(kcontrol);
3892 long *valp = ucontrol->value.integer.value;
3893 int idx;
3894
3895 idx = nid - TUNING_CTL_START_NID;
3896 /* any change? */
3897 if (spec->cur_ctl_vals[idx] == *valp)
3898 return 0;
3899
3900 spec->cur_ctl_vals[idx] = *valp;
3901
3902 idx = *valp - 20;
3903 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3904
3905 return 1;
3906 }
3907
mic_svm_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3908 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3909 struct snd_ctl_elem_info *uinfo)
3910 {
3911 int chs = get_amp_channels(kcontrol);
3912 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3913 uinfo->count = chs == 3 ? 2 : 1;
3914 uinfo->value.integer.min = 0;
3915 uinfo->value.integer.max = 100;
3916 uinfo->value.integer.step = 1;
3917
3918 return 0;
3919 }
3920
mic_svm_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3921 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3922 struct snd_ctl_elem_value *ucontrol)
3923 {
3924 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3925 struct ca0132_spec *spec = codec->spec;
3926 hda_nid_t nid = get_amp_nid(kcontrol);
3927 long *valp = ucontrol->value.integer.value;
3928 int idx;
3929
3930 idx = nid - TUNING_CTL_START_NID;
3931 /* any change? */
3932 if (spec->cur_ctl_vals[idx] == *valp)
3933 return 0;
3934
3935 spec->cur_ctl_vals[idx] = *valp;
3936
3937 idx = *valp;
3938 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3939
3940 return 0;
3941 }
3942
equalizer_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3943 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3944 struct snd_ctl_elem_info *uinfo)
3945 {
3946 int chs = get_amp_channels(kcontrol);
3947 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3948 uinfo->count = chs == 3 ? 2 : 1;
3949 uinfo->value.integer.min = 0;
3950 uinfo->value.integer.max = 48;
3951 uinfo->value.integer.step = 1;
3952
3953 return 0;
3954 }
3955
equalizer_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3956 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3957 struct snd_ctl_elem_value *ucontrol)
3958 {
3959 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3960 struct ca0132_spec *spec = codec->spec;
3961 hda_nid_t nid = get_amp_nid(kcontrol);
3962 long *valp = ucontrol->value.integer.value;
3963 int idx;
3964
3965 idx = nid - TUNING_CTL_START_NID;
3966 /* any change? */
3967 if (spec->cur_ctl_vals[idx] == *valp)
3968 return 0;
3969
3970 spec->cur_ctl_vals[idx] = *valp;
3971
3972 idx = *valp;
3973 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3974
3975 return 1;
3976 }
3977
3978 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3979 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
3980
add_tuning_control(struct hda_codec * codec,hda_nid_t pnid,hda_nid_t nid,const char * name,int dir)3981 static int add_tuning_control(struct hda_codec *codec,
3982 hda_nid_t pnid, hda_nid_t nid,
3983 const char *name, int dir)
3984 {
3985 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3986 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3987 struct snd_kcontrol_new knew =
3988 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3989
3990 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3991 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3992 knew.tlv.c = 0;
3993 knew.tlv.p = 0;
3994 switch (pnid) {
3995 case VOICE_FOCUS:
3996 knew.info = voice_focus_ctl_info;
3997 knew.get = tuning_ctl_get;
3998 knew.put = voice_focus_ctl_put;
3999 knew.tlv.p = voice_focus_db_scale;
4000 break;
4001 case MIC_SVM:
4002 knew.info = mic_svm_ctl_info;
4003 knew.get = tuning_ctl_get;
4004 knew.put = mic_svm_ctl_put;
4005 break;
4006 case EQUALIZER:
4007 knew.info = equalizer_ctl_info;
4008 knew.get = tuning_ctl_get;
4009 knew.put = equalizer_ctl_put;
4010 knew.tlv.p = eq_db_scale;
4011 break;
4012 default:
4013 return 0;
4014 }
4015 knew.private_value =
4016 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4017 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4018 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4019 }
4020
add_tuning_ctls(struct hda_codec * codec)4021 static int add_tuning_ctls(struct hda_codec *codec)
4022 {
4023 int i;
4024 int err;
4025
4026 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4027 err = add_tuning_control(codec,
4028 ca0132_tuning_ctls[i].parent_nid,
4029 ca0132_tuning_ctls[i].nid,
4030 ca0132_tuning_ctls[i].name,
4031 ca0132_tuning_ctls[i].direct);
4032 if (err < 0)
4033 return err;
4034 }
4035
4036 return 0;
4037 }
4038
ca0132_init_tuning_defaults(struct hda_codec * codec)4039 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4040 {
4041 struct ca0132_spec *spec = codec->spec;
4042 int i;
4043
4044 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4045 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4046 /* SVM level defaults to 0.74. */
4047 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4048
4049 /* EQ defaults to 0dB. */
4050 for (i = 2; i < TUNING_CTLS_COUNT; i++)
4051 spec->cur_ctl_vals[i] = 24;
4052 }
4053 #endif /*ENABLE_TUNING_CONTROLS*/
4054
4055 /*
4056 * Select the active output.
4057 * If autodetect is enabled, output will be selected based on jack detection.
4058 * If jack inserted, headphone will be selected, else built-in speakers
4059 * If autodetect is disabled, output will be selected based on selection.
4060 */
ca0132_select_out(struct hda_codec * codec)4061 static int ca0132_select_out(struct hda_codec *codec)
4062 {
4063 struct ca0132_spec *spec = codec->spec;
4064 unsigned int pin_ctl;
4065 int jack_present;
4066 int auto_jack;
4067 unsigned int tmp;
4068 int err;
4069
4070 codec_dbg(codec, "ca0132_select_out\n");
4071
4072 snd_hda_power_up_pm(codec);
4073
4074 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4075
4076 if (auto_jack)
4077 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4078 else
4079 jack_present =
4080 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4081
4082 if (jack_present)
4083 spec->cur_out_type = HEADPHONE_OUT;
4084 else
4085 spec->cur_out_type = SPEAKER_OUT;
4086
4087 if (spec->cur_out_type == SPEAKER_OUT) {
4088 codec_dbg(codec, "ca0132_select_out speaker\n");
4089 /*speaker out config*/
4090 tmp = FLOAT_ONE;
4091 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4092 if (err < 0)
4093 goto exit;
4094 /*enable speaker EQ*/
4095 tmp = FLOAT_ONE;
4096 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4097 if (err < 0)
4098 goto exit;
4099
4100 /* Setup EAPD */
4101 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4102 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4103 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4104 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4105 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4106 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4107 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4108 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4109
4110 /* disable headphone node */
4111 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4112 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4113 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4114 pin_ctl & ~PIN_HP);
4115 /* enable speaker node */
4116 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4117 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4118 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4119 pin_ctl | PIN_OUT);
4120 } else {
4121 codec_dbg(codec, "ca0132_select_out hp\n");
4122 /*headphone out config*/
4123 tmp = FLOAT_ZERO;
4124 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4125 if (err < 0)
4126 goto exit;
4127 /*disable speaker EQ*/
4128 tmp = FLOAT_ZERO;
4129 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4130 if (err < 0)
4131 goto exit;
4132
4133 /* Setup EAPD */
4134 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4135 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4136 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4137 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4138 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4139 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4140 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4141 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4142
4143 /* disable speaker*/
4144 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4145 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4146 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4147 pin_ctl & ~PIN_HP);
4148 /* enable headphone*/
4149 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4150 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4151 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4152 pin_ctl | PIN_HP);
4153 }
4154
4155 exit:
4156 snd_hda_power_down_pm(codec);
4157
4158 return err < 0 ? err : 0;
4159 }
4160
4161 static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4162 static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4163 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4164
ae5_mmio_select_out(struct hda_codec * codec)4165 static void ae5_mmio_select_out(struct hda_codec *codec)
4166 {
4167 struct ca0132_spec *spec = codec->spec;
4168 unsigned int i;
4169
4170 for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++)
4171 ca0113_mmio_command_set(codec,
4172 ae5_ca0113_output_presets[spec->cur_out_type].group[i],
4173 ae5_ca0113_output_presets[spec->cur_out_type].target[i],
4174 ae5_ca0113_output_presets[spec->cur_out_type].vals[i]);
4175 }
4176
4177 /*
4178 * These are the commands needed to setup output on each of the different card
4179 * types.
4180 */
ca0132_alt_select_out_quirk_handler(struct hda_codec * codec)4181 static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec)
4182 {
4183 struct ca0132_spec *spec = codec->spec;
4184 unsigned int tmp;
4185
4186 switch (spec->cur_out_type) {
4187 case SPEAKER_OUT:
4188 switch (ca0132_quirk(spec)) {
4189 case QUIRK_SBZ:
4190 ca0113_mmio_gpio_set(codec, 7, false);
4191 ca0113_mmio_gpio_set(codec, 4, true);
4192 ca0113_mmio_gpio_set(codec, 1, true);
4193 chipio_set_control_param(codec, 0x0d, 0x18);
4194 break;
4195 case QUIRK_ZXR:
4196 ca0113_mmio_gpio_set(codec, 2, true);
4197 ca0113_mmio_gpio_set(codec, 3, true);
4198 ca0113_mmio_gpio_set(codec, 5, false);
4199 zxr_headphone_gain_set(codec, 0);
4200 chipio_set_control_param(codec, 0x0d, 0x24);
4201 break;
4202 case QUIRK_R3DI:
4203 chipio_set_control_param(codec, 0x0d, 0x24);
4204 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4205 break;
4206 case QUIRK_R3D:
4207 chipio_set_control_param(codec, 0x0d, 0x24);
4208 ca0113_mmio_gpio_set(codec, 1, true);
4209 break;
4210 case QUIRK_AE5:
4211 ae5_mmio_select_out(codec);
4212 ae5_headphone_gain_set(codec, 2);
4213 tmp = FLOAT_ZERO;
4214 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4215 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4216 chipio_set_control_param(codec, 0x0d, 0xa4);
4217 chipio_write(codec, 0x18b03c, 0x00000012);
4218 break;
4219 default:
4220 break;
4221 }
4222 break;
4223 case HEADPHONE_OUT:
4224 switch (ca0132_quirk(spec)) {
4225 case QUIRK_SBZ:
4226 ca0113_mmio_gpio_set(codec, 7, true);
4227 ca0113_mmio_gpio_set(codec, 4, true);
4228 ca0113_mmio_gpio_set(codec, 1, false);
4229 chipio_set_control_param(codec, 0x0d, 0x12);
4230 break;
4231 case QUIRK_ZXR:
4232 ca0113_mmio_gpio_set(codec, 2, false);
4233 ca0113_mmio_gpio_set(codec, 3, false);
4234 ca0113_mmio_gpio_set(codec, 5, true);
4235 zxr_headphone_gain_set(codec, spec->zxr_gain_set);
4236 chipio_set_control_param(codec, 0x0d, 0x21);
4237 break;
4238 case QUIRK_R3DI:
4239 chipio_set_control_param(codec, 0x0d, 0x21);
4240 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4241 break;
4242 case QUIRK_R3D:
4243 chipio_set_control_param(codec, 0x0d, 0x21);
4244 ca0113_mmio_gpio_set(codec, 0x1, false);
4245 break;
4246 case QUIRK_AE5:
4247 ae5_mmio_select_out(codec);
4248 ae5_headphone_gain_set(codec,
4249 spec->ae5_headphone_gain_val);
4250 tmp = FLOAT_ONE;
4251 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4252 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4253 chipio_set_control_param(codec, 0x0d, 0xa1);
4254 chipio_write(codec, 0x18b03c, 0x00000012);
4255 break;
4256 default:
4257 break;
4258 }
4259 break;
4260 case SURROUND_OUT:
4261 switch (ca0132_quirk(spec)) {
4262 case QUIRK_SBZ:
4263 ca0113_mmio_gpio_set(codec, 7, false);
4264 ca0113_mmio_gpio_set(codec, 4, true);
4265 ca0113_mmio_gpio_set(codec, 1, true);
4266 chipio_set_control_param(codec, 0x0d, 0x18);
4267 break;
4268 case QUIRK_ZXR:
4269 ca0113_mmio_gpio_set(codec, 2, true);
4270 ca0113_mmio_gpio_set(codec, 3, true);
4271 ca0113_mmio_gpio_set(codec, 5, false);
4272 zxr_headphone_gain_set(codec, 0);
4273 chipio_set_control_param(codec, 0x0d, 0x24);
4274 break;
4275 case QUIRK_R3DI:
4276 chipio_set_control_param(codec, 0x0d, 0x24);
4277 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4278 break;
4279 case QUIRK_R3D:
4280 ca0113_mmio_gpio_set(codec, 1, true);
4281 chipio_set_control_param(codec, 0x0d, 0x24);
4282 break;
4283 case QUIRK_AE5:
4284 ae5_mmio_select_out(codec);
4285 ae5_headphone_gain_set(codec, 2);
4286 tmp = FLOAT_ZERO;
4287 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4288 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4289 chipio_set_control_param(codec, 0x0d, 0xa4);
4290 chipio_write(codec, 0x18b03c, 0x00000012);
4291 break;
4292 default:
4293 break;
4294 }
4295 break;
4296 }
4297 }
4298
4299 /*
4300 * This function behaves similarly to the ca0132_select_out funciton above,
4301 * except with a few differences. It adds the ability to select the current
4302 * output with an enumerated control "output source" if the auto detect
4303 * mute switch is set to off. If the auto detect mute switch is enabled, it
4304 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4305 * It also adds the ability to auto-detect the front headphone port. The only
4306 * way to select surround is to disable auto detect, and set Surround with the
4307 * enumerated control.
4308 */
ca0132_alt_select_out(struct hda_codec * codec)4309 static int ca0132_alt_select_out(struct hda_codec *codec)
4310 {
4311 struct ca0132_spec *spec = codec->spec;
4312 unsigned int pin_ctl;
4313 int jack_present;
4314 int auto_jack;
4315 unsigned int i;
4316 unsigned int tmp;
4317 int err;
4318 /* Default Headphone is rear headphone */
4319 hda_nid_t headphone_nid = spec->out_pins[1];
4320
4321 codec_dbg(codec, "%s\n", __func__);
4322
4323 snd_hda_power_up_pm(codec);
4324
4325 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4326
4327 /*
4328 * If headphone rear or front is plugged in, set to headphone.
4329 * If neither is plugged in, set to rear line out. Only if
4330 * hp/speaker auto detect is enabled.
4331 */
4332 if (auto_jack) {
4333 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4334 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4335
4336 if (jack_present)
4337 spec->cur_out_type = HEADPHONE_OUT;
4338 else
4339 spec->cur_out_type = SPEAKER_OUT;
4340 } else
4341 spec->cur_out_type = spec->out_enum_val;
4342
4343 /* Begin DSP output switch */
4344 tmp = FLOAT_ONE;
4345 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
4346 if (err < 0)
4347 goto exit;
4348
4349 ca0132_alt_select_out_quirk_handler(codec);
4350
4351 switch (spec->cur_out_type) {
4352 case SPEAKER_OUT:
4353 codec_dbg(codec, "%s speaker\n", __func__);
4354
4355 /* disable headphone node */
4356 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4357 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4358 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4359 pin_ctl & ~PIN_HP);
4360 /* enable line-out node */
4361 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4362 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4363 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4364 pin_ctl | PIN_OUT);
4365 /* Enable EAPD */
4366 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4367 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4368
4369 /* If PlayEnhancement is enabled, set different source */
4370 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4371 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4372 else
4373 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4374 break;
4375 case HEADPHONE_OUT:
4376 codec_dbg(codec, "%s hp\n", __func__);
4377
4378 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4379 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4380
4381 /* disable speaker*/
4382 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4383 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4384 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4385 pin_ctl & ~PIN_HP);
4386
4387 /* enable headphone, either front or rear */
4388
4389 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4390 headphone_nid = spec->out_pins[2];
4391 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4392 headphone_nid = spec->out_pins[1];
4393
4394 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4395 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4396 snd_hda_set_pin_ctl(codec, headphone_nid,
4397 pin_ctl | PIN_HP);
4398
4399 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4400 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4401 else
4402 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4403 break;
4404 case SURROUND_OUT:
4405 codec_dbg(codec, "%s surround\n", __func__);
4406
4407 /* enable line out node */
4408 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4409 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4410 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4411 pin_ctl | PIN_OUT);
4412 /* Disable headphone out */
4413 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4414 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4415 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4416 pin_ctl & ~PIN_HP);
4417 /* Enable EAPD on line out */
4418 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4419 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4420 /* enable center/lfe out node */
4421 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4422 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4423 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4424 pin_ctl | PIN_OUT);
4425 /* Now set rear surround node as out. */
4426 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4427 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4428 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4429 pin_ctl | PIN_OUT);
4430
4431 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4432 break;
4433 }
4434 /*
4435 * Surround always sets it's scp command to req 0x04 to FLOAT_EIGHT.
4436 * With this set though, X_BASS cannot be enabled. So, if we have OutFX
4437 * enabled, we need to make sure X_BASS is off, otherwise everything
4438 * sounds all muffled. Running ca0132_effects_set with X_BASS as the
4439 * effect should sort this out.
4440 */
4441 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4442 ca0132_effects_set(codec, X_BASS,
4443 spec->effects_switch[X_BASS - EFFECT_START_NID]);
4444
4445 /* run through the output dsp commands for the selected output. */
4446 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4447 err = dspio_set_uint_param(codec,
4448 alt_out_presets[spec->cur_out_type].mids[i],
4449 alt_out_presets[spec->cur_out_type].reqs[i],
4450 alt_out_presets[spec->cur_out_type].vals[i]);
4451
4452 if (err < 0)
4453 goto exit;
4454 }
4455
4456 exit:
4457 snd_hda_power_down_pm(codec);
4458
4459 return err < 0 ? err : 0;
4460 }
4461
ca0132_unsol_hp_delayed(struct work_struct * work)4462 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4463 {
4464 struct ca0132_spec *spec = container_of(
4465 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4466 struct hda_jack_tbl *jack;
4467
4468 if (ca0132_use_alt_functions(spec))
4469 ca0132_alt_select_out(spec->codec);
4470 else
4471 ca0132_select_out(spec->codec);
4472
4473 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4474 if (jack) {
4475 jack->block_report = 0;
4476 snd_hda_jack_report_sync(spec->codec);
4477 }
4478 }
4479
4480 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4481 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4482 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4483 static int stop_mic1(struct hda_codec *codec);
4484 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4485 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4486
4487 /*
4488 * Select the active VIP source
4489 */
ca0132_set_vipsource(struct hda_codec * codec,int val)4490 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4491 {
4492 struct ca0132_spec *spec = codec->spec;
4493 unsigned int tmp;
4494
4495 if (spec->dsp_state != DSP_DOWNLOADED)
4496 return 0;
4497
4498 /* if CrystalVoice if off, vipsource should be 0 */
4499 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4500 (val == 0)) {
4501 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4502 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4503 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4504 if (spec->cur_mic_type == DIGITAL_MIC)
4505 tmp = FLOAT_TWO;
4506 else
4507 tmp = FLOAT_ONE;
4508 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4509 tmp = FLOAT_ZERO;
4510 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4511 } else {
4512 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4513 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4514 if (spec->cur_mic_type == DIGITAL_MIC)
4515 tmp = FLOAT_TWO;
4516 else
4517 tmp = FLOAT_ONE;
4518 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4519 tmp = FLOAT_ONE;
4520 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4521 msleep(20);
4522 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4523 }
4524
4525 return 1;
4526 }
4527
ca0132_alt_set_vipsource(struct hda_codec * codec,int val)4528 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4529 {
4530 struct ca0132_spec *spec = codec->spec;
4531 unsigned int tmp;
4532
4533 if (spec->dsp_state != DSP_DOWNLOADED)
4534 return 0;
4535
4536 codec_dbg(codec, "%s\n", __func__);
4537
4538 chipio_set_stream_control(codec, 0x03, 0);
4539 chipio_set_stream_control(codec, 0x04, 0);
4540
4541 /* if CrystalVoice is off, vipsource should be 0 */
4542 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4543 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4544 codec_dbg(codec, "%s: off.", __func__);
4545 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4546
4547 tmp = FLOAT_ZERO;
4548 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4549
4550 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4551 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4552 if (ca0132_quirk(spec) == QUIRK_R3DI)
4553 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4554
4555
4556 if (spec->in_enum_val == REAR_LINE_IN)
4557 tmp = FLOAT_ZERO;
4558 else {
4559 if (ca0132_quirk(spec) == QUIRK_SBZ)
4560 tmp = FLOAT_THREE;
4561 else
4562 tmp = FLOAT_ONE;
4563 }
4564
4565 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4566
4567 } else {
4568 codec_dbg(codec, "%s: on.", __func__);
4569 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4570 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4571 if (ca0132_quirk(spec) == QUIRK_R3DI)
4572 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4573
4574 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4575 tmp = FLOAT_TWO;
4576 else
4577 tmp = FLOAT_ONE;
4578 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4579
4580 tmp = FLOAT_ONE;
4581 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4582
4583 msleep(20);
4584 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4585 }
4586
4587 chipio_set_stream_control(codec, 0x03, 1);
4588 chipio_set_stream_control(codec, 0x04, 1);
4589
4590 return 1;
4591 }
4592
4593 /*
4594 * Select the active microphone.
4595 * If autodetect is enabled, mic will be selected based on jack detection.
4596 * If jack inserted, ext.mic will be selected, else built-in mic
4597 * If autodetect is disabled, mic will be selected based on selection.
4598 */
ca0132_select_mic(struct hda_codec * codec)4599 static int ca0132_select_mic(struct hda_codec *codec)
4600 {
4601 struct ca0132_spec *spec = codec->spec;
4602 int jack_present;
4603 int auto_jack;
4604
4605 codec_dbg(codec, "ca0132_select_mic\n");
4606
4607 snd_hda_power_up_pm(codec);
4608
4609 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4610
4611 if (auto_jack)
4612 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
4613 else
4614 jack_present =
4615 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4616
4617 if (jack_present)
4618 spec->cur_mic_type = LINE_MIC_IN;
4619 else
4620 spec->cur_mic_type = DIGITAL_MIC;
4621
4622 if (spec->cur_mic_type == DIGITAL_MIC) {
4623 /* enable digital Mic */
4624 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4625 ca0132_set_dmic(codec, 1);
4626 ca0132_mic_boost_set(codec, 0);
4627 /* set voice focus */
4628 ca0132_effects_set(codec, VOICE_FOCUS,
4629 spec->effects_switch
4630 [VOICE_FOCUS - EFFECT_START_NID]);
4631 } else {
4632 /* disable digital Mic */
4633 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4634 ca0132_set_dmic(codec, 0);
4635 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4636 /* disable voice focus */
4637 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4638 }
4639
4640 snd_hda_power_down_pm(codec);
4641
4642 return 0;
4643 }
4644
4645 /*
4646 * Select the active input.
4647 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4648 * The front mic has no jack-detection, so the only way to switch to it
4649 * is to do it manually in alsamixer.
4650 */
ca0132_alt_select_in(struct hda_codec * codec)4651 static int ca0132_alt_select_in(struct hda_codec *codec)
4652 {
4653 struct ca0132_spec *spec = codec->spec;
4654 unsigned int tmp;
4655
4656 codec_dbg(codec, "%s\n", __func__);
4657
4658 snd_hda_power_up_pm(codec);
4659
4660 chipio_set_stream_control(codec, 0x03, 0);
4661 chipio_set_stream_control(codec, 0x04, 0);
4662
4663 spec->cur_mic_type = spec->in_enum_val;
4664
4665 switch (spec->cur_mic_type) {
4666 case REAR_MIC:
4667 switch (ca0132_quirk(spec)) {
4668 case QUIRK_SBZ:
4669 case QUIRK_R3D:
4670 ca0113_mmio_gpio_set(codec, 0, false);
4671 tmp = FLOAT_THREE;
4672 break;
4673 case QUIRK_ZXR:
4674 tmp = FLOAT_THREE;
4675 break;
4676 case QUIRK_R3DI:
4677 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4678 tmp = FLOAT_ONE;
4679 break;
4680 case QUIRK_AE5:
4681 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
4682 tmp = FLOAT_THREE;
4683 break;
4684 case QUIRK_AE7:
4685 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
4686 tmp = FLOAT_THREE;
4687 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
4688 SR_96_000);
4689 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
4690 SR_96_000);
4691 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
4692 break;
4693 default:
4694 tmp = FLOAT_ONE;
4695 break;
4696 }
4697
4698 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4699 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4700 if (ca0132_quirk(spec) == QUIRK_R3DI)
4701 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4702
4703 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4704
4705 chipio_set_stream_control(codec, 0x03, 1);
4706 chipio_set_stream_control(codec, 0x04, 1);
4707 switch (ca0132_quirk(spec)) {
4708 case QUIRK_SBZ:
4709 chipio_write(codec, 0x18B098, 0x0000000C);
4710 chipio_write(codec, 0x18B09C, 0x0000000C);
4711 break;
4712 case QUIRK_ZXR:
4713 chipio_write(codec, 0x18B098, 0x0000000C);
4714 chipio_write(codec, 0x18B09C, 0x000000CC);
4715 break;
4716 case QUIRK_AE5:
4717 chipio_write(codec, 0x18B098, 0x0000000C);
4718 chipio_write(codec, 0x18B09C, 0x0000004C);
4719 break;
4720 default:
4721 break;
4722 }
4723 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4724 break;
4725 case REAR_LINE_IN:
4726 ca0132_mic_boost_set(codec, 0);
4727 switch (ca0132_quirk(spec)) {
4728 case QUIRK_SBZ:
4729 case QUIRK_R3D:
4730 ca0113_mmio_gpio_set(codec, 0, false);
4731 break;
4732 case QUIRK_R3DI:
4733 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4734 break;
4735 case QUIRK_AE5:
4736 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
4737 break;
4738 case QUIRK_AE7:
4739 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
4740 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
4741 SR_96_000);
4742 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
4743 SR_96_000);
4744 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
4745 break;
4746 default:
4747 break;
4748 }
4749
4750 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4751 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4752 if (ca0132_quirk(spec) == QUIRK_R3DI)
4753 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4754
4755 if (ca0132_quirk(spec) == QUIRK_AE7)
4756 tmp = FLOAT_THREE;
4757 else
4758 tmp = FLOAT_ZERO;
4759 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4760
4761 switch (ca0132_quirk(spec)) {
4762 case QUIRK_SBZ:
4763 case QUIRK_AE5:
4764 chipio_write(codec, 0x18B098, 0x00000000);
4765 chipio_write(codec, 0x18B09C, 0x00000000);
4766 break;
4767 default:
4768 break;
4769 }
4770 chipio_set_stream_control(codec, 0x03, 1);
4771 chipio_set_stream_control(codec, 0x04, 1);
4772 break;
4773 case FRONT_MIC:
4774 switch (ca0132_quirk(spec)) {
4775 case QUIRK_SBZ:
4776 case QUIRK_R3D:
4777 ca0113_mmio_gpio_set(codec, 0, true);
4778 ca0113_mmio_gpio_set(codec, 5, false);
4779 tmp = FLOAT_THREE;
4780 break;
4781 case QUIRK_R3DI:
4782 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4783 tmp = FLOAT_ONE;
4784 break;
4785 case QUIRK_AE5:
4786 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
4787 tmp = FLOAT_THREE;
4788 break;
4789 default:
4790 tmp = FLOAT_ONE;
4791 break;
4792 }
4793
4794 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4795 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4796 if (ca0132_quirk(spec) == QUIRK_R3DI)
4797 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4798
4799 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4800
4801 chipio_set_stream_control(codec, 0x03, 1);
4802 chipio_set_stream_control(codec, 0x04, 1);
4803
4804 switch (ca0132_quirk(spec)) {
4805 case QUIRK_SBZ:
4806 chipio_write(codec, 0x18B098, 0x0000000C);
4807 chipio_write(codec, 0x18B09C, 0x000000CC);
4808 break;
4809 case QUIRK_AE5:
4810 chipio_write(codec, 0x18B098, 0x0000000C);
4811 chipio_write(codec, 0x18B09C, 0x0000004C);
4812 break;
4813 default:
4814 break;
4815 }
4816 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4817 break;
4818 }
4819 ca0132_cvoice_switch_set(codec);
4820
4821 snd_hda_power_down_pm(codec);
4822 return 0;
4823 }
4824
4825 /*
4826 * Check if VNODE settings take effect immediately.
4827 */
ca0132_is_vnode_effective(struct hda_codec * codec,hda_nid_t vnid,hda_nid_t * shared_nid)4828 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4829 hda_nid_t vnid,
4830 hda_nid_t *shared_nid)
4831 {
4832 struct ca0132_spec *spec = codec->spec;
4833 hda_nid_t nid;
4834
4835 switch (vnid) {
4836 case VNID_SPK:
4837 nid = spec->shared_out_nid;
4838 break;
4839 case VNID_MIC:
4840 nid = spec->shared_mic_nid;
4841 break;
4842 default:
4843 return false;
4844 }
4845
4846 if (shared_nid)
4847 *shared_nid = nid;
4848
4849 return true;
4850 }
4851
4852 /*
4853 * The following functions are control change helpers.
4854 * They return 0 if no changed. Return 1 if changed.
4855 */
ca0132_voicefx_set(struct hda_codec * codec,int enable)4856 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4857 {
4858 struct ca0132_spec *spec = codec->spec;
4859 unsigned int tmp;
4860
4861 /* based on CrystalVoice state to enable VoiceFX. */
4862 if (enable) {
4863 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4864 FLOAT_ONE : FLOAT_ZERO;
4865 } else {
4866 tmp = FLOAT_ZERO;
4867 }
4868
4869 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4870 ca0132_voicefx.reqs[0], tmp);
4871
4872 return 1;
4873 }
4874
4875 /*
4876 * Set the effects parameters
4877 */
ca0132_effects_set(struct hda_codec * codec,hda_nid_t nid,long val)4878 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4879 {
4880 struct ca0132_spec *spec = codec->spec;
4881 unsigned int on, tmp;
4882 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4883 int err = 0;
4884 int idx = nid - EFFECT_START_NID;
4885
4886 if ((idx < 0) || (idx >= num_fx))
4887 return 0; /* no changed */
4888
4889 /* for out effect, qualify with PE */
4890 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4891 /* if PE if off, turn off out effects. */
4892 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4893 val = 0;
4894 if (spec->cur_out_type == SURROUND_OUT && nid == X_BASS)
4895 val = 0;
4896 }
4897
4898 /* for in effect, qualify with CrystalVoice */
4899 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4900 /* if CrystalVoice if off, turn off in effects. */
4901 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4902 val = 0;
4903
4904 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4905 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4906 val = 0;
4907
4908 /* If Voice Focus on SBZ, set to two channel. */
4909 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
4910 && (spec->cur_mic_type != REAR_LINE_IN)) {
4911 if (spec->effects_switch[CRYSTAL_VOICE -
4912 EFFECT_START_NID]) {
4913
4914 if (spec->effects_switch[VOICE_FOCUS -
4915 EFFECT_START_NID]) {
4916 tmp = FLOAT_TWO;
4917 val = 1;
4918 } else
4919 tmp = FLOAT_ONE;
4920
4921 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4922 }
4923 }
4924 /*
4925 * For SBZ noise reduction, there's an extra command
4926 * to module ID 0x47. No clue why.
4927 */
4928 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
4929 && (spec->cur_mic_type != REAR_LINE_IN)) {
4930 if (spec->effects_switch[CRYSTAL_VOICE -
4931 EFFECT_START_NID]) {
4932 if (spec->effects_switch[NOISE_REDUCTION -
4933 EFFECT_START_NID])
4934 tmp = FLOAT_ONE;
4935 else
4936 tmp = FLOAT_ZERO;
4937 } else
4938 tmp = FLOAT_ZERO;
4939
4940 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4941 }
4942
4943 /* If rear line in disable effects. */
4944 if (ca0132_use_alt_functions(spec) &&
4945 spec->in_enum_val == REAR_LINE_IN)
4946 val = 0;
4947 }
4948
4949 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
4950 nid, val);
4951
4952 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4953 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4954 ca0132_effects[idx].reqs[0], on);
4955
4956 if (err < 0)
4957 return 0; /* no changed */
4958
4959 return 1;
4960 }
4961
4962 /*
4963 * Turn on/off Playback Enhancements
4964 */
ca0132_pe_switch_set(struct hda_codec * codec)4965 static int ca0132_pe_switch_set(struct hda_codec *codec)
4966 {
4967 struct ca0132_spec *spec = codec->spec;
4968 hda_nid_t nid;
4969 int i, ret = 0;
4970
4971 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
4972 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4973
4974 if (ca0132_use_alt_functions(spec))
4975 ca0132_alt_select_out(codec);
4976
4977 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4978 nid = OUT_EFFECT_START_NID;
4979 /* PE affects all out effects */
4980 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4981 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4982
4983 return ret;
4984 }
4985
4986 /* Check if Mic1 is streaming, if so, stop streaming */
stop_mic1(struct hda_codec * codec)4987 static int stop_mic1(struct hda_codec *codec)
4988 {
4989 struct ca0132_spec *spec = codec->spec;
4990 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4991 AC_VERB_GET_CONV, 0);
4992 if (oldval != 0)
4993 snd_hda_codec_write(codec, spec->adcs[0], 0,
4994 AC_VERB_SET_CHANNEL_STREAMID,
4995 0);
4996 return oldval;
4997 }
4998
4999 /* Resume Mic1 streaming if it was stopped. */
resume_mic1(struct hda_codec * codec,unsigned int oldval)5000 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
5001 {
5002 struct ca0132_spec *spec = codec->spec;
5003 /* Restore the previous stream and channel */
5004 if (oldval != 0)
5005 snd_hda_codec_write(codec, spec->adcs[0], 0,
5006 AC_VERB_SET_CHANNEL_STREAMID,
5007 oldval);
5008 }
5009
5010 /*
5011 * Turn on/off CrystalVoice
5012 */
ca0132_cvoice_switch_set(struct hda_codec * codec)5013 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
5014 {
5015 struct ca0132_spec *spec = codec->spec;
5016 hda_nid_t nid;
5017 int i, ret = 0;
5018 unsigned int oldval;
5019
5020 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
5021 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5022
5023 i = IN_EFFECT_START_NID - EFFECT_START_NID;
5024 nid = IN_EFFECT_START_NID;
5025 /* CrystalVoice affects all in effects */
5026 for (; nid < IN_EFFECT_END_NID; nid++, i++)
5027 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5028
5029 /* including VoiceFX */
5030 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5031
5032 /* set correct vipsource */
5033 oldval = stop_mic1(codec);
5034 if (ca0132_use_alt_functions(spec))
5035 ret |= ca0132_alt_set_vipsource(codec, 1);
5036 else
5037 ret |= ca0132_set_vipsource(codec, 1);
5038 resume_mic1(codec, oldval);
5039 return ret;
5040 }
5041
ca0132_mic_boost_set(struct hda_codec * codec,long val)5042 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5043 {
5044 struct ca0132_spec *spec = codec->spec;
5045 int ret = 0;
5046
5047 if (val) /* on */
5048 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5049 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5050 else /* off */
5051 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5052 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5053
5054 return ret;
5055 }
5056
ca0132_alt_mic_boost_set(struct hda_codec * codec,long val)5057 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5058 {
5059 struct ca0132_spec *spec = codec->spec;
5060 int ret = 0;
5061
5062 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5063 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5064 return ret;
5065 }
5066
ae5_headphone_gain_set(struct hda_codec * codec,long val)5067 static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5068 {
5069 unsigned int i;
5070
5071 for (i = 0; i < 4; i++)
5072 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5073 ae5_headphone_gain_presets[val].vals[i]);
5074 return 0;
5075 }
5076
5077 /*
5078 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5079 * amplifier to handle a 600 ohm load.
5080 */
zxr_headphone_gain_set(struct hda_codec * codec,long val)5081 static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5082 {
5083 ca0113_mmio_gpio_set(codec, 1, val);
5084
5085 return 0;
5086 }
5087
ca0132_vnode_switch_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5088 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5089 struct snd_ctl_elem_value *ucontrol)
5090 {
5091 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5092 hda_nid_t nid = get_amp_nid(kcontrol);
5093 hda_nid_t shared_nid = 0;
5094 bool effective;
5095 int ret = 0;
5096 struct ca0132_spec *spec = codec->spec;
5097 int auto_jack;
5098
5099 if (nid == VNID_HP_SEL) {
5100 auto_jack =
5101 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5102 if (!auto_jack) {
5103 if (ca0132_use_alt_functions(spec))
5104 ca0132_alt_select_out(codec);
5105 else
5106 ca0132_select_out(codec);
5107 }
5108 return 1;
5109 }
5110
5111 if (nid == VNID_AMIC1_SEL) {
5112 auto_jack =
5113 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5114 if (!auto_jack)
5115 ca0132_select_mic(codec);
5116 return 1;
5117 }
5118
5119 if (nid == VNID_HP_ASEL) {
5120 if (ca0132_use_alt_functions(spec))
5121 ca0132_alt_select_out(codec);
5122 else
5123 ca0132_select_out(codec);
5124 return 1;
5125 }
5126
5127 if (nid == VNID_AMIC1_ASEL) {
5128 ca0132_select_mic(codec);
5129 return 1;
5130 }
5131
5132 /* if effective conditions, then update hw immediately. */
5133 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5134 if (effective) {
5135 int dir = get_amp_direction(kcontrol);
5136 int ch = get_amp_channels(kcontrol);
5137 unsigned long pval;
5138
5139 mutex_lock(&codec->control_mutex);
5140 pval = kcontrol->private_value;
5141 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5142 0, dir);
5143 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5144 kcontrol->private_value = pval;
5145 mutex_unlock(&codec->control_mutex);
5146 }
5147
5148 return ret;
5149 }
5150 /* End of control change helpers. */
5151 /*
5152 * Below I've added controls to mess with the effect levels, I've only enabled
5153 * them on the Sound Blaster Z, but they would probably also work on the
5154 * Chromebook. I figured they were probably tuned specifically for it, and left
5155 * out for a reason.
5156 */
5157
5158 /* Sets DSP effect level from the sliders above the controls */
ca0132_alt_slider_ctl_set(struct hda_codec * codec,hda_nid_t nid,const unsigned int * lookup,int idx)5159 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5160 const unsigned int *lookup, int idx)
5161 {
5162 int i = 0;
5163 unsigned int y;
5164 /*
5165 * For X_BASS, req 2 is actually crossover freq instead of
5166 * effect level
5167 */
5168 if (nid == X_BASS)
5169 y = 2;
5170 else
5171 y = 1;
5172
5173 snd_hda_power_up(codec);
5174 if (nid == XBASS_XOVER) {
5175 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5176 if (ca0132_effects[i].nid == X_BASS)
5177 break;
5178
5179 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5180 ca0132_effects[i].reqs[1],
5181 &(lookup[idx - 1]), sizeof(unsigned int));
5182 } else {
5183 /* Find the actual effect structure */
5184 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5185 if (nid == ca0132_effects[i].nid)
5186 break;
5187
5188 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5189 ca0132_effects[i].reqs[y],
5190 &(lookup[idx]), sizeof(unsigned int));
5191 }
5192
5193 snd_hda_power_down(codec);
5194
5195 return 0;
5196 }
5197
ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5198 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5199 struct snd_ctl_elem_value *ucontrol)
5200 {
5201 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5202 struct ca0132_spec *spec = codec->spec;
5203 long *valp = ucontrol->value.integer.value;
5204
5205 *valp = spec->xbass_xover_freq;
5206 return 0;
5207 }
5208
ca0132_alt_slider_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5209 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5210 struct snd_ctl_elem_value *ucontrol)
5211 {
5212 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5213 struct ca0132_spec *spec = codec->spec;
5214 hda_nid_t nid = get_amp_nid(kcontrol);
5215 long *valp = ucontrol->value.integer.value;
5216 int idx = nid - OUT_EFFECT_START_NID;
5217
5218 *valp = spec->fx_ctl_val[idx];
5219 return 0;
5220 }
5221
5222 /*
5223 * The X-bass crossover starts at 10hz, so the min is 1. The
5224 * frequency is set in multiples of 10.
5225 */
ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5226 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5227 struct snd_ctl_elem_info *uinfo)
5228 {
5229 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5230 uinfo->count = 1;
5231 uinfo->value.integer.min = 1;
5232 uinfo->value.integer.max = 100;
5233 uinfo->value.integer.step = 1;
5234
5235 return 0;
5236 }
5237
ca0132_alt_effect_slider_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5238 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5239 struct snd_ctl_elem_info *uinfo)
5240 {
5241 int chs = get_amp_channels(kcontrol);
5242
5243 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5244 uinfo->count = chs == 3 ? 2 : 1;
5245 uinfo->value.integer.min = 0;
5246 uinfo->value.integer.max = 100;
5247 uinfo->value.integer.step = 1;
5248
5249 return 0;
5250 }
5251
ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5252 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5253 struct snd_ctl_elem_value *ucontrol)
5254 {
5255 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5256 struct ca0132_spec *spec = codec->spec;
5257 hda_nid_t nid = get_amp_nid(kcontrol);
5258 long *valp = ucontrol->value.integer.value;
5259 int idx;
5260
5261 /* any change? */
5262 if (spec->xbass_xover_freq == *valp)
5263 return 0;
5264
5265 spec->xbass_xover_freq = *valp;
5266
5267 idx = *valp;
5268 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5269
5270 return 0;
5271 }
5272
ca0132_alt_effect_slider_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5273 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5274 struct snd_ctl_elem_value *ucontrol)
5275 {
5276 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5277 struct ca0132_spec *spec = codec->spec;
5278 hda_nid_t nid = get_amp_nid(kcontrol);
5279 long *valp = ucontrol->value.integer.value;
5280 int idx;
5281
5282 idx = nid - EFFECT_START_NID;
5283 /* any change? */
5284 if (spec->fx_ctl_val[idx] == *valp)
5285 return 0;
5286
5287 spec->fx_ctl_val[idx] = *valp;
5288
5289 idx = *valp;
5290 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5291
5292 return 0;
5293 }
5294
5295
5296 /*
5297 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5298 * only has off or full 30 dB, and didn't like making a volume slider that has
5299 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5300 */
5301 #define MIC_BOOST_NUM_OF_STEPS 4
5302 #define MIC_BOOST_ENUM_MAX_STRLEN 10
5303
ca0132_alt_mic_boost_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5304 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5305 struct snd_ctl_elem_info *uinfo)
5306 {
5307 char *sfx = "dB";
5308 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5309
5310 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5311 uinfo->count = 1;
5312 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5313 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5314 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5315 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5316 strcpy(uinfo->value.enumerated.name, namestr);
5317 return 0;
5318 }
5319
ca0132_alt_mic_boost_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5320 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5321 struct snd_ctl_elem_value *ucontrol)
5322 {
5323 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5324 struct ca0132_spec *spec = codec->spec;
5325
5326 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5327 return 0;
5328 }
5329
ca0132_alt_mic_boost_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5330 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5331 struct snd_ctl_elem_value *ucontrol)
5332 {
5333 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5334 struct ca0132_spec *spec = codec->spec;
5335 int sel = ucontrol->value.enumerated.item[0];
5336 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5337
5338 if (sel >= items)
5339 return 0;
5340
5341 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5342 sel);
5343
5344 spec->mic_boost_enum_val = sel;
5345
5346 if (spec->in_enum_val != REAR_LINE_IN)
5347 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5348
5349 return 1;
5350 }
5351
5352 /*
5353 * Sound BlasterX AE-5 Headphone Gain Controls.
5354 */
5355 #define AE5_HEADPHONE_GAIN_MAX 3
ae5_headphone_gain_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5356 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5357 struct snd_ctl_elem_info *uinfo)
5358 {
5359 char *sfx = " Ohms)";
5360 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5361
5362 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5363 uinfo->count = 1;
5364 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5365 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5366 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5367 sprintf(namestr, "%s %s",
5368 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5369 sfx);
5370 strcpy(uinfo->value.enumerated.name, namestr);
5371 return 0;
5372 }
5373
ae5_headphone_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5374 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5375 struct snd_ctl_elem_value *ucontrol)
5376 {
5377 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5378 struct ca0132_spec *spec = codec->spec;
5379
5380 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5381 return 0;
5382 }
5383
ae5_headphone_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5384 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5385 struct snd_ctl_elem_value *ucontrol)
5386 {
5387 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5388 struct ca0132_spec *spec = codec->spec;
5389 int sel = ucontrol->value.enumerated.item[0];
5390 unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5391
5392 if (sel >= items)
5393 return 0;
5394
5395 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5396 sel);
5397
5398 spec->ae5_headphone_gain_val = sel;
5399
5400 if (spec->out_enum_val == HEADPHONE_OUT)
5401 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5402
5403 return 1;
5404 }
5405
5406 /*
5407 * Sound BlasterX AE-5 sound filter enumerated control.
5408 */
5409 #define AE5_SOUND_FILTER_MAX 3
5410
ae5_sound_filter_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5411 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5412 struct snd_ctl_elem_info *uinfo)
5413 {
5414 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5415
5416 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5417 uinfo->count = 1;
5418 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5419 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5420 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5421 sprintf(namestr, "%s",
5422 ae5_filter_presets[uinfo->value.enumerated.item].name);
5423 strcpy(uinfo->value.enumerated.name, namestr);
5424 return 0;
5425 }
5426
ae5_sound_filter_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5427 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5428 struct snd_ctl_elem_value *ucontrol)
5429 {
5430 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5431 struct ca0132_spec *spec = codec->spec;
5432
5433 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5434 return 0;
5435 }
5436
ae5_sound_filter_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5437 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5438 struct snd_ctl_elem_value *ucontrol)
5439 {
5440 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5441 struct ca0132_spec *spec = codec->spec;
5442 int sel = ucontrol->value.enumerated.item[0];
5443 unsigned int items = AE5_SOUND_FILTER_MAX;
5444
5445 if (sel >= items)
5446 return 0;
5447
5448 codec_dbg(codec, "ae5_sound_filter: %s\n",
5449 ae5_filter_presets[sel].name);
5450
5451 spec->ae5_filter_val = sel;
5452
5453 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5454 ae5_filter_presets[sel].val);
5455
5456 return 1;
5457 }
5458
5459 /*
5460 * Input Select Control for alternative ca0132 codecs. This exists because
5461 * front microphone has no auto-detect, and we need a way to set the rear
5462 * as line-in
5463 */
ca0132_alt_input_source_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5464 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5465 struct snd_ctl_elem_info *uinfo)
5466 {
5467 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5468 uinfo->count = 1;
5469 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5470 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5471 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5472 strcpy(uinfo->value.enumerated.name,
5473 in_src_str[uinfo->value.enumerated.item]);
5474 return 0;
5475 }
5476
ca0132_alt_input_source_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5477 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5478 struct snd_ctl_elem_value *ucontrol)
5479 {
5480 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5481 struct ca0132_spec *spec = codec->spec;
5482
5483 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5484 return 0;
5485 }
5486
ca0132_alt_input_source_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5487 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5488 struct snd_ctl_elem_value *ucontrol)
5489 {
5490 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5491 struct ca0132_spec *spec = codec->spec;
5492 int sel = ucontrol->value.enumerated.item[0];
5493 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5494
5495 if (sel >= items)
5496 return 0;
5497
5498 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5499 sel, in_src_str[sel]);
5500
5501 spec->in_enum_val = sel;
5502
5503 ca0132_alt_select_in(codec);
5504
5505 return 1;
5506 }
5507
5508 /* Sound Blaster Z Output Select Control */
ca0132_alt_output_select_get_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5509 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5510 struct snd_ctl_elem_info *uinfo)
5511 {
5512 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5513 uinfo->count = 1;
5514 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5515 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5516 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5517 strcpy(uinfo->value.enumerated.name,
5518 alt_out_presets[uinfo->value.enumerated.item].name);
5519 return 0;
5520 }
5521
ca0132_alt_output_select_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5522 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5523 struct snd_ctl_elem_value *ucontrol)
5524 {
5525 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5526 struct ca0132_spec *spec = codec->spec;
5527
5528 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5529 return 0;
5530 }
5531
ca0132_alt_output_select_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5532 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5533 struct snd_ctl_elem_value *ucontrol)
5534 {
5535 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5536 struct ca0132_spec *spec = codec->spec;
5537 int sel = ucontrol->value.enumerated.item[0];
5538 unsigned int items = NUM_OF_OUTPUTS;
5539 unsigned int auto_jack;
5540
5541 if (sel >= items)
5542 return 0;
5543
5544 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5545 sel, alt_out_presets[sel].name);
5546
5547 spec->out_enum_val = sel;
5548
5549 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5550
5551 if (!auto_jack)
5552 ca0132_alt_select_out(codec);
5553
5554 return 1;
5555 }
5556
5557 /*
5558 * Smart Volume output setting control. Three different settings, Normal,
5559 * which takes the value from the smart volume slider. The two others, loud
5560 * and night, disregard the slider value and have uneditable values.
5561 */
5562 #define NUM_OF_SVM_SETTINGS 3
5563 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
5564
ca0132_alt_svm_setting_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5565 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5566 struct snd_ctl_elem_info *uinfo)
5567 {
5568 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5569 uinfo->count = 1;
5570 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5571 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5572 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5573 strcpy(uinfo->value.enumerated.name,
5574 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5575 return 0;
5576 }
5577
ca0132_alt_svm_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5578 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5579 struct snd_ctl_elem_value *ucontrol)
5580 {
5581 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5582 struct ca0132_spec *spec = codec->spec;
5583
5584 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5585 return 0;
5586 }
5587
ca0132_alt_svm_setting_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5588 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5589 struct snd_ctl_elem_value *ucontrol)
5590 {
5591 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5592 struct ca0132_spec *spec = codec->spec;
5593 int sel = ucontrol->value.enumerated.item[0];
5594 unsigned int items = NUM_OF_SVM_SETTINGS;
5595 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5596 unsigned int tmp;
5597
5598 if (sel >= items)
5599 return 0;
5600
5601 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5602 sel, out_svm_set_enum_str[sel]);
5603
5604 spec->smart_volume_setting = sel;
5605
5606 switch (sel) {
5607 case 0:
5608 tmp = FLOAT_ZERO;
5609 break;
5610 case 1:
5611 tmp = FLOAT_ONE;
5612 break;
5613 case 2:
5614 tmp = FLOAT_TWO;
5615 break;
5616 default:
5617 tmp = FLOAT_ZERO;
5618 break;
5619 }
5620 /* Req 2 is the Smart Volume Setting req. */
5621 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5622 ca0132_effects[idx].reqs[2], tmp);
5623 return 1;
5624 }
5625
5626 /* Sound Blaster Z EQ preset controls */
ca0132_alt_eq_preset_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5627 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5628 struct snd_ctl_elem_info *uinfo)
5629 {
5630 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5631
5632 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5633 uinfo->count = 1;
5634 uinfo->value.enumerated.items = items;
5635 if (uinfo->value.enumerated.item >= items)
5636 uinfo->value.enumerated.item = items - 1;
5637 strcpy(uinfo->value.enumerated.name,
5638 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5639 return 0;
5640 }
5641
ca0132_alt_eq_preset_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5642 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5643 struct snd_ctl_elem_value *ucontrol)
5644 {
5645 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5646 struct ca0132_spec *spec = codec->spec;
5647
5648 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5649 return 0;
5650 }
5651
ca0132_alt_eq_preset_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5652 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5653 struct snd_ctl_elem_value *ucontrol)
5654 {
5655 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5656 struct ca0132_spec *spec = codec->spec;
5657 int i, err = 0;
5658 int sel = ucontrol->value.enumerated.item[0];
5659 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5660
5661 if (sel >= items)
5662 return 0;
5663
5664 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5665 ca0132_alt_eq_presets[sel].name);
5666 /*
5667 * Idx 0 is default.
5668 * Default needs to qualify with CrystalVoice state.
5669 */
5670 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5671 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5672 ca0132_alt_eq_enum.reqs[i],
5673 ca0132_alt_eq_presets[sel].vals[i]);
5674 if (err < 0)
5675 break;
5676 }
5677
5678 if (err >= 0)
5679 spec->eq_preset_val = sel;
5680
5681 return 1;
5682 }
5683
ca0132_voicefx_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5684 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5685 struct snd_ctl_elem_info *uinfo)
5686 {
5687 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
5688
5689 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5690 uinfo->count = 1;
5691 uinfo->value.enumerated.items = items;
5692 if (uinfo->value.enumerated.item >= items)
5693 uinfo->value.enumerated.item = items - 1;
5694 strcpy(uinfo->value.enumerated.name,
5695 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5696 return 0;
5697 }
5698
ca0132_voicefx_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5699 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
5700 struct snd_ctl_elem_value *ucontrol)
5701 {
5702 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5703 struct ca0132_spec *spec = codec->spec;
5704
5705 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
5706 return 0;
5707 }
5708
ca0132_voicefx_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5709 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
5710 struct snd_ctl_elem_value *ucontrol)
5711 {
5712 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5713 struct ca0132_spec *spec = codec->spec;
5714 int i, err = 0;
5715 int sel = ucontrol->value.enumerated.item[0];
5716
5717 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
5718 return 0;
5719
5720 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
5721 sel, ca0132_voicefx_presets[sel].name);
5722
5723 /*
5724 * Idx 0 is default.
5725 * Default needs to qualify with CrystalVoice state.
5726 */
5727 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5728 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5729 ca0132_voicefx.reqs[i],
5730 ca0132_voicefx_presets[sel].vals[i]);
5731 if (err < 0)
5732 break;
5733 }
5734
5735 if (err >= 0) {
5736 spec->voicefx_val = sel;
5737 /* enable voice fx */
5738 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5739 }
5740
5741 return 1;
5742 }
5743
ca0132_switch_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5744 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5745 struct snd_ctl_elem_value *ucontrol)
5746 {
5747 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5748 struct ca0132_spec *spec = codec->spec;
5749 hda_nid_t nid = get_amp_nid(kcontrol);
5750 int ch = get_amp_channels(kcontrol);
5751 long *valp = ucontrol->value.integer.value;
5752
5753 /* vnode */
5754 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5755 if (ch & 1) {
5756 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5757 valp++;
5758 }
5759 if (ch & 2) {
5760 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5761 valp++;
5762 }
5763 return 0;
5764 }
5765
5766 /* effects, include PE and CrystalVoice */
5767 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5768 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5769 return 0;
5770 }
5771
5772 /* mic boost */
5773 if (nid == spec->input_pins[0]) {
5774 *valp = spec->cur_mic_boost;
5775 return 0;
5776 }
5777
5778 if (nid == ZXR_HEADPHONE_GAIN) {
5779 *valp = spec->zxr_gain_set;
5780 return 0;
5781 }
5782
5783 return 0;
5784 }
5785
ca0132_switch_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5786 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5787 struct snd_ctl_elem_value *ucontrol)
5788 {
5789 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5790 struct ca0132_spec *spec = codec->spec;
5791 hda_nid_t nid = get_amp_nid(kcontrol);
5792 int ch = get_amp_channels(kcontrol);
5793 long *valp = ucontrol->value.integer.value;
5794 int changed = 1;
5795
5796 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
5797 nid, *valp);
5798
5799 snd_hda_power_up(codec);
5800 /* vnode */
5801 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5802 if (ch & 1) {
5803 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5804 valp++;
5805 }
5806 if (ch & 2) {
5807 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5808 valp++;
5809 }
5810 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5811 goto exit;
5812 }
5813
5814 /* PE */
5815 if (nid == PLAY_ENHANCEMENT) {
5816 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5817 changed = ca0132_pe_switch_set(codec);
5818 goto exit;
5819 }
5820
5821 /* CrystalVoice */
5822 if (nid == CRYSTAL_VOICE) {
5823 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5824 changed = ca0132_cvoice_switch_set(codec);
5825 goto exit;
5826 }
5827
5828 /* out and in effects */
5829 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5830 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5831 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5832 changed = ca0132_effects_set(codec, nid, *valp);
5833 goto exit;
5834 }
5835
5836 /* mic boost */
5837 if (nid == spec->input_pins[0]) {
5838 spec->cur_mic_boost = *valp;
5839 if (ca0132_use_alt_functions(spec)) {
5840 if (spec->in_enum_val != REAR_LINE_IN)
5841 changed = ca0132_mic_boost_set(codec, *valp);
5842 } else {
5843 /* Mic boost does not apply to Digital Mic */
5844 if (spec->cur_mic_type != DIGITAL_MIC)
5845 changed = ca0132_mic_boost_set(codec, *valp);
5846 }
5847
5848 goto exit;
5849 }
5850
5851 if (nid == ZXR_HEADPHONE_GAIN) {
5852 spec->zxr_gain_set = *valp;
5853 if (spec->cur_out_type == HEADPHONE_OUT)
5854 changed = zxr_headphone_gain_set(codec, *valp);
5855 else
5856 changed = 0;
5857
5858 goto exit;
5859 }
5860
5861 exit:
5862 snd_hda_power_down(codec);
5863 return changed;
5864 }
5865
5866 /*
5867 * Volume related
5868 */
5869 /*
5870 * Sets the internal DSP decibel level to match the DAC for output, and the
5871 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5872 * all alternative codecs set DSP playback volume.
5873 */
ca0132_alt_dsp_volume_put(struct hda_codec * codec,hda_nid_t nid)5874 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5875 {
5876 struct ca0132_spec *spec = codec->spec;
5877 unsigned int dsp_dir;
5878 unsigned int lookup_val;
5879
5880 if (nid == VNID_SPK)
5881 dsp_dir = DSP_VOL_OUT;
5882 else
5883 dsp_dir = DSP_VOL_IN;
5884
5885 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5886
5887 dspio_set_uint_param(codec,
5888 ca0132_alt_vol_ctls[dsp_dir].mid,
5889 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5890 float_vol_db_lookup[lookup_val]);
5891
5892 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5893
5894 dspio_set_uint_param(codec,
5895 ca0132_alt_vol_ctls[dsp_dir].mid,
5896 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5897 float_vol_db_lookup[lookup_val]);
5898
5899 dspio_set_uint_param(codec,
5900 ca0132_alt_vol_ctls[dsp_dir].mid,
5901 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5902 }
5903
ca0132_volume_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5904 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5905 struct snd_ctl_elem_info *uinfo)
5906 {
5907 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5908 struct ca0132_spec *spec = codec->spec;
5909 hda_nid_t nid = get_amp_nid(kcontrol);
5910 int ch = get_amp_channels(kcontrol);
5911 int dir = get_amp_direction(kcontrol);
5912 unsigned long pval;
5913 int err;
5914
5915 switch (nid) {
5916 case VNID_SPK:
5917 /* follow shared_out info */
5918 nid = spec->shared_out_nid;
5919 mutex_lock(&codec->control_mutex);
5920 pval = kcontrol->private_value;
5921 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5922 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5923 kcontrol->private_value = pval;
5924 mutex_unlock(&codec->control_mutex);
5925 break;
5926 case VNID_MIC:
5927 /* follow shared_mic info */
5928 nid = spec->shared_mic_nid;
5929 mutex_lock(&codec->control_mutex);
5930 pval = kcontrol->private_value;
5931 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5932 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5933 kcontrol->private_value = pval;
5934 mutex_unlock(&codec->control_mutex);
5935 break;
5936 default:
5937 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5938 }
5939 return err;
5940 }
5941
ca0132_volume_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5942 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
5943 struct snd_ctl_elem_value *ucontrol)
5944 {
5945 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5946 struct ca0132_spec *spec = codec->spec;
5947 hda_nid_t nid = get_amp_nid(kcontrol);
5948 int ch = get_amp_channels(kcontrol);
5949 long *valp = ucontrol->value.integer.value;
5950
5951 /* store the left and right volume */
5952 if (ch & 1) {
5953 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5954 valp++;
5955 }
5956 if (ch & 2) {
5957 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5958 valp++;
5959 }
5960 return 0;
5961 }
5962
ca0132_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5963 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
5964 struct snd_ctl_elem_value *ucontrol)
5965 {
5966 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5967 struct ca0132_spec *spec = codec->spec;
5968 hda_nid_t nid = get_amp_nid(kcontrol);
5969 int ch = get_amp_channels(kcontrol);
5970 long *valp = ucontrol->value.integer.value;
5971 hda_nid_t shared_nid = 0;
5972 bool effective;
5973 int changed = 1;
5974
5975 /* store the left and right volume */
5976 if (ch & 1) {
5977 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5978 valp++;
5979 }
5980 if (ch & 2) {
5981 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5982 valp++;
5983 }
5984
5985 /* if effective conditions, then update hw immediately. */
5986 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5987 if (effective) {
5988 int dir = get_amp_direction(kcontrol);
5989 unsigned long pval;
5990
5991 snd_hda_power_up(codec);
5992 mutex_lock(&codec->control_mutex);
5993 pval = kcontrol->private_value;
5994 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5995 0, dir);
5996 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5997 kcontrol->private_value = pval;
5998 mutex_unlock(&codec->control_mutex);
5999 snd_hda_power_down(codec);
6000 }
6001
6002 return changed;
6003 }
6004
6005 /*
6006 * This function is the same as the one above, because using an if statement
6007 * inside of the above volume control for the DSP volume would cause too much
6008 * lag. This is a lot more smooth.
6009 */
ca0132_alt_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6010 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
6011 struct snd_ctl_elem_value *ucontrol)
6012 {
6013 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6014 struct ca0132_spec *spec = codec->spec;
6015 hda_nid_t nid = get_amp_nid(kcontrol);
6016 int ch = get_amp_channels(kcontrol);
6017 long *valp = ucontrol->value.integer.value;
6018 hda_nid_t vnid = 0;
6019 int changed;
6020
6021 switch (nid) {
6022 case 0x02:
6023 vnid = VNID_SPK;
6024 break;
6025 case 0x07:
6026 vnid = VNID_MIC;
6027 break;
6028 }
6029
6030 /* store the left and right volume */
6031 if (ch & 1) {
6032 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6033 valp++;
6034 }
6035 if (ch & 2) {
6036 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6037 valp++;
6038 }
6039
6040 snd_hda_power_up(codec);
6041 ca0132_alt_dsp_volume_put(codec, vnid);
6042 mutex_lock(&codec->control_mutex);
6043 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6044 mutex_unlock(&codec->control_mutex);
6045 snd_hda_power_down(codec);
6046
6047 return changed;
6048 }
6049
ca0132_volume_tlv(struct snd_kcontrol * kcontrol,int op_flag,unsigned int size,unsigned int __user * tlv)6050 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
6051 unsigned int size, unsigned int __user *tlv)
6052 {
6053 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6054 struct ca0132_spec *spec = codec->spec;
6055 hda_nid_t nid = get_amp_nid(kcontrol);
6056 int ch = get_amp_channels(kcontrol);
6057 int dir = get_amp_direction(kcontrol);
6058 unsigned long pval;
6059 int err;
6060
6061 switch (nid) {
6062 case VNID_SPK:
6063 /* follow shared_out tlv */
6064 nid = spec->shared_out_nid;
6065 mutex_lock(&codec->control_mutex);
6066 pval = kcontrol->private_value;
6067 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6068 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6069 kcontrol->private_value = pval;
6070 mutex_unlock(&codec->control_mutex);
6071 break;
6072 case VNID_MIC:
6073 /* follow shared_mic tlv */
6074 nid = spec->shared_mic_nid;
6075 mutex_lock(&codec->control_mutex);
6076 pval = kcontrol->private_value;
6077 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6078 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6079 kcontrol->private_value = pval;
6080 mutex_unlock(&codec->control_mutex);
6081 break;
6082 default:
6083 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6084 }
6085 return err;
6086 }
6087
6088 /* Add volume slider control for effect level */
ca0132_alt_add_effect_slider(struct hda_codec * codec,hda_nid_t nid,const char * pfx,int dir)6089 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6090 const char *pfx, int dir)
6091 {
6092 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6093 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6094 struct snd_kcontrol_new knew =
6095 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6096
6097 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
6098
6099 knew.tlv.c = NULL;
6100
6101 switch (nid) {
6102 case XBASS_XOVER:
6103 knew.info = ca0132_alt_xbass_xover_slider_info;
6104 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6105 knew.put = ca0132_alt_xbass_xover_slider_put;
6106 break;
6107 default:
6108 knew.info = ca0132_alt_effect_slider_info;
6109 knew.get = ca0132_alt_slider_ctl_get;
6110 knew.put = ca0132_alt_effect_slider_put;
6111 knew.private_value =
6112 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6113 break;
6114 }
6115
6116 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6117 }
6118
6119 /*
6120 * Added FX: prefix for the alternative codecs, because otherwise the surround
6121 * effect would conflict with the Surround sound volume control. Also seems more
6122 * clear as to what the switches do. Left alone for others.
6123 */
add_fx_switch(struct hda_codec * codec,hda_nid_t nid,const char * pfx,int dir)6124 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6125 const char *pfx, int dir)
6126 {
6127 struct ca0132_spec *spec = codec->spec;
6128 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6129 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6130 struct snd_kcontrol_new knew =
6131 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
6132 /* If using alt_controls, add FX: prefix. But, don't add FX:
6133 * prefix to OutFX or InFX enable controls.
6134 */
6135 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
6136 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
6137 else
6138 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6139
6140 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6141 }
6142
add_voicefx(struct hda_codec * codec)6143 static int add_voicefx(struct hda_codec *codec)
6144 {
6145 struct snd_kcontrol_new knew =
6146 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6147 VOICEFX, 1, 0, HDA_INPUT);
6148 knew.info = ca0132_voicefx_info;
6149 knew.get = ca0132_voicefx_get;
6150 knew.put = ca0132_voicefx_put;
6151 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
6152 }
6153
6154 /* Create the EQ Preset control */
add_ca0132_alt_eq_presets(struct hda_codec * codec)6155 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6156 {
6157 struct snd_kcontrol_new knew =
6158 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6159 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6160 knew.info = ca0132_alt_eq_preset_info;
6161 knew.get = ca0132_alt_eq_preset_get;
6162 knew.put = ca0132_alt_eq_preset_put;
6163 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6164 snd_ctl_new1(&knew, codec));
6165 }
6166
6167 /*
6168 * Add enumerated control for the three different settings of the smart volume
6169 * output effect. Normal just uses the slider value, and loud and night are
6170 * their own things that ignore that value.
6171 */
ca0132_alt_add_svm_enum(struct hda_codec * codec)6172 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6173 {
6174 struct snd_kcontrol_new knew =
6175 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6176 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6177 knew.info = ca0132_alt_svm_setting_info;
6178 knew.get = ca0132_alt_svm_setting_get;
6179 knew.put = ca0132_alt_svm_setting_put;
6180 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6181 snd_ctl_new1(&knew, codec));
6182
6183 }
6184
6185 /*
6186 * Create an Output Select enumerated control for codecs with surround
6187 * out capabilities.
6188 */
ca0132_alt_add_output_enum(struct hda_codec * codec)6189 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6190 {
6191 struct snd_kcontrol_new knew =
6192 HDA_CODEC_MUTE_MONO("Output Select",
6193 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6194 knew.info = ca0132_alt_output_select_get_info;
6195 knew.get = ca0132_alt_output_select_get;
6196 knew.put = ca0132_alt_output_select_put;
6197 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6198 snd_ctl_new1(&knew, codec));
6199 }
6200
6201 /*
6202 * Create an Input Source enumerated control for the alternate ca0132 codecs
6203 * because the front microphone has no auto-detect, and Line-in has to be set
6204 * somehow.
6205 */
ca0132_alt_add_input_enum(struct hda_codec * codec)6206 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6207 {
6208 struct snd_kcontrol_new knew =
6209 HDA_CODEC_MUTE_MONO("Input Source",
6210 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6211 knew.info = ca0132_alt_input_source_info;
6212 knew.get = ca0132_alt_input_source_get;
6213 knew.put = ca0132_alt_input_source_put;
6214 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6215 snd_ctl_new1(&knew, codec));
6216 }
6217
6218 /*
6219 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6220 * more control than the original mic boost, which is either full 30dB or off.
6221 */
ca0132_alt_add_mic_boost_enum(struct hda_codec * codec)6222 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6223 {
6224 struct snd_kcontrol_new knew =
6225 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6226 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6227 knew.info = ca0132_alt_mic_boost_info;
6228 knew.get = ca0132_alt_mic_boost_get;
6229 knew.put = ca0132_alt_mic_boost_put;
6230 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6231 snd_ctl_new1(&knew, codec));
6232
6233 }
6234
6235 /*
6236 * Add headphone gain enumerated control for the AE-5. This switches between
6237 * three modes, low, medium, and high. When non-headphone outputs are selected,
6238 * it is automatically set to high. This is the same behavior as Windows.
6239 */
ae5_add_headphone_gain_enum(struct hda_codec * codec)6240 static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6241 {
6242 struct snd_kcontrol_new knew =
6243 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6244 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6245 knew.info = ae5_headphone_gain_info;
6246 knew.get = ae5_headphone_gain_get;
6247 knew.put = ae5_headphone_gain_put;
6248 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6249 snd_ctl_new1(&knew, codec));
6250 }
6251
6252 /*
6253 * Add sound filter enumerated control for the AE-5. This adds three different
6254 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6255 * read into it, it changes the DAC's interpolation filter.
6256 */
ae5_add_sound_filter_enum(struct hda_codec * codec)6257 static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6258 {
6259 struct snd_kcontrol_new knew =
6260 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6261 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6262 knew.info = ae5_sound_filter_info;
6263 knew.get = ae5_sound_filter_get;
6264 knew.put = ae5_sound_filter_put;
6265 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6266 snd_ctl_new1(&knew, codec));
6267 }
6268
zxr_add_headphone_gain_switch(struct hda_codec * codec)6269 static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6270 {
6271 struct snd_kcontrol_new knew =
6272 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6273 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6274
6275 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6276 snd_ctl_new1(&knew, codec));
6277 }
6278
6279 /*
6280 * Need to create slave controls for the alternate codecs that have surround
6281 * capabilities.
6282 */
6283 static const char * const ca0132_alt_slave_pfxs[] = {
6284 "Front", "Surround", "Center", "LFE", NULL,
6285 };
6286
6287 /*
6288 * Also need special channel map, because the default one is incorrect.
6289 * I think this has to do with the pin for rear surround being 0x11,
6290 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6291 */
6292 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
6293 { .channels = 2,
6294 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6295 { .channels = 4,
6296 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6297 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6298 { .channels = 6,
6299 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6300 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6301 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6302 { }
6303 };
6304
6305 /* Add the correct chmap for streams with 6 channels. */
ca0132_alt_add_chmap_ctls(struct hda_codec * codec)6306 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6307 {
6308 int err = 0;
6309 struct hda_pcm *pcm;
6310
6311 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6312 struct hda_pcm_stream *hinfo =
6313 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6314 struct snd_pcm_chmap *chmap;
6315 const struct snd_pcm_chmap_elem *elem;
6316
6317 elem = ca0132_alt_chmaps;
6318 if (hinfo->channels_max == 6) {
6319 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6320 SNDRV_PCM_STREAM_PLAYBACK,
6321 elem, hinfo->channels_max, 0, &chmap);
6322 if (err < 0)
6323 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6324 }
6325 }
6326 }
6327
6328 /*
6329 * When changing Node IDs for Mixer Controls below, make sure to update
6330 * Node IDs in ca0132_config() as well.
6331 */
6332 static const struct snd_kcontrol_new ca0132_mixer[] = {
6333 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6334 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6335 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6336 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6337 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6338 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6339 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6340 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6341 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6342 0x12, 1, HDA_INPUT),
6343 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6344 VNID_HP_SEL, 1, HDA_OUTPUT),
6345 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6346 VNID_AMIC1_SEL, 1, HDA_INPUT),
6347 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6348 VNID_HP_ASEL, 1, HDA_OUTPUT),
6349 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6350 VNID_AMIC1_ASEL, 1, HDA_INPUT),
6351 { } /* end */
6352 };
6353
6354 /*
6355 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6356 * surround controls. Also sets both the Front Playback and Capture Volume
6357 * controls to alt so they set the DSP's decibel level.
6358 */
6359 static const struct snd_kcontrol_new desktop_mixer[] = {
6360 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6361 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6362 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6363 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6364 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6365 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6366 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6367 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6368 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6369 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6370 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6371 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6372 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6373 VNID_HP_ASEL, 1, HDA_OUTPUT),
6374 { } /* end */
6375 };
6376
6377 /*
6378 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
6379 * because it doesn't set decibel levels for the DSP for capture.
6380 */
6381 static const struct snd_kcontrol_new r3di_mixer[] = {
6382 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6383 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6384 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6385 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6386 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6387 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6388 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6389 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6390 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6391 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6392 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6393 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6394 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6395 VNID_HP_ASEL, 1, HDA_OUTPUT),
6396 { } /* end */
6397 };
6398
ca0132_build_controls(struct hda_codec * codec)6399 static int ca0132_build_controls(struct hda_codec *codec)
6400 {
6401 struct ca0132_spec *spec = codec->spec;
6402 int i, num_fx, num_sliders;
6403 int err = 0;
6404
6405 /* Add Mixer controls */
6406 for (i = 0; i < spec->num_mixers; i++) {
6407 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6408 if (err < 0)
6409 return err;
6410 }
6411 /* Setup vmaster with surround slaves for desktop ca0132 devices */
6412 if (ca0132_use_alt_functions(spec)) {
6413 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6414 spec->tlv);
6415 snd_hda_add_vmaster(codec, "Master Playback Volume",
6416 spec->tlv, ca0132_alt_slave_pfxs,
6417 "Playback Volume");
6418 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
6419 NULL, ca0132_alt_slave_pfxs,
6420 "Playback Switch",
6421 true, &spec->vmaster_mute.sw_kctl);
6422 if (err < 0)
6423 return err;
6424 }
6425
6426 /* Add in and out effects controls.
6427 * VoiceFX, PE and CrystalVoice are added separately.
6428 */
6429 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6430 for (i = 0; i < num_fx; i++) {
6431 /* Desktop cards break if Echo Cancellation is used. */
6432 if (ca0132_use_pci_mmio(spec)) {
6433 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
6434 OUT_EFFECTS_COUNT))
6435 continue;
6436 }
6437
6438 err = add_fx_switch(codec, ca0132_effects[i].nid,
6439 ca0132_effects[i].name,
6440 ca0132_effects[i].direct);
6441 if (err < 0)
6442 return err;
6443 }
6444 /*
6445 * If codec has use_alt_controls set to true, add effect level sliders,
6446 * EQ presets, and Smart Volume presets. Also, change names to add FX
6447 * prefix, and change PlayEnhancement and CrystalVoice to match.
6448 */
6449 if (ca0132_use_alt_controls(spec)) {
6450 err = ca0132_alt_add_svm_enum(codec);
6451 if (err < 0)
6452 return err;
6453
6454 err = add_ca0132_alt_eq_presets(codec);
6455 if (err < 0)
6456 return err;
6457
6458 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6459 "Enable OutFX", 0);
6460 if (err < 0)
6461 return err;
6462
6463 err = add_fx_switch(codec, CRYSTAL_VOICE,
6464 "Enable InFX", 1);
6465 if (err < 0)
6466 return err;
6467
6468 num_sliders = OUT_EFFECTS_COUNT - 1;
6469 for (i = 0; i < num_sliders; i++) {
6470 err = ca0132_alt_add_effect_slider(codec,
6471 ca0132_effects[i].nid,
6472 ca0132_effects[i].name,
6473 ca0132_effects[i].direct);
6474 if (err < 0)
6475 return err;
6476 }
6477
6478 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
6479 "X-Bass Crossover", EFX_DIR_OUT);
6480
6481 if (err < 0)
6482 return err;
6483 } else {
6484 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6485 "PlayEnhancement", 0);
6486 if (err < 0)
6487 return err;
6488
6489 err = add_fx_switch(codec, CRYSTAL_VOICE,
6490 "CrystalVoice", 1);
6491 if (err < 0)
6492 return err;
6493 }
6494 err = add_voicefx(codec);
6495 if (err < 0)
6496 return err;
6497
6498 /*
6499 * If the codec uses alt_functions, you need the enumerated controls
6500 * to select the new outputs and inputs, plus add the new mic boost
6501 * setting control.
6502 */
6503 if (ca0132_use_alt_functions(spec)) {
6504 err = ca0132_alt_add_output_enum(codec);
6505 if (err < 0)
6506 return err;
6507 err = ca0132_alt_add_mic_boost_enum(codec);
6508 if (err < 0)
6509 return err;
6510 /*
6511 * ZxR only has microphone input, there is no front panel
6512 * header on the card, and aux-in is handled by the DBPro board.
6513 */
6514 if (ca0132_quirk(spec) != QUIRK_ZXR) {
6515 err = ca0132_alt_add_input_enum(codec);
6516 if (err < 0)
6517 return err;
6518 }
6519 }
6520
6521 if (ca0132_quirk(spec) == QUIRK_AE5) {
6522 err = ae5_add_headphone_gain_enum(codec);
6523 if (err < 0)
6524 return err;
6525 err = ae5_add_sound_filter_enum(codec);
6526 if (err < 0)
6527 return err;
6528 }
6529
6530 if (ca0132_quirk(spec) == QUIRK_ZXR) {
6531 err = zxr_add_headphone_gain_switch(codec);
6532 if (err < 0)
6533 return err;
6534 }
6535 #ifdef ENABLE_TUNING_CONTROLS
6536 add_tuning_ctls(codec);
6537 #endif
6538
6539 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
6540 if (err < 0)
6541 return err;
6542
6543 if (spec->dig_out) {
6544 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6545 spec->dig_out);
6546 if (err < 0)
6547 return err;
6548 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
6549 if (err < 0)
6550 return err;
6551 /* spec->multiout.share_spdif = 1; */
6552 }
6553
6554 if (spec->dig_in) {
6555 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6556 if (err < 0)
6557 return err;
6558 }
6559
6560 if (ca0132_use_alt_functions(spec))
6561 ca0132_alt_add_chmap_ctls(codec);
6562
6563 return 0;
6564 }
6565
dbpro_build_controls(struct hda_codec * codec)6566 static int dbpro_build_controls(struct hda_codec *codec)
6567 {
6568 struct ca0132_spec *spec = codec->spec;
6569 int err = 0;
6570
6571 if (spec->dig_out) {
6572 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6573 spec->dig_out);
6574 if (err < 0)
6575 return err;
6576 }
6577
6578 if (spec->dig_in) {
6579 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6580 if (err < 0)
6581 return err;
6582 }
6583
6584 return 0;
6585 }
6586
6587 /*
6588 * PCM
6589 */
6590 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
6591 .substreams = 1,
6592 .channels_min = 2,
6593 .channels_max = 6,
6594 .ops = {
6595 .prepare = ca0132_playback_pcm_prepare,
6596 .cleanup = ca0132_playback_pcm_cleanup,
6597 .get_delay = ca0132_playback_pcm_delay,
6598 },
6599 };
6600
6601 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
6602 .substreams = 1,
6603 .channels_min = 2,
6604 .channels_max = 2,
6605 .ops = {
6606 .prepare = ca0132_capture_pcm_prepare,
6607 .cleanup = ca0132_capture_pcm_cleanup,
6608 .get_delay = ca0132_capture_pcm_delay,
6609 },
6610 };
6611
6612 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
6613 .substreams = 1,
6614 .channels_min = 2,
6615 .channels_max = 2,
6616 .ops = {
6617 .open = ca0132_dig_playback_pcm_open,
6618 .close = ca0132_dig_playback_pcm_close,
6619 .prepare = ca0132_dig_playback_pcm_prepare,
6620 .cleanup = ca0132_dig_playback_pcm_cleanup
6621 },
6622 };
6623
6624 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
6625 .substreams = 1,
6626 .channels_min = 2,
6627 .channels_max = 2,
6628 };
6629
ca0132_build_pcms(struct hda_codec * codec)6630 static int ca0132_build_pcms(struct hda_codec *codec)
6631 {
6632 struct ca0132_spec *spec = codec->spec;
6633 struct hda_pcm *info;
6634
6635 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6636 if (!info)
6637 return -ENOMEM;
6638 if (ca0132_use_alt_functions(spec)) {
6639 info->own_chmap = true;
6640 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6641 = ca0132_alt_chmaps;
6642 }
6643 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6644 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6645 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6646 spec->multiout.max_channels;
6647 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6648 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6649 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6650
6651 /* With the DSP enabled, desktops don't use this ADC. */
6652 if (!ca0132_use_alt_functions(spec)) {
6653 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6654 if (!info)
6655 return -ENOMEM;
6656 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6657 ca0132_pcm_analog_capture;
6658 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6659 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6660 }
6661
6662 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6663 if (!info)
6664 return -ENOMEM;
6665 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6666 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6667 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
6668
6669 if (!spec->dig_out && !spec->dig_in)
6670 return 0;
6671
6672 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6673 if (!info)
6674 return -ENOMEM;
6675 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6676 if (spec->dig_out) {
6677 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6678 ca0132_pcm_digital_playback;
6679 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6680 }
6681 if (spec->dig_in) {
6682 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6683 ca0132_pcm_digital_capture;
6684 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6685 }
6686
6687 return 0;
6688 }
6689
dbpro_build_pcms(struct hda_codec * codec)6690 static int dbpro_build_pcms(struct hda_codec *codec)
6691 {
6692 struct ca0132_spec *spec = codec->spec;
6693 struct hda_pcm *info;
6694
6695 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
6696 if (!info)
6697 return -ENOMEM;
6698 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6699 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6700 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6701
6702
6703 if (!spec->dig_out && !spec->dig_in)
6704 return 0;
6705
6706 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6707 if (!info)
6708 return -ENOMEM;
6709 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6710 if (spec->dig_out) {
6711 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6712 ca0132_pcm_digital_playback;
6713 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6714 }
6715 if (spec->dig_in) {
6716 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6717 ca0132_pcm_digital_capture;
6718 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6719 }
6720
6721 return 0;
6722 }
6723
init_output(struct hda_codec * codec,hda_nid_t pin,hda_nid_t dac)6724 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6725 {
6726 if (pin) {
6727 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
6728 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6729 snd_hda_codec_write(codec, pin, 0,
6730 AC_VERB_SET_AMP_GAIN_MUTE,
6731 AMP_OUT_UNMUTE);
6732 }
6733 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6734 snd_hda_codec_write(codec, dac, 0,
6735 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6736 }
6737
init_input(struct hda_codec * codec,hda_nid_t pin,hda_nid_t adc)6738 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6739 {
6740 if (pin) {
6741 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
6742 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6743 snd_hda_codec_write(codec, pin, 0,
6744 AC_VERB_SET_AMP_GAIN_MUTE,
6745 AMP_IN_UNMUTE(0));
6746 }
6747 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6748 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6749 AMP_IN_UNMUTE(0));
6750
6751 /* init to 0 dB and unmute. */
6752 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6753 HDA_AMP_VOLMASK, 0x5a);
6754 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6755 HDA_AMP_MUTE, 0);
6756 }
6757 }
6758
refresh_amp_caps(struct hda_codec * codec,hda_nid_t nid,int dir)6759 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6760 {
6761 unsigned int caps;
6762
6763 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6764 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6765 snd_hda_override_amp_caps(codec, nid, dir, caps);
6766 }
6767
6768 /*
6769 * Switch between Digital built-in mic and analog mic.
6770 */
ca0132_set_dmic(struct hda_codec * codec,int enable)6771 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6772 {
6773 struct ca0132_spec *spec = codec->spec;
6774 unsigned int tmp;
6775 u8 val;
6776 unsigned int oldval;
6777
6778 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
6779
6780 oldval = stop_mic1(codec);
6781 ca0132_set_vipsource(codec, 0);
6782 if (enable) {
6783 /* set DMic input as 2-ch */
6784 tmp = FLOAT_TWO;
6785 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6786
6787 val = spec->dmic_ctl;
6788 val |= 0x80;
6789 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6790 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6791
6792 if (!(spec->dmic_ctl & 0x20))
6793 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6794 } else {
6795 /* set AMic input as mono */
6796 tmp = FLOAT_ONE;
6797 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6798
6799 val = spec->dmic_ctl;
6800 /* clear bit7 and bit5 to disable dmic */
6801 val &= 0x5f;
6802 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6803 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6804
6805 if (!(spec->dmic_ctl & 0x20))
6806 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6807 }
6808 ca0132_set_vipsource(codec, 1);
6809 resume_mic1(codec, oldval);
6810 }
6811
6812 /*
6813 * Initialization for Digital Mic.
6814 */
ca0132_init_dmic(struct hda_codec * codec)6815 static void ca0132_init_dmic(struct hda_codec *codec)
6816 {
6817 struct ca0132_spec *spec = codec->spec;
6818 u8 val;
6819
6820 /* Setup Digital Mic here, but don't enable.
6821 * Enable based on jack detect.
6822 */
6823
6824 /* MCLK uses MPIO1, set to enable.
6825 * Bit 2-0: MPIO select
6826 * Bit 3: set to disable
6827 * Bit 7-4: reserved
6828 */
6829 val = 0x01;
6830 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6831 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6832
6833 /* Data1 uses MPIO3. Data2 not use
6834 * Bit 2-0: Data1 MPIO select
6835 * Bit 3: set disable Data1
6836 * Bit 6-4: Data2 MPIO select
6837 * Bit 7: set disable Data2
6838 */
6839 val = 0x83;
6840 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6841 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6842
6843 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6844 * Bit 3-0: Channel mask
6845 * Bit 4: set for 48KHz, clear for 32KHz
6846 * Bit 5: mode
6847 * Bit 6: set to select Data2, clear for Data1
6848 * Bit 7: set to enable DMic, clear for AMic
6849 */
6850 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
6851 val = 0x33;
6852 else
6853 val = 0x23;
6854 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6855 spec->dmic_ctl = val;
6856 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6857 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6858 }
6859
6860 /*
6861 * Initialization for Analog Mic 2
6862 */
ca0132_init_analog_mic2(struct hda_codec * codec)6863 static void ca0132_init_analog_mic2(struct hda_codec *codec)
6864 {
6865 struct ca0132_spec *spec = codec->spec;
6866
6867 mutex_lock(&spec->chipio_mutex);
6868 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6869 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6870 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6871 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6872 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6873 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6874 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6875 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6876 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6877 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6878 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6879 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6880 mutex_unlock(&spec->chipio_mutex);
6881 }
6882
ca0132_refresh_widget_caps(struct hda_codec * codec)6883 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6884 {
6885 struct ca0132_spec *spec = codec->spec;
6886 int i;
6887
6888 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
6889 snd_hda_codec_update_widgets(codec);
6890
6891 for (i = 0; i < spec->multiout.num_dacs; i++)
6892 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6893
6894 for (i = 0; i < spec->num_outputs; i++)
6895 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6896
6897 for (i = 0; i < spec->num_inputs; i++) {
6898 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6899 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6900 }
6901 }
6902
6903 /*
6904 * Creates a dummy stream to bind the output to. This seems to have to be done
6905 * after changing the main outputs source and destination streams.
6906 */
ca0132_alt_create_dummy_stream(struct hda_codec * codec)6907 static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
6908 {
6909 struct ca0132_spec *spec = codec->spec;
6910 unsigned int stream_format;
6911
6912 stream_format = snd_hdac_calc_stream_format(48000, 2,
6913 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
6914
6915 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6916 0, stream_format);
6917
6918 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6919 }
6920
6921 /*
6922 * Initialize mic for non-chromebook ca0132 implementations.
6923 */
ca0132_alt_init_analog_mics(struct hda_codec * codec)6924 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
6925 {
6926 struct ca0132_spec *spec = codec->spec;
6927 unsigned int tmp;
6928
6929 /* Mic 1 Setup */
6930 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6931 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6932 if (ca0132_quirk(spec) == QUIRK_R3DI) {
6933 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6934 tmp = FLOAT_ONE;
6935 } else
6936 tmp = FLOAT_THREE;
6937 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6938
6939 /* Mic 2 setup (not present on desktop cards) */
6940 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6941 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6942 if (ca0132_quirk(spec) == QUIRK_R3DI)
6943 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6944 tmp = FLOAT_ZERO;
6945 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6946 }
6947
6948 /*
6949 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6950 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6951 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6952 * having an updated DAC, which changes the destination to that DAC.
6953 */
sbz_connect_streams(struct hda_codec * codec)6954 static void sbz_connect_streams(struct hda_codec *codec)
6955 {
6956 struct ca0132_spec *spec = codec->spec;
6957
6958 mutex_lock(&spec->chipio_mutex);
6959
6960 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6961
6962 chipio_set_stream_channels(codec, 0x0C, 6);
6963 chipio_set_stream_control(codec, 0x0C, 1);
6964
6965 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6966 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6967
6968 /* Setup stream 0x14 with it's source and destination points */
6969 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6970 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6971 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6972 chipio_set_stream_channels(codec, 0x14, 2);
6973 chipio_set_stream_control(codec, 0x14, 1);
6974
6975 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6976
6977 mutex_unlock(&spec->chipio_mutex);
6978 }
6979
6980 /*
6981 * Write data through ChipIO to setup proper stream destinations.
6982 * Not sure how it exactly works, but it seems to direct data
6983 * to different destinations. Example is f8 to c0, e0 to c0.
6984 * All I know is, if you don't set these, you get no sound.
6985 */
sbz_chipio_startup_data(struct hda_codec * codec)6986 static void sbz_chipio_startup_data(struct hda_codec *codec)
6987 {
6988 struct ca0132_spec *spec = codec->spec;
6989
6990 mutex_lock(&spec->chipio_mutex);
6991 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6992
6993 /* These control audio output */
6994 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6995 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6996 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6997 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6998 /* Signal to update I think */
6999 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7000
7001 chipio_set_stream_channels(codec, 0x0C, 6);
7002 chipio_set_stream_control(codec, 0x0C, 1);
7003 /* No clue what these control */
7004 if (ca0132_quirk(spec) == QUIRK_SBZ) {
7005 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
7006 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
7007 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
7008 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
7009 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
7010 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
7011 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
7012 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
7013 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
7014 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
7015 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
7016 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
7017 } else if (ca0132_quirk(spec) == QUIRK_ZXR) {
7018 chipio_write_no_mutex(codec, 0x190038, 0x000140c2);
7019 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3);
7020 chipio_write_no_mutex(codec, 0x190040, 0x000150c4);
7021 chipio_write_no_mutex(codec, 0x190044, 0x000151c5);
7022 chipio_write_no_mutex(codec, 0x190050, 0x000142c8);
7023 chipio_write_no_mutex(codec, 0x190054, 0x000143c9);
7024 chipio_write_no_mutex(codec, 0x190058, 0x000152ca);
7025 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb);
7026 }
7027 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7028
7029 codec_dbg(codec, "Startup Data exited, mutex released.\n");
7030 mutex_unlock(&spec->chipio_mutex);
7031 }
7032
7033 /*
7034 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
7035 * done after the DSP is loaded.
7036 */
ca0132_alt_dsp_scp_startup(struct hda_codec * codec)7037 static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
7038 {
7039 struct ca0132_spec *spec = codec->spec;
7040 unsigned int tmp, i;
7041
7042 /*
7043 * Gotta run these twice, or else mic works inconsistently. Not clear
7044 * why this is, but multiple tests have confirmed it.
7045 */
7046 for (i = 0; i < 2; i++) {
7047 switch (ca0132_quirk(spec)) {
7048 case QUIRK_SBZ:
7049 case QUIRK_AE5:
7050 tmp = 0x00000003;
7051 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7052 tmp = 0x00000000;
7053 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7054 tmp = 0x00000001;
7055 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7056 tmp = 0x00000004;
7057 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7058 tmp = 0x00000005;
7059 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7060 tmp = 0x00000000;
7061 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7062 break;
7063 case QUIRK_R3D:
7064 case QUIRK_R3DI:
7065 tmp = 0x00000000;
7066 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7067 tmp = 0x00000001;
7068 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7069 tmp = 0x00000004;
7070 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7071 tmp = 0x00000005;
7072 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7073 tmp = 0x00000000;
7074 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7075 break;
7076 default:
7077 break;
7078 }
7079 msleep(100);
7080 }
7081 }
7082
ca0132_alt_dsp_initial_mic_setup(struct hda_codec * codec)7083 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
7084 {
7085 struct ca0132_spec *spec = codec->spec;
7086 unsigned int tmp;
7087
7088 chipio_set_stream_control(codec, 0x03, 0);
7089 chipio_set_stream_control(codec, 0x04, 0);
7090
7091 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7092 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7093
7094 tmp = FLOAT_THREE;
7095 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7096
7097 chipio_set_stream_control(codec, 0x03, 1);
7098 chipio_set_stream_control(codec, 0x04, 1);
7099
7100 switch (ca0132_quirk(spec)) {
7101 case QUIRK_SBZ:
7102 chipio_write(codec, 0x18b098, 0x0000000c);
7103 chipio_write(codec, 0x18b09C, 0x0000000c);
7104 break;
7105 case QUIRK_AE5:
7106 chipio_write(codec, 0x18b098, 0x0000000c);
7107 chipio_write(codec, 0x18b09c, 0x0000004c);
7108 break;
7109 default:
7110 break;
7111 }
7112 }
7113
ae5_post_dsp_register_set(struct hda_codec * codec)7114 static void ae5_post_dsp_register_set(struct hda_codec *codec)
7115 {
7116 struct ca0132_spec *spec = codec->spec;
7117
7118 chipio_8051_write_direct(codec, 0x93, 0x10);
7119 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7120 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
7121 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7122 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
7123
7124 writeb(0xff, spec->mem_base + 0x304);
7125 writeb(0xff, spec->mem_base + 0x304);
7126 writeb(0xff, spec->mem_base + 0x304);
7127 writeb(0xff, spec->mem_base + 0x304);
7128 writeb(0x00, spec->mem_base + 0x100);
7129 writeb(0xff, spec->mem_base + 0x304);
7130 writeb(0x00, spec->mem_base + 0x100);
7131 writeb(0xff, spec->mem_base + 0x304);
7132 writeb(0x00, spec->mem_base + 0x100);
7133 writeb(0xff, spec->mem_base + 0x304);
7134 writeb(0x00, spec->mem_base + 0x100);
7135 writeb(0xff, spec->mem_base + 0x304);
7136
7137 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7138 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7139 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7140 }
7141
ae5_post_dsp_param_setup(struct hda_codec * codec)7142 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7143 {
7144 /*
7145 * Param3 in the 8051's memory is represented by the ascii string 'mch'
7146 * which seems to be 'multichannel'. This is also mentioned in the
7147 * AE-5's registry values in Windows.
7148 */
7149 chipio_set_control_param(codec, 3, 0);
7150 /*
7151 * I believe ASI is 'audio serial interface' and that it's used to
7152 * change colors on the external LED strip connected to the AE-5.
7153 */
7154 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7155
7156 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7157 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7158
7159 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7160 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
7161 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7162 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
7163 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7164 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
7165 }
7166
ae5_post_dsp_pll_setup(struct hda_codec * codec)7167 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7168 {
7169 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7170 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
7171 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7172 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
7173
7174 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7175 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
7176 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7177 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
7178
7179 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7180 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
7181 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7182 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
7183
7184 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7185 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7186 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7187 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7188
7189 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7190 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
7191 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7192 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
7193 }
7194
ae5_post_dsp_stream_setup(struct hda_codec * codec)7195 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7196 {
7197 struct ca0132_spec *spec = codec->spec;
7198
7199 mutex_lock(&spec->chipio_mutex);
7200
7201 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7202
7203 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7204
7205 chipio_set_stream_channels(codec, 0x0C, 6);
7206 chipio_set_stream_control(codec, 0x0C, 1);
7207
7208 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7209
7210 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7211 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7212 chipio_set_stream_channels(codec, 0x18, 6);
7213 chipio_set_stream_control(codec, 0x18, 1);
7214
7215 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7216
7217 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7218 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7219 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7220 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7221
7222 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7223
7224 mutex_unlock(&spec->chipio_mutex);
7225 }
7226
ae5_post_dsp_startup_data(struct hda_codec * codec)7227 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
7228 {
7229 struct ca0132_spec *spec = codec->spec;
7230
7231 mutex_lock(&spec->chipio_mutex);
7232
7233 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7234 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7235 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7236 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7237
7238 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7239 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7240 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
7241 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
7242 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
7243 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7244 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7245 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7246 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7247 ca0113_mmio_gpio_set(codec, 0, true);
7248 ca0113_mmio_gpio_set(codec, 1, true);
7249 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7250
7251 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7252
7253 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7254 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7255
7256 mutex_unlock(&spec->chipio_mutex);
7257 }
7258
7259 /*
7260 * Setup default parameters for DSP
7261 */
ca0132_setup_defaults(struct hda_codec * codec)7262 static void ca0132_setup_defaults(struct hda_codec *codec)
7263 {
7264 struct ca0132_spec *spec = codec->spec;
7265 unsigned int tmp;
7266 int num_fx;
7267 int idx, i;
7268
7269 if (spec->dsp_state != DSP_DOWNLOADED)
7270 return;
7271
7272 /* out, in effects + voicefx */
7273 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7274 for (idx = 0; idx < num_fx; idx++) {
7275 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7276 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
7277 ca0132_effects[idx].reqs[i],
7278 ca0132_effects[idx].def_vals[i]);
7279 }
7280 }
7281
7282 /*remove DSP headroom*/
7283 tmp = FLOAT_ZERO;
7284 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7285
7286 /*set speaker EQ bypass attenuation*/
7287 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
7288
7289 /* set AMic1 and AMic2 as mono mic */
7290 tmp = FLOAT_ONE;
7291 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7292 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7293
7294 /* set AMic1 as CrystalVoice input */
7295 tmp = FLOAT_ONE;
7296 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
7297
7298 /* set WUH source */
7299 tmp = FLOAT_TWO;
7300 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7301 }
7302
7303 /*
7304 * Setup default parameters for Recon3D/Recon3Di DSP.
7305 */
7306
r3d_setup_defaults(struct hda_codec * codec)7307 static void r3d_setup_defaults(struct hda_codec *codec)
7308 {
7309 struct ca0132_spec *spec = codec->spec;
7310 unsigned int tmp;
7311 int num_fx;
7312 int idx, i;
7313
7314 if (spec->dsp_state != DSP_DOWNLOADED)
7315 return;
7316
7317 ca0132_alt_dsp_scp_startup(codec);
7318 ca0132_alt_init_analog_mics(codec);
7319
7320 /*remove DSP headroom*/
7321 tmp = FLOAT_ZERO;
7322 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7323
7324 /* set WUH source */
7325 tmp = FLOAT_TWO;
7326 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7327 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7328
7329 /* Set speaker source? */
7330 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7331
7332 if (ca0132_quirk(spec) == QUIRK_R3DI)
7333 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
7334
7335 /* Setup effect defaults */
7336 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7337 for (idx = 0; idx < num_fx; idx++) {
7338 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7339 dspio_set_uint_param(codec,
7340 ca0132_effects[idx].mid,
7341 ca0132_effects[idx].reqs[i],
7342 ca0132_effects[idx].def_vals[i]);
7343 }
7344 }
7345 }
7346
7347 /*
7348 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
7349 * than the Chromebook setup.
7350 */
sbz_setup_defaults(struct hda_codec * codec)7351 static void sbz_setup_defaults(struct hda_codec *codec)
7352 {
7353 struct ca0132_spec *spec = codec->spec;
7354 unsigned int tmp;
7355 int num_fx;
7356 int idx, i;
7357
7358 if (spec->dsp_state != DSP_DOWNLOADED)
7359 return;
7360
7361 ca0132_alt_dsp_scp_startup(codec);
7362 ca0132_alt_init_analog_mics(codec);
7363 sbz_connect_streams(codec);
7364 sbz_chipio_startup_data(codec);
7365
7366 chipio_set_stream_control(codec, 0x03, 1);
7367 chipio_set_stream_control(codec, 0x04, 1);
7368
7369 /*
7370 * Sets internal input loopback to off, used to have a switch to
7371 * enable input loopback, but turned out to be way too buggy.
7372 */
7373 tmp = FLOAT_ONE;
7374 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7375 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7376
7377 /*remove DSP headroom*/
7378 tmp = FLOAT_ZERO;
7379 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7380
7381 /* set WUH source */
7382 tmp = FLOAT_TWO;
7383 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7384 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7385
7386 /* Set speaker source? */
7387 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7388
7389 ca0132_alt_dsp_initial_mic_setup(codec);
7390
7391 /* out, in effects + voicefx */
7392 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7393 for (idx = 0; idx < num_fx; idx++) {
7394 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7395 dspio_set_uint_param(codec,
7396 ca0132_effects[idx].mid,
7397 ca0132_effects[idx].reqs[i],
7398 ca0132_effects[idx].def_vals[i]);
7399 }
7400 }
7401
7402 ca0132_alt_create_dummy_stream(codec);
7403 }
7404
7405 /*
7406 * Setup default parameters for the Sound BlasterX AE-5 DSP.
7407 */
ae5_setup_defaults(struct hda_codec * codec)7408 static void ae5_setup_defaults(struct hda_codec *codec)
7409 {
7410 struct ca0132_spec *spec = codec->spec;
7411 unsigned int tmp;
7412 int num_fx;
7413 int idx, i;
7414
7415 if (spec->dsp_state != DSP_DOWNLOADED)
7416 return;
7417
7418 ca0132_alt_dsp_scp_startup(codec);
7419 ca0132_alt_init_analog_mics(codec);
7420 chipio_set_stream_control(codec, 0x03, 1);
7421 chipio_set_stream_control(codec, 0x04, 1);
7422
7423 /* New, unknown SCP req's */
7424 tmp = FLOAT_ZERO;
7425 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
7426 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
7427 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
7428 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
7429
7430 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
7431 ca0113_mmio_gpio_set(codec, 0, false);
7432 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
7433
7434 /* Internal loopback off */
7435 tmp = FLOAT_ONE;
7436 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7437 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7438
7439 /*remove DSP headroom*/
7440 tmp = FLOAT_ZERO;
7441 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7442
7443 /* set WUH source */
7444 tmp = FLOAT_TWO;
7445 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7446 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7447
7448 /* Set speaker source? */
7449 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7450
7451 ca0132_alt_dsp_initial_mic_setup(codec);
7452 ae5_post_dsp_register_set(codec);
7453 ae5_post_dsp_param_setup(codec);
7454 ae5_post_dsp_pll_setup(codec);
7455 ae5_post_dsp_stream_setup(codec);
7456 ae5_post_dsp_startup_data(codec);
7457
7458 /* out, in effects + voicefx */
7459 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7460 for (idx = 0; idx < num_fx; idx++) {
7461 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7462 dspio_set_uint_param(codec,
7463 ca0132_effects[idx].mid,
7464 ca0132_effects[idx].reqs[i],
7465 ca0132_effects[idx].def_vals[i]);
7466 }
7467 }
7468
7469 ca0132_alt_create_dummy_stream(codec);
7470 }
7471
7472 /*
7473 * Initialization of flags in chip
7474 */
ca0132_init_flags(struct hda_codec * codec)7475 static void ca0132_init_flags(struct hda_codec *codec)
7476 {
7477 struct ca0132_spec *spec = codec->spec;
7478
7479 if (ca0132_use_alt_functions(spec)) {
7480 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
7481 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
7482 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
7483 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
7484 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
7485 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7486 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
7487 chipio_set_control_flag(codec,
7488 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7489 chipio_set_control_flag(codec,
7490 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
7491 } else {
7492 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7493 chipio_set_control_flag(codec,
7494 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
7495 chipio_set_control_flag(codec,
7496 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
7497 chipio_set_control_flag(codec,
7498 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
7499 chipio_set_control_flag(codec,
7500 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7501 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
7502 }
7503 }
7504
7505 /*
7506 * Initialization of parameters in chip
7507 */
ca0132_init_params(struct hda_codec * codec)7508 static void ca0132_init_params(struct hda_codec *codec)
7509 {
7510 struct ca0132_spec *spec = codec->spec;
7511
7512 if (ca0132_use_alt_functions(spec)) {
7513 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7514 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
7515 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
7516 chipio_set_control_param(codec, 0, 0);
7517 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
7518 }
7519
7520 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
7521 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
7522 }
7523
ca0132_set_dsp_msr(struct hda_codec * codec,bool is96k)7524 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
7525 {
7526 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
7527 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
7528 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
7529 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
7530 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
7531 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
7532
7533 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7534 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7535 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7536 }
7537
ca0132_download_dsp_images(struct hda_codec * codec)7538 static bool ca0132_download_dsp_images(struct hda_codec *codec)
7539 {
7540 bool dsp_loaded = false;
7541 struct ca0132_spec *spec = codec->spec;
7542 const struct dsp_image_seg *dsp_os_image;
7543 const struct firmware *fw_entry = NULL;
7544 /*
7545 * Alternate firmwares for different variants. The Recon3Di apparently
7546 * can use the default firmware, but I'll leave the option in case
7547 * it needs it again.
7548 */
7549 switch (ca0132_quirk(spec)) {
7550 case QUIRK_SBZ:
7551 case QUIRK_R3D:
7552 case QUIRK_AE5:
7553 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
7554 codec->card->dev) != 0)
7555 codec_dbg(codec, "Desktop firmware not found.");
7556 else
7557 codec_dbg(codec, "Desktop firmware selected.");
7558 break;
7559 case QUIRK_R3DI:
7560 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
7561 codec->card->dev) != 0)
7562 codec_dbg(codec, "Recon3Di alt firmware not detected.");
7563 else
7564 codec_dbg(codec, "Recon3Di firmware selected.");
7565 break;
7566 default:
7567 break;
7568 }
7569 /*
7570 * Use default ctefx.bin if no alt firmware is detected, or if none
7571 * exists for your particular codec.
7572 */
7573 if (!fw_entry) {
7574 codec_dbg(codec, "Default firmware selected.");
7575 if (request_firmware(&fw_entry, EFX_FILE,
7576 codec->card->dev) != 0)
7577 return false;
7578 }
7579
7580 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
7581 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
7582 codec_err(codec, "ca0132 DSP load image failed\n");
7583 goto exit_download;
7584 }
7585
7586 dsp_loaded = dspload_wait_loaded(codec);
7587
7588 exit_download:
7589 release_firmware(fw_entry);
7590
7591 return dsp_loaded;
7592 }
7593
ca0132_download_dsp(struct hda_codec * codec)7594 static void ca0132_download_dsp(struct hda_codec *codec)
7595 {
7596 struct ca0132_spec *spec = codec->spec;
7597
7598 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
7599 return; /* NOP */
7600 #endif
7601
7602 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
7603 return; /* don't retry failures */
7604
7605 chipio_enable_clocks(codec);
7606 if (spec->dsp_state != DSP_DOWNLOADED) {
7607 spec->dsp_state = DSP_DOWNLOADING;
7608
7609 if (!ca0132_download_dsp_images(codec))
7610 spec->dsp_state = DSP_DOWNLOAD_FAILED;
7611 else
7612 spec->dsp_state = DSP_DOWNLOADED;
7613 }
7614
7615 /* For codecs using alt functions, this is already done earlier */
7616 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
7617 ca0132_set_dsp_msr(codec, true);
7618 }
7619
ca0132_process_dsp_response(struct hda_codec * codec,struct hda_jack_callback * callback)7620 static void ca0132_process_dsp_response(struct hda_codec *codec,
7621 struct hda_jack_callback *callback)
7622 {
7623 struct ca0132_spec *spec = codec->spec;
7624
7625 codec_dbg(codec, "ca0132_process_dsp_response\n");
7626 snd_hda_power_up_pm(codec);
7627 if (spec->wait_scp) {
7628 if (dspio_get_response_data(codec) >= 0)
7629 spec->wait_scp = 0;
7630 }
7631
7632 dspio_clear_response_queue(codec);
7633 snd_hda_power_down_pm(codec);
7634 }
7635
hp_callback(struct hda_codec * codec,struct hda_jack_callback * cb)7636 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
7637 {
7638 struct ca0132_spec *spec = codec->spec;
7639 struct hda_jack_tbl *tbl;
7640
7641 /* Delay enabling the HP amp, to let the mic-detection
7642 * state machine run.
7643 */
7644 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
7645 if (tbl)
7646 tbl->block_report = 1;
7647 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
7648 }
7649
amic_callback(struct hda_codec * codec,struct hda_jack_callback * cb)7650 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
7651 {
7652 struct ca0132_spec *spec = codec->spec;
7653
7654 if (ca0132_use_alt_functions(spec))
7655 ca0132_alt_select_in(codec);
7656 else
7657 ca0132_select_mic(codec);
7658 }
7659
ca0132_init_unsol(struct hda_codec * codec)7660 static void ca0132_init_unsol(struct hda_codec *codec)
7661 {
7662 struct ca0132_spec *spec = codec->spec;
7663 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
7664 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
7665 amic_callback);
7666 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
7667 ca0132_process_dsp_response);
7668 /* Front headphone jack detection */
7669 if (ca0132_use_alt_functions(spec))
7670 snd_hda_jack_detect_enable_callback(codec,
7671 spec->unsol_tag_front_hp, hp_callback);
7672 }
7673
7674 /*
7675 * Verbs tables.
7676 */
7677
7678 /* Sends before DSP download. */
7679 static struct hda_verb ca0132_base_init_verbs[] = {
7680 /*enable ct extension*/
7681 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
7682 {}
7683 };
7684
7685 /* Send at exit. */
7686 static struct hda_verb ca0132_base_exit_verbs[] = {
7687 /*set afg to D3*/
7688 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
7689 /*disable ct extension*/
7690 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
7691 {}
7692 };
7693
7694 /* Other verbs tables. Sends after DSP download. */
7695
7696 static struct hda_verb ca0132_init_verbs0[] = {
7697 /* chip init verbs */
7698 {0x15, 0x70D, 0xF0},
7699 {0x15, 0x70E, 0xFE},
7700 {0x15, 0x707, 0x75},
7701 {0x15, 0x707, 0xD3},
7702 {0x15, 0x707, 0x09},
7703 {0x15, 0x707, 0x53},
7704 {0x15, 0x707, 0xD4},
7705 {0x15, 0x707, 0xEF},
7706 {0x15, 0x707, 0x75},
7707 {0x15, 0x707, 0xD3},
7708 {0x15, 0x707, 0x09},
7709 {0x15, 0x707, 0x02},
7710 {0x15, 0x707, 0x37},
7711 {0x15, 0x707, 0x78},
7712 {0x15, 0x53C, 0xCE},
7713 {0x15, 0x575, 0xC9},
7714 {0x15, 0x53D, 0xCE},
7715 {0x15, 0x5B7, 0xC9},
7716 {0x15, 0x70D, 0xE8},
7717 {0x15, 0x70E, 0xFE},
7718 {0x15, 0x707, 0x02},
7719 {0x15, 0x707, 0x68},
7720 {0x15, 0x707, 0x62},
7721 {0x15, 0x53A, 0xCE},
7722 {0x15, 0x546, 0xC9},
7723 {0x15, 0x53B, 0xCE},
7724 {0x15, 0x5E8, 0xC9},
7725 {}
7726 };
7727
7728 /* Extra init verbs for desktop cards. */
7729 static struct hda_verb ca0132_init_verbs1[] = {
7730 {0x15, 0x70D, 0x20},
7731 {0x15, 0x70E, 0x19},
7732 {0x15, 0x707, 0x00},
7733 {0x15, 0x539, 0xCE},
7734 {0x15, 0x546, 0xC9},
7735 {0x15, 0x70D, 0xB7},
7736 {0x15, 0x70E, 0x09},
7737 {0x15, 0x707, 0x10},
7738 {0x15, 0x70D, 0xAF},
7739 {0x15, 0x70E, 0x09},
7740 {0x15, 0x707, 0x01},
7741 {0x15, 0x707, 0x05},
7742 {0x15, 0x70D, 0x73},
7743 {0x15, 0x70E, 0x09},
7744 {0x15, 0x707, 0x14},
7745 {0x15, 0x6FF, 0xC4},
7746 {}
7747 };
7748
ca0132_init_chip(struct hda_codec * codec)7749 static void ca0132_init_chip(struct hda_codec *codec)
7750 {
7751 struct ca0132_spec *spec = codec->spec;
7752 int num_fx;
7753 int i;
7754 unsigned int on;
7755
7756 mutex_init(&spec->chipio_mutex);
7757
7758 spec->cur_out_type = SPEAKER_OUT;
7759 if (!ca0132_use_alt_functions(spec))
7760 spec->cur_mic_type = DIGITAL_MIC;
7761 else
7762 spec->cur_mic_type = REAR_MIC;
7763
7764 spec->cur_mic_boost = 0;
7765
7766 for (i = 0; i < VNODES_COUNT; i++) {
7767 spec->vnode_lvol[i] = 0x5a;
7768 spec->vnode_rvol[i] = 0x5a;
7769 spec->vnode_lswitch[i] = 0;
7770 spec->vnode_rswitch[i] = 0;
7771 }
7772
7773 /*
7774 * Default states for effects are in ca0132_effects[].
7775 */
7776 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7777 for (i = 0; i < num_fx; i++) {
7778 on = (unsigned int)ca0132_effects[i].reqs[0];
7779 spec->effects_switch[i] = on ? 1 : 0;
7780 }
7781 /*
7782 * Sets defaults for the effect slider controls, only for alternative
7783 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
7784 */
7785 if (ca0132_use_alt_controls(spec)) {
7786 spec->xbass_xover_freq = 8;
7787 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
7788 spec->fx_ctl_val[i] = effect_slider_defaults[i];
7789 }
7790
7791 spec->voicefx_val = 0;
7792 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
7793 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
7794
7795 /*
7796 * The ZxR doesn't have a front panel header, and it's line-in is on
7797 * the daughter board. So, there is no input enum control, and we need
7798 * to make sure that spec->in_enum_val is set properly.
7799 */
7800 if (ca0132_quirk(spec) == QUIRK_ZXR)
7801 spec->in_enum_val = REAR_MIC;
7802
7803 #ifdef ENABLE_TUNING_CONTROLS
7804 ca0132_init_tuning_defaults(codec);
7805 #endif
7806 }
7807
7808 /*
7809 * Recon3Di exit specific commands.
7810 */
7811 /* prevents popping noise on shutdown */
r3di_gpio_shutdown(struct hda_codec * codec)7812 static void r3di_gpio_shutdown(struct hda_codec *codec)
7813 {
7814 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
7815 }
7816
7817 /*
7818 * Sound Blaster Z exit specific commands.
7819 */
sbz_region2_exit(struct hda_codec * codec)7820 static void sbz_region2_exit(struct hda_codec *codec)
7821 {
7822 struct ca0132_spec *spec = codec->spec;
7823 unsigned int i;
7824
7825 for (i = 0; i < 4; i++)
7826 writeb(0x0, spec->mem_base + 0x100);
7827 for (i = 0; i < 8; i++)
7828 writeb(0xb3, spec->mem_base + 0x304);
7829
7830 ca0113_mmio_gpio_set(codec, 0, false);
7831 ca0113_mmio_gpio_set(codec, 1, false);
7832 ca0113_mmio_gpio_set(codec, 4, true);
7833 ca0113_mmio_gpio_set(codec, 5, false);
7834 ca0113_mmio_gpio_set(codec, 7, false);
7835 }
7836
sbz_set_pin_ctl_default(struct hda_codec * codec)7837 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
7838 {
7839 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
7840 unsigned int i;
7841
7842 snd_hda_codec_write(codec, 0x11, 0,
7843 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
7844
7845 for (i = 0; i < ARRAY_SIZE(pins); i++)
7846 snd_hda_codec_write(codec, pins[i], 0,
7847 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
7848 }
7849
ca0132_clear_unsolicited(struct hda_codec * codec)7850 static void ca0132_clear_unsolicited(struct hda_codec *codec)
7851 {
7852 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
7853 unsigned int i;
7854
7855 for (i = 0; i < ARRAY_SIZE(pins); i++) {
7856 snd_hda_codec_write(codec, pins[i], 0,
7857 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
7858 }
7859 }
7860
7861 /* On shutdown, sends commands in sets of three */
sbz_gpio_shutdown_commands(struct hda_codec * codec,int dir,int mask,int data)7862 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
7863 int mask, int data)
7864 {
7865 if (dir >= 0)
7866 snd_hda_codec_write(codec, 0x01, 0,
7867 AC_VERB_SET_GPIO_DIRECTION, dir);
7868 if (mask >= 0)
7869 snd_hda_codec_write(codec, 0x01, 0,
7870 AC_VERB_SET_GPIO_MASK, mask);
7871
7872 if (data >= 0)
7873 snd_hda_codec_write(codec, 0x01, 0,
7874 AC_VERB_SET_GPIO_DATA, data);
7875 }
7876
zxr_dbpro_power_state_shutdown(struct hda_codec * codec)7877 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
7878 {
7879 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
7880 unsigned int i;
7881
7882 for (i = 0; i < ARRAY_SIZE(pins); i++)
7883 snd_hda_codec_write(codec, pins[i], 0,
7884 AC_VERB_SET_POWER_STATE, 0x03);
7885 }
7886
sbz_exit_chip(struct hda_codec * codec)7887 static void sbz_exit_chip(struct hda_codec *codec)
7888 {
7889 chipio_set_stream_control(codec, 0x03, 0);
7890 chipio_set_stream_control(codec, 0x04, 0);
7891
7892 /* Mess with GPIO */
7893 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7894 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7895 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7896
7897 chipio_set_stream_control(codec, 0x14, 0);
7898 chipio_set_stream_control(codec, 0x0C, 0);
7899
7900 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7901 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7902
7903 chipio_write(codec, 0x18a020, 0x00000083);
7904
7905 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7906 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7907 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7908
7909 chipio_set_stream_control(codec, 0x0C, 0);
7910
7911 chipio_set_control_param(codec, 0x0D, 0x24);
7912
7913 ca0132_clear_unsolicited(codec);
7914 sbz_set_pin_ctl_default(codec);
7915
7916 snd_hda_codec_write(codec, 0x0B, 0,
7917 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7918
7919 sbz_region2_exit(codec);
7920 }
7921
r3d_exit_chip(struct hda_codec * codec)7922 static void r3d_exit_chip(struct hda_codec *codec)
7923 {
7924 ca0132_clear_unsolicited(codec);
7925 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7926 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7927 }
7928
ae5_exit_chip(struct hda_codec * codec)7929 static void ae5_exit_chip(struct hda_codec *codec)
7930 {
7931 chipio_set_stream_control(codec, 0x03, 0);
7932 chipio_set_stream_control(codec, 0x04, 0);
7933
7934 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
7935 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7936 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7937 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
7938 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
7939 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
7940 ca0113_mmio_gpio_set(codec, 0, false);
7941 ca0113_mmio_gpio_set(codec, 1, false);
7942
7943 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7944 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
7945
7946 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7947
7948 chipio_set_stream_control(codec, 0x18, 0);
7949 chipio_set_stream_control(codec, 0x0c, 0);
7950
7951 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
7952 }
7953
zxr_exit_chip(struct hda_codec * codec)7954 static void zxr_exit_chip(struct hda_codec *codec)
7955 {
7956 chipio_set_stream_control(codec, 0x03, 0);
7957 chipio_set_stream_control(codec, 0x04, 0);
7958 chipio_set_stream_control(codec, 0x14, 0);
7959 chipio_set_stream_control(codec, 0x0C, 0);
7960
7961 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7962 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7963
7964 chipio_write(codec, 0x18a020, 0x00000083);
7965
7966 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7967 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
7968
7969 ca0132_clear_unsolicited(codec);
7970 sbz_set_pin_ctl_default(codec);
7971 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7972
7973 ca0113_mmio_gpio_set(codec, 5, false);
7974 ca0113_mmio_gpio_set(codec, 2, false);
7975 ca0113_mmio_gpio_set(codec, 3, false);
7976 ca0113_mmio_gpio_set(codec, 0, false);
7977 ca0113_mmio_gpio_set(codec, 4, true);
7978 ca0113_mmio_gpio_set(codec, 0, true);
7979 ca0113_mmio_gpio_set(codec, 5, true);
7980 ca0113_mmio_gpio_set(codec, 2, false);
7981 ca0113_mmio_gpio_set(codec, 3, false);
7982 }
7983
ca0132_exit_chip(struct hda_codec * codec)7984 static void ca0132_exit_chip(struct hda_codec *codec)
7985 {
7986 /* put any chip cleanup stuffs here. */
7987
7988 if (dspload_is_loaded(codec))
7989 dsp_reset(codec);
7990 }
7991
7992 /*
7993 * This fixes a problem that was hard to reproduce. Very rarely, I would
7994 * boot up, and there would be no sound, but the DSP indicated it had loaded
7995 * properly. I did a few memory dumps to see if anything was different, and
7996 * there were a few areas of memory uninitialized with a1a2a3a4. This function
7997 * checks if those areas are uninitialized, and if they are, it'll attempt to
7998 * reload the card 3 times. Usually it fixes by the second.
7999 */
sbz_dsp_startup_check(struct hda_codec * codec)8000 static void sbz_dsp_startup_check(struct hda_codec *codec)
8001 {
8002 struct ca0132_spec *spec = codec->spec;
8003 unsigned int dsp_data_check[4];
8004 unsigned int cur_address = 0x390;
8005 unsigned int i;
8006 unsigned int failure = 0;
8007 unsigned int reload = 3;
8008
8009 if (spec->startup_check_entered)
8010 return;
8011
8012 spec->startup_check_entered = true;
8013
8014 for (i = 0; i < 4; i++) {
8015 chipio_read(codec, cur_address, &dsp_data_check[i]);
8016 cur_address += 0x4;
8017 }
8018 for (i = 0; i < 4; i++) {
8019 if (dsp_data_check[i] == 0xa1a2a3a4)
8020 failure = 1;
8021 }
8022
8023 codec_dbg(codec, "Startup Check: %d ", failure);
8024 if (failure)
8025 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
8026 /*
8027 * While the failure condition is true, and we haven't reached our
8028 * three reload limit, continue trying to reload the driver and
8029 * fix the issue.
8030 */
8031 while (failure && (reload != 0)) {
8032 codec_info(codec, "Reloading... Tries left: %d", reload);
8033 sbz_exit_chip(codec);
8034 spec->dsp_state = DSP_DOWNLOAD_INIT;
8035 codec->patch_ops.init(codec);
8036 failure = 0;
8037 for (i = 0; i < 4; i++) {
8038 chipio_read(codec, cur_address, &dsp_data_check[i]);
8039 cur_address += 0x4;
8040 }
8041 for (i = 0; i < 4; i++) {
8042 if (dsp_data_check[i] == 0xa1a2a3a4)
8043 failure = 1;
8044 }
8045 reload--;
8046 }
8047
8048 if (!failure && reload < 3)
8049 codec_info(codec, "DSP fixed.");
8050
8051 if (!failure)
8052 return;
8053
8054 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
8055 }
8056
8057 /*
8058 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
8059 * extra precision for decibel values. If you had the dB value in floating point
8060 * you would take the value after the decimal point, multiply by 64, and divide
8061 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
8062 * implement fixed point or floating point dB volumes. For now, I'll set them
8063 * to 0 just incase a value has lingered from a boot into Windows.
8064 */
ca0132_alt_vol_setup(struct hda_codec * codec)8065 static void ca0132_alt_vol_setup(struct hda_codec *codec)
8066 {
8067 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
8068 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
8069 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
8070 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
8071 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
8072 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
8073 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
8074 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
8075 }
8076
8077 /*
8078 * Extra commands that don't really fit anywhere else.
8079 */
sbz_pre_dsp_setup(struct hda_codec * codec)8080 static void sbz_pre_dsp_setup(struct hda_codec *codec)
8081 {
8082 struct ca0132_spec *spec = codec->spec;
8083
8084 writel(0x00820680, spec->mem_base + 0x01C);
8085 writel(0x00820680, spec->mem_base + 0x01C);
8086
8087 chipio_write(codec, 0x18b0a4, 0x000000c2);
8088
8089 snd_hda_codec_write(codec, 0x11, 0,
8090 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
8091 }
8092
r3d_pre_dsp_setup(struct hda_codec * codec)8093 static void r3d_pre_dsp_setup(struct hda_codec *codec)
8094 {
8095 chipio_write(codec, 0x18b0a4, 0x000000c2);
8096
8097 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8098 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
8099 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8100 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
8101 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8102 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
8103
8104 snd_hda_codec_write(codec, 0x11, 0,
8105 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
8106 }
8107
r3di_pre_dsp_setup(struct hda_codec * codec)8108 static void r3di_pre_dsp_setup(struct hda_codec *codec)
8109 {
8110 chipio_write(codec, 0x18b0a4, 0x000000c2);
8111
8112 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8113 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
8114 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8115 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
8116 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8117 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
8118
8119 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8120 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
8121 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8122 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
8123 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8124 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
8125 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8126 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
8127
8128 snd_hda_codec_write(codec, 0x11, 0,
8129 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
8130 }
8131
8132 /*
8133 * These are sent before the DSP is downloaded. Not sure
8134 * what they do, or if they're necessary. Could possibly
8135 * be removed. Figure they're better to leave in.
8136 */
ca0132_mmio_init(struct hda_codec * codec)8137 static void ca0132_mmio_init(struct hda_codec *codec)
8138 {
8139 struct ca0132_spec *spec = codec->spec;
8140
8141 if (ca0132_quirk(spec) == QUIRK_AE5)
8142 writel(0x00000001, spec->mem_base + 0x400);
8143 else
8144 writel(0x00000000, spec->mem_base + 0x400);
8145
8146 if (ca0132_quirk(spec) == QUIRK_AE5)
8147 writel(0x00000001, spec->mem_base + 0x408);
8148 else
8149 writel(0x00000000, spec->mem_base + 0x408);
8150
8151 if (ca0132_quirk(spec) == QUIRK_AE5)
8152 writel(0x00000001, spec->mem_base + 0x40c);
8153 else
8154 writel(0x00000000, spec->mem_base + 0x40C);
8155
8156 if (ca0132_quirk(spec) == QUIRK_ZXR)
8157 writel(0x00880640, spec->mem_base + 0x01C);
8158 else
8159 writel(0x00880680, spec->mem_base + 0x01C);
8160
8161 if (ca0132_quirk(spec) == QUIRK_AE5)
8162 writel(0x00000080, spec->mem_base + 0xC0C);
8163 else
8164 writel(0x00000083, spec->mem_base + 0xC0C);
8165
8166 writel(0x00000030, spec->mem_base + 0xC00);
8167 writel(0x00000000, spec->mem_base + 0xC04);
8168
8169 if (ca0132_quirk(spec) == QUIRK_AE5)
8170 writel(0x00000000, spec->mem_base + 0xC0C);
8171 else
8172 writel(0x00000003, spec->mem_base + 0xC0C);
8173
8174 writel(0x00000003, spec->mem_base + 0xC0C);
8175 writel(0x00000003, spec->mem_base + 0xC0C);
8176 writel(0x00000003, spec->mem_base + 0xC0C);
8177
8178 if (ca0132_quirk(spec) == QUIRK_AE5)
8179 writel(0x00000001, spec->mem_base + 0xC08);
8180 else
8181 writel(0x000000C1, spec->mem_base + 0xC08);
8182
8183 writel(0x000000F1, spec->mem_base + 0xC08);
8184 writel(0x00000001, spec->mem_base + 0xC08);
8185 writel(0x000000C7, spec->mem_base + 0xC08);
8186 writel(0x000000C1, spec->mem_base + 0xC08);
8187 writel(0x00000080, spec->mem_base + 0xC04);
8188
8189 if (ca0132_quirk(spec) == QUIRK_AE5) {
8190 writel(0x00000000, spec->mem_base + 0x42c);
8191 writel(0x00000000, spec->mem_base + 0x46c);
8192 writel(0x00000000, spec->mem_base + 0x4ac);
8193 writel(0x00000000, spec->mem_base + 0x4ec);
8194 writel(0x00000000, spec->mem_base + 0x43c);
8195 writel(0x00000000, spec->mem_base + 0x47c);
8196 writel(0x00000000, spec->mem_base + 0x4bc);
8197 writel(0x00000000, spec->mem_base + 0x4fc);
8198 writel(0x00000600, spec->mem_base + 0x100);
8199 writel(0x00000014, spec->mem_base + 0x410);
8200 writel(0x0000060f, spec->mem_base + 0x100);
8201 writel(0x0000070f, spec->mem_base + 0x100);
8202 writel(0x00000aff, spec->mem_base + 0x830);
8203 writel(0x00000000, spec->mem_base + 0x86c);
8204 writel(0x0000006b, spec->mem_base + 0x800);
8205 writel(0x00000001, spec->mem_base + 0x86c);
8206 writel(0x0000006b, spec->mem_base + 0x800);
8207 writel(0x00000057, spec->mem_base + 0x804);
8208 writel(0x00800000, spec->mem_base + 0x20c);
8209 }
8210 }
8211
8212 /*
8213 * This function writes to some SFR's, does some region2 writes, and then
8214 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
8215 * what it does.
8216 */
ae5_register_set(struct hda_codec * codec)8217 static void ae5_register_set(struct hda_codec *codec)
8218 {
8219 struct ca0132_spec *spec = codec->spec;
8220
8221 chipio_8051_write_direct(codec, 0x93, 0x10);
8222 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8223 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
8224 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8225 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
8226
8227 writeb(0x0f, spec->mem_base + 0x304);
8228 writeb(0x0f, spec->mem_base + 0x304);
8229 writeb(0x0f, spec->mem_base + 0x304);
8230 writeb(0x0f, spec->mem_base + 0x304);
8231 writeb(0x0e, spec->mem_base + 0x100);
8232 writeb(0x1f, spec->mem_base + 0x304);
8233 writeb(0x0c, spec->mem_base + 0x100);
8234 writeb(0x3f, spec->mem_base + 0x304);
8235 writeb(0x08, spec->mem_base + 0x100);
8236 writeb(0x7f, spec->mem_base + 0x304);
8237 writeb(0x00, spec->mem_base + 0x100);
8238 writeb(0xff, spec->mem_base + 0x304);
8239
8240 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
8241
8242 chipio_8051_write_direct(codec, 0x90, 0x00);
8243 chipio_8051_write_direct(codec, 0x90, 0x10);
8244
8245 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8246
8247 chipio_write(codec, 0x18b0a4, 0x000000c2);
8248
8249 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
8250 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
8251 }
8252
8253 /*
8254 * Extra init functions for alternative ca0132 codecs. Done
8255 * here so they don't clutter up the main ca0132_init function
8256 * anymore than they have to.
8257 */
ca0132_alt_init(struct hda_codec * codec)8258 static void ca0132_alt_init(struct hda_codec *codec)
8259 {
8260 struct ca0132_spec *spec = codec->spec;
8261
8262 ca0132_alt_vol_setup(codec);
8263
8264 switch (ca0132_quirk(spec)) {
8265 case QUIRK_SBZ:
8266 codec_dbg(codec, "SBZ alt_init");
8267 ca0132_gpio_init(codec);
8268 sbz_pre_dsp_setup(codec);
8269 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8270 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8271 break;
8272 case QUIRK_R3DI:
8273 codec_dbg(codec, "R3DI alt_init");
8274 ca0132_gpio_init(codec);
8275 ca0132_gpio_setup(codec);
8276 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
8277 r3di_pre_dsp_setup(codec);
8278 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8279 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
8280 break;
8281 case QUIRK_R3D:
8282 r3d_pre_dsp_setup(codec);
8283 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8284 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8285 break;
8286 case QUIRK_AE5:
8287 ca0132_gpio_init(codec);
8288 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8289 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
8290 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8291 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
8292 chipio_write(codec, 0x18b030, 0x00000020);
8293 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8294 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8295 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8296 break;
8297 case QUIRK_ZXR:
8298 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8299 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8300 break;
8301 default:
8302 break;
8303 }
8304 }
8305
ca0132_init(struct hda_codec * codec)8306 static int ca0132_init(struct hda_codec *codec)
8307 {
8308 struct ca0132_spec *spec = codec->spec;
8309 struct auto_pin_cfg *cfg = &spec->autocfg;
8310 int i;
8311 bool dsp_loaded;
8312
8313 /*
8314 * If the DSP is already downloaded, and init has been entered again,
8315 * there's only two reasons for it. One, the codec has awaken from a
8316 * suspended state, and in that case dspload_is_loaded will return
8317 * false, and the init will be ran again. The other reason it gets
8318 * re entered is on startup for some reason it triggers a suspend and
8319 * resume state. In this case, it will check if the DSP is downloaded,
8320 * and not run the init function again. For codecs using alt_functions,
8321 * it will check if the DSP is loaded properly.
8322 */
8323 if (spec->dsp_state == DSP_DOWNLOADED) {
8324 dsp_loaded = dspload_is_loaded(codec);
8325 if (!dsp_loaded) {
8326 spec->dsp_reload = true;
8327 spec->dsp_state = DSP_DOWNLOAD_INIT;
8328 } else {
8329 if (ca0132_quirk(spec) == QUIRK_SBZ)
8330 sbz_dsp_startup_check(codec);
8331 return 0;
8332 }
8333 }
8334
8335 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
8336 spec->dsp_state = DSP_DOWNLOAD_INIT;
8337 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
8338
8339 if (ca0132_use_pci_mmio(spec))
8340 ca0132_mmio_init(codec);
8341
8342 snd_hda_power_up_pm(codec);
8343
8344 if (ca0132_quirk(spec) == QUIRK_AE5)
8345 ae5_register_set(codec);
8346
8347 ca0132_init_unsol(codec);
8348 ca0132_init_params(codec);
8349 ca0132_init_flags(codec);
8350
8351 snd_hda_sequence_write(codec, spec->base_init_verbs);
8352
8353 if (ca0132_use_alt_functions(spec))
8354 ca0132_alt_init(codec);
8355
8356 ca0132_download_dsp(codec);
8357
8358 ca0132_refresh_widget_caps(codec);
8359
8360 switch (ca0132_quirk(spec)) {
8361 case QUIRK_R3DI:
8362 case QUIRK_R3D:
8363 r3d_setup_defaults(codec);
8364 break;
8365 case QUIRK_SBZ:
8366 case QUIRK_ZXR:
8367 sbz_setup_defaults(codec);
8368 break;
8369 case QUIRK_AE5:
8370 ae5_setup_defaults(codec);
8371 break;
8372 default:
8373 ca0132_setup_defaults(codec);
8374 ca0132_init_analog_mic2(codec);
8375 ca0132_init_dmic(codec);
8376 break;
8377 }
8378
8379 for (i = 0; i < spec->num_outputs; i++)
8380 init_output(codec, spec->out_pins[i], spec->dacs[0]);
8381
8382 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8383
8384 for (i = 0; i < spec->num_inputs; i++)
8385 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8386
8387 init_input(codec, cfg->dig_in_pin, spec->dig_in);
8388
8389 if (!ca0132_use_alt_functions(spec)) {
8390 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8391 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8392 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
8393 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8394 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
8395 }
8396
8397 if (ca0132_quirk(spec) == QUIRK_SBZ)
8398 ca0132_gpio_setup(codec);
8399
8400 snd_hda_sequence_write(codec, spec->spec_init_verbs);
8401 if (ca0132_use_alt_functions(spec)) {
8402 ca0132_alt_select_out(codec);
8403 ca0132_alt_select_in(codec);
8404 } else {
8405 ca0132_select_out(codec);
8406 ca0132_select_mic(codec);
8407 }
8408
8409 snd_hda_jack_report_sync(codec);
8410
8411 /*
8412 * Re set the PlayEnhancement switch on a resume event, because the
8413 * controls will not be reloaded.
8414 */
8415 if (spec->dsp_reload) {
8416 spec->dsp_reload = false;
8417 ca0132_pe_switch_set(codec);
8418 }
8419
8420 snd_hda_power_down_pm(codec);
8421
8422 return 0;
8423 }
8424
dbpro_init(struct hda_codec * codec)8425 static int dbpro_init(struct hda_codec *codec)
8426 {
8427 struct ca0132_spec *spec = codec->spec;
8428 struct auto_pin_cfg *cfg = &spec->autocfg;
8429 unsigned int i;
8430
8431 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8432 init_input(codec, cfg->dig_in_pin, spec->dig_in);
8433
8434 for (i = 0; i < spec->num_inputs; i++)
8435 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8436
8437 return 0;
8438 }
8439
ca0132_free(struct hda_codec * codec)8440 static void ca0132_free(struct hda_codec *codec)
8441 {
8442 struct ca0132_spec *spec = codec->spec;
8443
8444 cancel_delayed_work_sync(&spec->unsol_hp_work);
8445 snd_hda_power_up(codec);
8446 switch (ca0132_quirk(spec)) {
8447 case QUIRK_SBZ:
8448 sbz_exit_chip(codec);
8449 break;
8450 case QUIRK_ZXR:
8451 zxr_exit_chip(codec);
8452 break;
8453 case QUIRK_R3D:
8454 r3d_exit_chip(codec);
8455 break;
8456 case QUIRK_AE5:
8457 ae5_exit_chip(codec);
8458 break;
8459 case QUIRK_R3DI:
8460 r3di_gpio_shutdown(codec);
8461 break;
8462 default:
8463 break;
8464 }
8465
8466 snd_hda_sequence_write(codec, spec->base_exit_verbs);
8467 ca0132_exit_chip(codec);
8468
8469 snd_hda_power_down(codec);
8470 #ifdef CONFIG_PCI
8471 if (spec->mem_base)
8472 pci_iounmap(codec->bus->pci, spec->mem_base);
8473 #endif
8474 kfree(spec->spec_init_verbs);
8475 kfree(codec->spec);
8476 }
8477
dbpro_free(struct hda_codec * codec)8478 static void dbpro_free(struct hda_codec *codec)
8479 {
8480 struct ca0132_spec *spec = codec->spec;
8481
8482 zxr_dbpro_power_state_shutdown(codec);
8483
8484 kfree(spec->spec_init_verbs);
8485 kfree(codec->spec);
8486 }
8487
ca0132_reboot_notify(struct hda_codec * codec)8488 static void ca0132_reboot_notify(struct hda_codec *codec)
8489 {
8490 codec->patch_ops.free(codec);
8491 }
8492
8493 #ifdef CONFIG_PM
ca0132_suspend(struct hda_codec * codec)8494 static int ca0132_suspend(struct hda_codec *codec)
8495 {
8496 struct ca0132_spec *spec = codec->spec;
8497
8498 cancel_delayed_work_sync(&spec->unsol_hp_work);
8499 return 0;
8500 }
8501 #endif
8502
8503 static const struct hda_codec_ops ca0132_patch_ops = {
8504 .build_controls = ca0132_build_controls,
8505 .build_pcms = ca0132_build_pcms,
8506 .init = ca0132_init,
8507 .free = ca0132_free,
8508 .unsol_event = snd_hda_jack_unsol_event,
8509 #ifdef CONFIG_PM
8510 .suspend = ca0132_suspend,
8511 #endif
8512 .reboot_notify = ca0132_reboot_notify,
8513 };
8514
8515 static const struct hda_codec_ops dbpro_patch_ops = {
8516 .build_controls = dbpro_build_controls,
8517 .build_pcms = dbpro_build_pcms,
8518 .init = dbpro_init,
8519 .free = dbpro_free,
8520 };
8521
ca0132_config(struct hda_codec * codec)8522 static void ca0132_config(struct hda_codec *codec)
8523 {
8524 struct ca0132_spec *spec = codec->spec;
8525
8526 spec->dacs[0] = 0x2;
8527 spec->dacs[1] = 0x3;
8528 spec->dacs[2] = 0x4;
8529
8530 spec->multiout.dac_nids = spec->dacs;
8531 spec->multiout.num_dacs = 3;
8532
8533 if (!ca0132_use_alt_functions(spec))
8534 spec->multiout.max_channels = 2;
8535 else
8536 spec->multiout.max_channels = 6;
8537
8538 switch (ca0132_quirk(spec)) {
8539 case QUIRK_ALIENWARE:
8540 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
8541 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
8542 break;
8543 case QUIRK_SBZ:
8544 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
8545 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
8546 break;
8547 case QUIRK_ZXR:
8548 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
8549 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
8550 break;
8551 case QUIRK_R3D:
8552 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
8553 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
8554 break;
8555 case QUIRK_R3DI:
8556 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
8557 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
8558 break;
8559 case QUIRK_AE5:
8560 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
8561 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
8562 break;
8563 default:
8564 break;
8565 }
8566
8567 switch (ca0132_quirk(spec)) {
8568 case QUIRK_ALIENWARE:
8569 spec->num_outputs = 2;
8570 spec->out_pins[0] = 0x0b; /* speaker out */
8571 spec->out_pins[1] = 0x0f;
8572 spec->shared_out_nid = 0x2;
8573 spec->unsol_tag_hp = 0x0f;
8574
8575 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8576 spec->adcs[1] = 0x8; /* analog mic2 */
8577 spec->adcs[2] = 0xa; /* what u hear */
8578
8579 spec->num_inputs = 3;
8580 spec->input_pins[0] = 0x12;
8581 spec->input_pins[1] = 0x11;
8582 spec->input_pins[2] = 0x13;
8583 spec->shared_mic_nid = 0x7;
8584 spec->unsol_tag_amic1 = 0x11;
8585 break;
8586 case QUIRK_SBZ:
8587 case QUIRK_R3D:
8588 spec->num_outputs = 2;
8589 spec->out_pins[0] = 0x0B; /* Line out */
8590 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8591 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8592 spec->out_pins[3] = 0x11; /* Rear surround */
8593 spec->shared_out_nid = 0x2;
8594 spec->unsol_tag_hp = spec->out_pins[1];
8595 spec->unsol_tag_front_hp = spec->out_pins[2];
8596
8597 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8598 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8599 spec->adcs[2] = 0xa; /* what u hear */
8600
8601 spec->num_inputs = 2;
8602 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8603 spec->input_pins[1] = 0x13; /* What U Hear */
8604 spec->shared_mic_nid = 0x7;
8605 spec->unsol_tag_amic1 = spec->input_pins[0];
8606
8607 /* SPDIF I/O */
8608 spec->dig_out = 0x05;
8609 spec->multiout.dig_out_nid = spec->dig_out;
8610 spec->dig_in = 0x09;
8611 break;
8612 case QUIRK_ZXR:
8613 spec->num_outputs = 2;
8614 spec->out_pins[0] = 0x0B; /* Line out */
8615 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8616 spec->out_pins[2] = 0x10; /* Center/LFE */
8617 spec->out_pins[3] = 0x11; /* Rear surround */
8618 spec->shared_out_nid = 0x2;
8619 spec->unsol_tag_hp = spec->out_pins[1];
8620 spec->unsol_tag_front_hp = spec->out_pins[2];
8621
8622 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8623 spec->adcs[1] = 0x8; /* Not connected, no front mic */
8624 spec->adcs[2] = 0xa; /* what u hear */
8625
8626 spec->num_inputs = 2;
8627 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8628 spec->input_pins[1] = 0x13; /* What U Hear */
8629 spec->shared_mic_nid = 0x7;
8630 spec->unsol_tag_amic1 = spec->input_pins[0];
8631 break;
8632 case QUIRK_ZXR_DBPRO:
8633 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
8634
8635 spec->num_inputs = 1;
8636 spec->input_pins[0] = 0x11; /* RCA Line-in */
8637
8638 spec->dig_out = 0x05;
8639 spec->multiout.dig_out_nid = spec->dig_out;
8640
8641 spec->dig_in = 0x09;
8642 break;
8643 case QUIRK_AE5:
8644 spec->num_outputs = 2;
8645 spec->out_pins[0] = 0x0B; /* Line out */
8646 spec->out_pins[1] = 0x11; /* Rear headphone out */
8647 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8648 spec->out_pins[3] = 0x0F; /* Rear surround */
8649 spec->shared_out_nid = 0x2;
8650 spec->unsol_tag_hp = spec->out_pins[1];
8651 spec->unsol_tag_front_hp = spec->out_pins[2];
8652
8653 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8654 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8655 spec->adcs[2] = 0xa; /* what u hear */
8656
8657 spec->num_inputs = 2;
8658 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8659 spec->input_pins[1] = 0x13; /* What U Hear */
8660 spec->shared_mic_nid = 0x7;
8661 spec->unsol_tag_amic1 = spec->input_pins[0];
8662
8663 /* SPDIF I/O */
8664 spec->dig_out = 0x05;
8665 spec->multiout.dig_out_nid = spec->dig_out;
8666 break;
8667 case QUIRK_R3DI:
8668 spec->num_outputs = 2;
8669 spec->out_pins[0] = 0x0B; /* Line out */
8670 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8671 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8672 spec->out_pins[3] = 0x11; /* Rear surround */
8673 spec->shared_out_nid = 0x2;
8674 spec->unsol_tag_hp = spec->out_pins[1];
8675 spec->unsol_tag_front_hp = spec->out_pins[2];
8676
8677 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
8678 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
8679 spec->adcs[2] = 0x0a; /* what u hear */
8680
8681 spec->num_inputs = 2;
8682 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8683 spec->input_pins[1] = 0x13; /* What U Hear */
8684 spec->shared_mic_nid = 0x7;
8685 spec->unsol_tag_amic1 = spec->input_pins[0];
8686
8687 /* SPDIF I/O */
8688 spec->dig_out = 0x05;
8689 spec->multiout.dig_out_nid = spec->dig_out;
8690 break;
8691 default:
8692 spec->num_outputs = 2;
8693 spec->out_pins[0] = 0x0b; /* speaker out */
8694 spec->out_pins[1] = 0x10; /* headphone out */
8695 spec->shared_out_nid = 0x2;
8696 spec->unsol_tag_hp = spec->out_pins[1];
8697
8698 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8699 spec->adcs[1] = 0x8; /* analog mic2 */
8700 spec->adcs[2] = 0xa; /* what u hear */
8701
8702 spec->num_inputs = 3;
8703 spec->input_pins[0] = 0x12;
8704 spec->input_pins[1] = 0x11;
8705 spec->input_pins[2] = 0x13;
8706 spec->shared_mic_nid = 0x7;
8707 spec->unsol_tag_amic1 = spec->input_pins[0];
8708
8709 /* SPDIF I/O */
8710 spec->dig_out = 0x05;
8711 spec->multiout.dig_out_nid = spec->dig_out;
8712 spec->dig_in = 0x09;
8713 break;
8714 }
8715 }
8716
ca0132_prepare_verbs(struct hda_codec * codec)8717 static int ca0132_prepare_verbs(struct hda_codec *codec)
8718 {
8719 /* Verbs + terminator (an empty element) */
8720 #define NUM_SPEC_VERBS 2
8721 struct ca0132_spec *spec = codec->spec;
8722
8723 spec->chip_init_verbs = ca0132_init_verbs0;
8724 /*
8725 * Since desktop cards use pci_mmio, this can be used to determine
8726 * whether or not to use these verbs instead of a separate bool.
8727 */
8728 if (ca0132_use_pci_mmio(spec))
8729 spec->desktop_init_verbs = ca0132_init_verbs1;
8730 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
8731 sizeof(struct hda_verb),
8732 GFP_KERNEL);
8733 if (!spec->spec_init_verbs)
8734 return -ENOMEM;
8735
8736 /* config EAPD */
8737 spec->spec_init_verbs[0].nid = 0x0b;
8738 spec->spec_init_verbs[0].param = 0x78D;
8739 spec->spec_init_verbs[0].verb = 0x00;
8740
8741 /* Previously commented configuration */
8742 /*
8743 spec->spec_init_verbs[2].nid = 0x0b;
8744 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
8745 spec->spec_init_verbs[2].verb = 0x02;
8746
8747 spec->spec_init_verbs[3].nid = 0x10;
8748 spec->spec_init_verbs[3].param = 0x78D;
8749 spec->spec_init_verbs[3].verb = 0x02;
8750
8751 spec->spec_init_verbs[4].nid = 0x10;
8752 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
8753 spec->spec_init_verbs[4].verb = 0x02;
8754 */
8755
8756 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
8757 return 0;
8758 }
8759
8760 /*
8761 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
8762 * Sound Blaster Z cards. However, they have different HDA codec subsystem
8763 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
8764 * daughter boards ID.
8765 */
sbz_detect_quirk(struct hda_codec * codec)8766 static void sbz_detect_quirk(struct hda_codec *codec)
8767 {
8768 struct ca0132_spec *spec = codec->spec;
8769
8770 switch (codec->core.subsystem_id) {
8771 case 0x11020033:
8772 spec->quirk = QUIRK_ZXR;
8773 break;
8774 case 0x1102003f:
8775 spec->quirk = QUIRK_ZXR_DBPRO;
8776 break;
8777 default:
8778 spec->quirk = QUIRK_SBZ;
8779 break;
8780 }
8781 }
8782
patch_ca0132(struct hda_codec * codec)8783 static int patch_ca0132(struct hda_codec *codec)
8784 {
8785 struct ca0132_spec *spec;
8786 int err;
8787 const struct snd_pci_quirk *quirk;
8788
8789 codec_dbg(codec, "patch_ca0132\n");
8790
8791 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
8792 if (!spec)
8793 return -ENOMEM;
8794 codec->spec = spec;
8795 spec->codec = codec;
8796
8797 /* Detect codec quirk */
8798 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
8799 if (quirk)
8800 spec->quirk = quirk->value;
8801 else
8802 spec->quirk = QUIRK_NONE;
8803 if (ca0132_quirk(spec) == QUIRK_SBZ)
8804 sbz_detect_quirk(codec);
8805
8806 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
8807 codec->patch_ops = dbpro_patch_ops;
8808 else
8809 codec->patch_ops = ca0132_patch_ops;
8810
8811 codec->pcm_format_first = 1;
8812 codec->no_sticky_stream = 1;
8813
8814
8815 spec->dsp_state = DSP_DOWNLOAD_INIT;
8816 spec->num_mixers = 1;
8817
8818 /* Set which mixers each quirk uses. */
8819 switch (ca0132_quirk(spec)) {
8820 case QUIRK_SBZ:
8821 spec->mixers[0] = desktop_mixer;
8822 snd_hda_codec_set_name(codec, "Sound Blaster Z");
8823 break;
8824 case QUIRK_ZXR:
8825 spec->mixers[0] = desktop_mixer;
8826 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
8827 break;
8828 case QUIRK_ZXR_DBPRO:
8829 break;
8830 case QUIRK_R3D:
8831 spec->mixers[0] = desktop_mixer;
8832 snd_hda_codec_set_name(codec, "Recon3D");
8833 break;
8834 case QUIRK_R3DI:
8835 spec->mixers[0] = r3di_mixer;
8836 snd_hda_codec_set_name(codec, "Recon3Di");
8837 break;
8838 case QUIRK_AE5:
8839 spec->mixers[0] = desktop_mixer;
8840 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
8841 break;
8842 default:
8843 spec->mixers[0] = ca0132_mixer;
8844 break;
8845 }
8846
8847 /* Setup whether or not to use alt functions/controls/pci_mmio */
8848 switch (ca0132_quirk(spec)) {
8849 case QUIRK_SBZ:
8850 case QUIRK_R3D:
8851 case QUIRK_AE5:
8852 case QUIRK_ZXR:
8853 spec->use_alt_controls = true;
8854 spec->use_alt_functions = true;
8855 spec->use_pci_mmio = true;
8856 break;
8857 case QUIRK_R3DI:
8858 spec->use_alt_controls = true;
8859 spec->use_alt_functions = true;
8860 spec->use_pci_mmio = false;
8861 break;
8862 default:
8863 spec->use_alt_controls = false;
8864 spec->use_alt_functions = false;
8865 spec->use_pci_mmio = false;
8866 break;
8867 }
8868
8869 #ifdef CONFIG_PCI
8870 if (spec->use_pci_mmio) {
8871 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
8872 if (spec->mem_base == NULL) {
8873 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
8874 spec->quirk = QUIRK_NONE;
8875 }
8876 }
8877 #endif
8878
8879 spec->base_init_verbs = ca0132_base_init_verbs;
8880 spec->base_exit_verbs = ca0132_base_exit_verbs;
8881
8882 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
8883
8884 ca0132_init_chip(codec);
8885
8886 ca0132_config(codec);
8887
8888 err = ca0132_prepare_verbs(codec);
8889 if (err < 0)
8890 goto error;
8891
8892 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
8893 if (err < 0)
8894 goto error;
8895
8896 return 0;
8897
8898 error:
8899 ca0132_free(codec);
8900 return err;
8901 }
8902
8903 /*
8904 * patch entries
8905 */
8906 static struct hda_device_id snd_hda_id_ca0132[] = {
8907 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
8908 {} /* terminator */
8909 };
8910 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
8911
8912 MODULE_LICENSE("GPL");
8913 MODULE_DESCRIPTION("Creative Sound Core3D codec");
8914
8915 static struct hda_codec_driver ca0132_driver = {
8916 .id = snd_hda_id_ca0132,
8917 };
8918
8919 module_hda_codec_driver(ca0132_driver);
8920