• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * cs42l51.c
4  *
5  * ASoC Driver for Cirrus Logic CS42L51 codecs
6  *
7  * Copyright (c) 2010 Arnaud Patard <apatard@mandriva.com>
8  *
9  * Based on cs4270.c - Copyright (c) Freescale Semiconductor
10  *
11  * For now:
12  *  - Only I2C is support. Not SPI
13  *  - master mode *NOT* supported
14  */
15 
16 #include <linux/clk.h>
17 #include <linux/module.h>
18 #include <linux/slab.h>
19 #include <sound/core.h>
20 #include <sound/soc.h>
21 #include <sound/tlv.h>
22 #include <sound/initval.h>
23 #include <sound/pcm_params.h>
24 #include <sound/pcm.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
28 
29 #include "cs42l51.h"
30 
31 enum master_slave_mode {
32 	MODE_SLAVE,
33 	MODE_SLAVE_AUTO,
34 	MODE_MASTER,
35 };
36 
37 static const char * const cs42l51_supply_names[] = {
38 	"VL",
39 	"VD",
40 	"VA",
41 	"VAHP",
42 };
43 
44 struct cs42l51_private {
45 	unsigned int mclk;
46 	struct clk *mclk_handle;
47 	unsigned int audio_mode;	/* The mode (I2S or left-justified) */
48 	enum master_slave_mode func;
49 	struct regulator_bulk_data supplies[ARRAY_SIZE(cs42l51_supply_names)];
50 	struct gpio_desc *reset_gpio;
51 	struct regmap *regmap;
52 };
53 
54 #define CS42L51_FORMATS ( \
55 		SNDRV_PCM_FMTBIT_S16_LE  | SNDRV_PCM_FMTBIT_S16_BE  | \
56 		SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \
57 		SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \
58 		SNDRV_PCM_FMTBIT_S24_LE  | SNDRV_PCM_FMTBIT_S24_BE)
59 
cs42l51_get_chan_mix(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)60 static int cs42l51_get_chan_mix(struct snd_kcontrol *kcontrol,
61 			struct snd_ctl_elem_value *ucontrol)
62 {
63 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
64 	unsigned long value = snd_soc_component_read32(component, CS42L51_PCM_MIXER)&3;
65 
66 	switch (value) {
67 	default:
68 	case 0:
69 		ucontrol->value.enumerated.item[0] = 0;
70 		break;
71 	/* same value : (L+R)/2 and (R+L)/2 */
72 	case 1:
73 	case 2:
74 		ucontrol->value.enumerated.item[0] = 1;
75 		break;
76 	case 3:
77 		ucontrol->value.enumerated.item[0] = 2;
78 		break;
79 	}
80 
81 	return 0;
82 }
83 
84 #define CHAN_MIX_NORMAL	0x00
85 #define CHAN_MIX_BOTH	0x55
86 #define CHAN_MIX_SWAP	0xFF
87 
cs42l51_set_chan_mix(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)88 static int cs42l51_set_chan_mix(struct snd_kcontrol *kcontrol,
89 			struct snd_ctl_elem_value *ucontrol)
90 {
91 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
92 	unsigned char val;
93 
94 	switch (ucontrol->value.enumerated.item[0]) {
95 	default:
96 	case 0:
97 		val = CHAN_MIX_NORMAL;
98 		break;
99 	case 1:
100 		val = CHAN_MIX_BOTH;
101 		break;
102 	case 2:
103 		val = CHAN_MIX_SWAP;
104 		break;
105 	}
106 
107 	snd_soc_component_write(component, CS42L51_PCM_MIXER, val);
108 
109 	return 1;
110 }
111 
112 static const DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -5150, 50, 0);
113 static const DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 150, 0);
114 
115 static const DECLARE_TLV_DB_SCALE(aout_tlv, -10200, 50, 0);
116 
117 static const DECLARE_TLV_DB_SCALE(boost_tlv, 1600, 1600, 0);
118 static const DECLARE_TLV_DB_SCALE(adc_boost_tlv, 2000, 2000, 0);
119 static const char *chan_mix[] = {
120 	"L R",
121 	"L+R",
122 	"R L",
123 };
124 
125 static SOC_ENUM_SINGLE_EXT_DECL(cs42l51_chan_mix, chan_mix);
126 
127 static const struct snd_kcontrol_new cs42l51_snd_controls[] = {
128 	SOC_DOUBLE_R_SX_TLV("PCM Playback Volume",
129 			CS42L51_PCMA_VOL, CS42L51_PCMB_VOL,
130 			0, 0x19, 0x7F, adc_pcm_tlv),
131 	SOC_DOUBLE_R("PCM Playback Switch",
132 			CS42L51_PCMA_VOL, CS42L51_PCMB_VOL, 7, 1, 1),
133 	SOC_DOUBLE_R_SX_TLV("Analog Playback Volume",
134 			CS42L51_AOUTA_VOL, CS42L51_AOUTB_VOL,
135 			0, 0x34, 0xE4, aout_tlv),
136 	SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
137 			CS42L51_ADCA_VOL, CS42L51_ADCB_VOL,
138 			0, 0x19, 0x7F, adc_pcm_tlv),
139 	SOC_DOUBLE_R("ADC Mixer Switch",
140 			CS42L51_ADCA_VOL, CS42L51_ADCB_VOL, 7, 1, 1),
141 	SOC_SINGLE("Playback Deemphasis Switch", CS42L51_DAC_CTL, 3, 1, 0),
142 	SOC_SINGLE("Auto-Mute Switch", CS42L51_DAC_CTL, 2, 1, 0),
143 	SOC_SINGLE("Soft Ramp Switch", CS42L51_DAC_CTL, 1, 1, 0),
144 	SOC_SINGLE("Zero Cross Switch", CS42L51_DAC_CTL, 0, 0, 0),
145 	SOC_DOUBLE_TLV("Mic Boost Volume",
146 			CS42L51_MIC_CTL, 0, 1, 1, 0, boost_tlv),
147 	SOC_DOUBLE_TLV("ADC Boost Volume",
148 		       CS42L51_MIC_CTL, 5, 6, 1, 0, adc_boost_tlv),
149 	SOC_SINGLE_TLV("Bass Volume", CS42L51_TONE_CTL, 0, 0xf, 1, tone_tlv),
150 	SOC_SINGLE_TLV("Treble Volume", CS42L51_TONE_CTL, 4, 0xf, 1, tone_tlv),
151 	SOC_ENUM_EXT("PCM channel mixer",
152 			cs42l51_chan_mix,
153 			cs42l51_get_chan_mix, cs42l51_set_chan_mix),
154 };
155 
156 /*
157  * to power down, one must:
158  * 1.) Enable the PDN bit
159  * 2.) enable power-down for the select channels
160  * 3.) disable the PDN bit.
161  */
cs42l51_pdn_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)162 static int cs42l51_pdn_event(struct snd_soc_dapm_widget *w,
163 		struct snd_kcontrol *kcontrol, int event)
164 {
165 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
166 
167 	switch (event) {
168 	case SND_SOC_DAPM_PRE_PMD:
169 		snd_soc_component_update_bits(component, CS42L51_POWER_CTL1,
170 				    CS42L51_POWER_CTL1_PDN,
171 				    CS42L51_POWER_CTL1_PDN);
172 		break;
173 	default:
174 	case SND_SOC_DAPM_POST_PMD:
175 		snd_soc_component_update_bits(component, CS42L51_POWER_CTL1,
176 				    CS42L51_POWER_CTL1_PDN, 0);
177 		break;
178 	}
179 
180 	return 0;
181 }
182 
183 static const char *cs42l51_dac_names[] = {"Direct PCM",
184 	"DSP PCM", "ADC"};
185 static SOC_ENUM_SINGLE_DECL(cs42l51_dac_mux_enum,
186 			    CS42L51_DAC_CTL, 6, cs42l51_dac_names);
187 static const struct snd_kcontrol_new cs42l51_dac_mux_controls =
188 	SOC_DAPM_ENUM("Route", cs42l51_dac_mux_enum);
189 
190 static const char *cs42l51_adcl_names[] = {"AIN1 Left", "AIN2 Left",
191 	"MIC Left", "MIC+preamp Left"};
192 static SOC_ENUM_SINGLE_DECL(cs42l51_adcl_mux_enum,
193 			    CS42L51_ADC_INPUT, 4, cs42l51_adcl_names);
194 static const struct snd_kcontrol_new cs42l51_adcl_mux_controls =
195 	SOC_DAPM_ENUM("Route", cs42l51_adcl_mux_enum);
196 
197 static const char *cs42l51_adcr_names[] = {"AIN1 Right", "AIN2 Right",
198 	"MIC Right", "MIC+preamp Right"};
199 static SOC_ENUM_SINGLE_DECL(cs42l51_adcr_mux_enum,
200 			    CS42L51_ADC_INPUT, 6, cs42l51_adcr_names);
201 static const struct snd_kcontrol_new cs42l51_adcr_mux_controls =
202 	SOC_DAPM_ENUM("Route", cs42l51_adcr_mux_enum);
203 
204 static const struct snd_soc_dapm_widget cs42l51_dapm_widgets[] = {
205 	SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L51_MIC_POWER_CTL, 1, 1, NULL,
206 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
207 	SND_SOC_DAPM_PGA_E("Left PGA", CS42L51_POWER_CTL1, 3, 1, NULL, 0,
208 		cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
209 	SND_SOC_DAPM_PGA_E("Right PGA", CS42L51_POWER_CTL1, 4, 1, NULL, 0,
210 		cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
211 	SND_SOC_DAPM_ADC_E("Left ADC", "Left HiFi Capture",
212 		CS42L51_POWER_CTL1, 1, 1,
213 		cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
214 	SND_SOC_DAPM_ADC_E("Right ADC", "Right HiFi Capture",
215 		CS42L51_POWER_CTL1, 2, 1,
216 		cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
217 	SND_SOC_DAPM_DAC_E("Left DAC", "Left HiFi Playback",
218 		CS42L51_POWER_CTL1, 5, 1,
219 		cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
220 	SND_SOC_DAPM_DAC_E("Right DAC", "Right HiFi Playback",
221 		CS42L51_POWER_CTL1, 6, 1,
222 		cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
223 
224 	/* analog/mic */
225 	SND_SOC_DAPM_INPUT("AIN1L"),
226 	SND_SOC_DAPM_INPUT("AIN1R"),
227 	SND_SOC_DAPM_INPUT("AIN2L"),
228 	SND_SOC_DAPM_INPUT("AIN2R"),
229 	SND_SOC_DAPM_INPUT("MICL"),
230 	SND_SOC_DAPM_INPUT("MICR"),
231 
232 	SND_SOC_DAPM_MIXER("Mic Preamp Left",
233 		CS42L51_MIC_POWER_CTL, 2, 1, NULL, 0),
234 	SND_SOC_DAPM_MIXER("Mic Preamp Right",
235 		CS42L51_MIC_POWER_CTL, 3, 1, NULL, 0),
236 
237 	/* HP */
238 	SND_SOC_DAPM_OUTPUT("HPL"),
239 	SND_SOC_DAPM_OUTPUT("HPR"),
240 
241 	/* mux */
242 	SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
243 		&cs42l51_dac_mux_controls),
244 	SND_SOC_DAPM_MUX("PGA-ADC Mux Left", SND_SOC_NOPM, 0, 0,
245 		&cs42l51_adcl_mux_controls),
246 	SND_SOC_DAPM_MUX("PGA-ADC Mux Right", SND_SOC_NOPM, 0, 0,
247 		&cs42l51_adcr_mux_controls),
248 };
249 
mclk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)250 static int mclk_event(struct snd_soc_dapm_widget *w,
251 		      struct snd_kcontrol *kcontrol, int event)
252 {
253 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
254 	struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(comp);
255 
256 	switch (event) {
257 	case SND_SOC_DAPM_PRE_PMU:
258 		return clk_prepare_enable(cs42l51->mclk_handle);
259 	case SND_SOC_DAPM_POST_PMD:
260 		/* Delay mclk shutdown to fulfill power-down sequence requirements */
261 		msleep(20);
262 		clk_disable_unprepare(cs42l51->mclk_handle);
263 		break;
264 	}
265 
266 	return 0;
267 }
268 
269 static const struct snd_soc_dapm_widget cs42l51_dapm_mclk_widgets[] = {
270 	SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, mclk_event,
271 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
272 };
273 
274 static const struct snd_soc_dapm_route cs42l51_routes[] = {
275 	{"HPL", NULL, "Left DAC"},
276 	{"HPR", NULL, "Right DAC"},
277 
278 	{"Left ADC", NULL, "Left PGA"},
279 	{"Right ADC", NULL, "Right PGA"},
280 
281 	{"Mic Preamp Left",  NULL,  "MICL"},
282 	{"Mic Preamp Right", NULL,  "MICR"},
283 
284 	{"PGA-ADC Mux Left",  "AIN1 Left",        "AIN1L" },
285 	{"PGA-ADC Mux Left",  "AIN2 Left",        "AIN2L" },
286 	{"PGA-ADC Mux Left",  "MIC Left",         "MICL"  },
287 	{"PGA-ADC Mux Left",  "MIC+preamp Left",  "Mic Preamp Left" },
288 	{"PGA-ADC Mux Right", "AIN1 Right",       "AIN1R" },
289 	{"PGA-ADC Mux Right", "AIN2 Right",       "AIN2R" },
290 	{"PGA-ADC Mux Right", "MIC Right",        "MICR" },
291 	{"PGA-ADC Mux Right", "MIC+preamp Right", "Mic Preamp Right" },
292 
293 	{"Left PGA", NULL, "PGA-ADC Mux Left"},
294 	{"Right PGA", NULL, "PGA-ADC Mux Right"},
295 };
296 
cs42l51_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int format)297 static int cs42l51_set_dai_fmt(struct snd_soc_dai *codec_dai,
298 		unsigned int format)
299 {
300 	struct snd_soc_component *component = codec_dai->component;
301 	struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
302 
303 	switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
304 	case SND_SOC_DAIFMT_I2S:
305 	case SND_SOC_DAIFMT_LEFT_J:
306 	case SND_SOC_DAIFMT_RIGHT_J:
307 		cs42l51->audio_mode = format & SND_SOC_DAIFMT_FORMAT_MASK;
308 		break;
309 	default:
310 		dev_err(component->dev, "invalid DAI format\n");
311 		return -EINVAL;
312 	}
313 
314 	switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
315 	case SND_SOC_DAIFMT_CBM_CFM:
316 		cs42l51->func = MODE_MASTER;
317 		break;
318 	case SND_SOC_DAIFMT_CBS_CFS:
319 		cs42l51->func = MODE_SLAVE_AUTO;
320 		break;
321 	default:
322 		dev_err(component->dev, "Unknown master/slave configuration\n");
323 		return -EINVAL;
324 	}
325 
326 	return 0;
327 }
328 
329 struct cs42l51_ratios {
330 	unsigned int ratio;
331 	unsigned char speed_mode;
332 	unsigned char mclk;
333 };
334 
335 static struct cs42l51_ratios slave_ratios[] = {
336 	{  512, CS42L51_QSM_MODE, 0 }, {  768, CS42L51_QSM_MODE, 0 },
337 	{ 1024, CS42L51_QSM_MODE, 0 }, { 1536, CS42L51_QSM_MODE, 0 },
338 	{ 2048, CS42L51_QSM_MODE, 0 }, { 3072, CS42L51_QSM_MODE, 0 },
339 	{  256, CS42L51_HSM_MODE, 0 }, {  384, CS42L51_HSM_MODE, 0 },
340 	{  512, CS42L51_HSM_MODE, 0 }, {  768, CS42L51_HSM_MODE, 0 },
341 	{ 1024, CS42L51_HSM_MODE, 0 }, { 1536, CS42L51_HSM_MODE, 0 },
342 	{  128, CS42L51_SSM_MODE, 0 }, {  192, CS42L51_SSM_MODE, 0 },
343 	{  256, CS42L51_SSM_MODE, 0 }, {  384, CS42L51_SSM_MODE, 0 },
344 	{  512, CS42L51_SSM_MODE, 0 }, {  768, CS42L51_SSM_MODE, 0 },
345 	{  128, CS42L51_DSM_MODE, 0 }, {  192, CS42L51_DSM_MODE, 0 },
346 	{  256, CS42L51_DSM_MODE, 0 }, {  384, CS42L51_DSM_MODE, 0 },
347 };
348 
349 static struct cs42l51_ratios slave_auto_ratios[] = {
350 	{ 1024, CS42L51_QSM_MODE, 0 }, { 1536, CS42L51_QSM_MODE, 0 },
351 	{ 2048, CS42L51_QSM_MODE, 1 }, { 3072, CS42L51_QSM_MODE, 1 },
352 	{  512, CS42L51_HSM_MODE, 0 }, {  768, CS42L51_HSM_MODE, 0 },
353 	{ 1024, CS42L51_HSM_MODE, 1 }, { 1536, CS42L51_HSM_MODE, 1 },
354 	{  256, CS42L51_SSM_MODE, 0 }, {  384, CS42L51_SSM_MODE, 0 },
355 	{  512, CS42L51_SSM_MODE, 1 }, {  768, CS42L51_SSM_MODE, 1 },
356 	{  128, CS42L51_DSM_MODE, 0 }, {  192, CS42L51_DSM_MODE, 0 },
357 	{  256, CS42L51_DSM_MODE, 1 }, {  384, CS42L51_DSM_MODE, 1 },
358 };
359 
360 /*
361  * Master mode mclk/fs ratios.
362  * Recommended configurations are SSM for 4-50khz and DSM for 50-100kHz ranges
363  * The table below provides support of following ratios:
364  * 128: SSM (%128) with div2 disabled
365  * 256: SSM (%128) with div2 enabled
366  * In both cases, if sampling rate is above 50kHz, SSM is overridden
367  * with DSM (%128) configuration
368  */
369 static struct cs42l51_ratios master_ratios[] = {
370 	{ 128, CS42L51_SSM_MODE, 0 }, { 256, CS42L51_SSM_MODE, 1 },
371 };
372 
cs42l51_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)373 static int cs42l51_set_dai_sysclk(struct snd_soc_dai *codec_dai,
374 		int clk_id, unsigned int freq, int dir)
375 {
376 	struct snd_soc_component *component = codec_dai->component;
377 	struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
378 
379 	cs42l51->mclk = freq;
380 	return 0;
381 }
382 
cs42l51_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)383 static int cs42l51_hw_params(struct snd_pcm_substream *substream,
384 		struct snd_pcm_hw_params *params,
385 		struct snd_soc_dai *dai)
386 {
387 	struct snd_soc_component *component = dai->component;
388 	struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
389 	int ret;
390 	unsigned int i;
391 	unsigned int rate;
392 	unsigned int ratio;
393 	struct cs42l51_ratios *ratios = NULL;
394 	int nr_ratios = 0;
395 	int intf_ctl, power_ctl, fmt, mode;
396 
397 	switch (cs42l51->func) {
398 	case MODE_MASTER:
399 		ratios = master_ratios;
400 		nr_ratios = ARRAY_SIZE(master_ratios);
401 		break;
402 	case MODE_SLAVE:
403 		ratios = slave_ratios;
404 		nr_ratios = ARRAY_SIZE(slave_ratios);
405 		break;
406 	case MODE_SLAVE_AUTO:
407 		ratios = slave_auto_ratios;
408 		nr_ratios = ARRAY_SIZE(slave_auto_ratios);
409 		break;
410 	}
411 
412 	/* Figure out which MCLK/LRCK ratio to use */
413 	rate = params_rate(params);     /* Sampling rate, in Hz */
414 	ratio = cs42l51->mclk / rate;    /* MCLK/LRCK ratio */
415 	for (i = 0; i < nr_ratios; i++) {
416 		if (ratios[i].ratio == ratio)
417 			break;
418 	}
419 
420 	if (i == nr_ratios) {
421 		/* We did not find a matching ratio */
422 		dev_err(component->dev, "could not find matching ratio\n");
423 		return -EINVAL;
424 	}
425 
426 	intf_ctl = snd_soc_component_read32(component, CS42L51_INTF_CTL);
427 	power_ctl = snd_soc_component_read32(component, CS42L51_MIC_POWER_CTL);
428 
429 	intf_ctl &= ~(CS42L51_INTF_CTL_MASTER | CS42L51_INTF_CTL_ADC_I2S
430 			| CS42L51_INTF_CTL_DAC_FORMAT(7));
431 	power_ctl &= ~(CS42L51_MIC_POWER_CTL_SPEED(3)
432 			| CS42L51_MIC_POWER_CTL_MCLK_DIV2);
433 
434 	switch (cs42l51->func) {
435 	case MODE_MASTER:
436 		intf_ctl |= CS42L51_INTF_CTL_MASTER;
437 		mode = ratios[i].speed_mode;
438 		/* Force DSM mode if sampling rate is above 50kHz */
439 		if (rate > 50000)
440 			mode = CS42L51_DSM_MODE;
441 		power_ctl |= CS42L51_MIC_POWER_CTL_SPEED(mode);
442 		/*
443 		 * Auto detect mode is not applicable for master mode and has to
444 		 * be disabled. Otherwise SPEED[1:0] bits will be ignored.
445 		 */
446 		power_ctl &= ~CS42L51_MIC_POWER_CTL_AUTO;
447 		break;
448 	case MODE_SLAVE:
449 		power_ctl |= CS42L51_MIC_POWER_CTL_SPEED(ratios[i].speed_mode);
450 		break;
451 	case MODE_SLAVE_AUTO:
452 		power_ctl |= CS42L51_MIC_POWER_CTL_AUTO;
453 		break;
454 	}
455 
456 	switch (cs42l51->audio_mode) {
457 	case SND_SOC_DAIFMT_I2S:
458 		intf_ctl |= CS42L51_INTF_CTL_ADC_I2S;
459 		intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(CS42L51_DAC_DIF_I2S);
460 		break;
461 	case SND_SOC_DAIFMT_LEFT_J:
462 		intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(CS42L51_DAC_DIF_LJ24);
463 		break;
464 	case SND_SOC_DAIFMT_RIGHT_J:
465 		switch (params_width(params)) {
466 		case 16:
467 			fmt = CS42L51_DAC_DIF_RJ16;
468 			break;
469 		case 18:
470 			fmt = CS42L51_DAC_DIF_RJ18;
471 			break;
472 		case 20:
473 			fmt = CS42L51_DAC_DIF_RJ20;
474 			break;
475 		case 24:
476 			fmt = CS42L51_DAC_DIF_RJ24;
477 			break;
478 		default:
479 			dev_err(component->dev, "unknown format\n");
480 			return -EINVAL;
481 		}
482 		intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(fmt);
483 		break;
484 	default:
485 		dev_err(component->dev, "unknown format\n");
486 		return -EINVAL;
487 	}
488 
489 	if (ratios[i].mclk)
490 		power_ctl |= CS42L51_MIC_POWER_CTL_MCLK_DIV2;
491 
492 	ret = snd_soc_component_write(component, CS42L51_INTF_CTL, intf_ctl);
493 	if (ret < 0)
494 		return ret;
495 
496 	ret = snd_soc_component_write(component, CS42L51_MIC_POWER_CTL, power_ctl);
497 	if (ret < 0)
498 		return ret;
499 
500 	return 0;
501 }
502 
cs42l51_dai_mute(struct snd_soc_dai * dai,int mute)503 static int cs42l51_dai_mute(struct snd_soc_dai *dai, int mute)
504 {
505 	struct snd_soc_component *component = dai->component;
506 	int reg;
507 	int mask = CS42L51_DAC_OUT_CTL_DACA_MUTE|CS42L51_DAC_OUT_CTL_DACB_MUTE;
508 
509 	reg = snd_soc_component_read32(component, CS42L51_DAC_OUT_CTL);
510 
511 	if (mute)
512 		reg |= mask;
513 	else
514 		reg &= ~mask;
515 
516 	return snd_soc_component_write(component, CS42L51_DAC_OUT_CTL, reg);
517 }
518 
cs42l51_of_xlate_dai_id(struct snd_soc_component * component,struct device_node * endpoint)519 static int cs42l51_of_xlate_dai_id(struct snd_soc_component *component,
520 				   struct device_node *endpoint)
521 {
522 	/* return dai id 0, whatever the endpoint index */
523 	return 0;
524 }
525 
526 static const struct snd_soc_dai_ops cs42l51_dai_ops = {
527 	.hw_params      = cs42l51_hw_params,
528 	.set_sysclk     = cs42l51_set_dai_sysclk,
529 	.set_fmt        = cs42l51_set_dai_fmt,
530 	.digital_mute   = cs42l51_dai_mute,
531 };
532 
533 static struct snd_soc_dai_driver cs42l51_dai = {
534 	.name = "cs42l51-hifi",
535 	.playback = {
536 		.stream_name = "Playback",
537 		.channels_min = 1,
538 		.channels_max = 2,
539 		.rates = SNDRV_PCM_RATE_8000_96000,
540 		.formats = CS42L51_FORMATS,
541 	},
542 	.capture = {
543 		.stream_name = "Capture",
544 		.channels_min = 1,
545 		.channels_max = 2,
546 		.rates = SNDRV_PCM_RATE_8000_96000,
547 		.formats = CS42L51_FORMATS,
548 	},
549 	.ops = &cs42l51_dai_ops,
550 };
551 
cs42l51_component_probe(struct snd_soc_component * component)552 static int cs42l51_component_probe(struct snd_soc_component *component)
553 {
554 	int ret, reg;
555 	struct snd_soc_dapm_context *dapm;
556 	struct cs42l51_private *cs42l51;
557 
558 	cs42l51 = snd_soc_component_get_drvdata(component);
559 	dapm = snd_soc_component_get_dapm(component);
560 
561 	if (cs42l51->mclk_handle)
562 		snd_soc_dapm_new_controls(dapm, cs42l51_dapm_mclk_widgets, 1);
563 
564 	/*
565 	 * DAC configuration
566 	 * - Use signal processor
567 	 * - auto mute
568 	 * - vol changes immediate
569 	 * - no de-emphasize
570 	 */
571 	reg = CS42L51_DAC_CTL_DATA_SEL(1)
572 		| CS42L51_DAC_CTL_AMUTE | CS42L51_DAC_CTL_DACSZ(0);
573 	ret = snd_soc_component_write(component, CS42L51_DAC_CTL, reg);
574 	if (ret < 0)
575 		return ret;
576 
577 	return 0;
578 }
579 
580 static const struct snd_soc_component_driver soc_component_device_cs42l51 = {
581 	.probe			= cs42l51_component_probe,
582 	.controls		= cs42l51_snd_controls,
583 	.num_controls		= ARRAY_SIZE(cs42l51_snd_controls),
584 	.dapm_widgets		= cs42l51_dapm_widgets,
585 	.num_dapm_widgets	= ARRAY_SIZE(cs42l51_dapm_widgets),
586 	.dapm_routes		= cs42l51_routes,
587 	.num_dapm_routes	= ARRAY_SIZE(cs42l51_routes),
588 	.of_xlate_dai_id	= cs42l51_of_xlate_dai_id,
589 	.idle_bias_on		= 1,
590 	.use_pmdown_time	= 1,
591 	.endianness		= 1,
592 	.non_legacy_dai_naming	= 1,
593 };
594 
cs42l51_writeable_reg(struct device * dev,unsigned int reg)595 static bool cs42l51_writeable_reg(struct device *dev, unsigned int reg)
596 {
597 	switch (reg) {
598 	case CS42L51_POWER_CTL1:
599 	case CS42L51_MIC_POWER_CTL:
600 	case CS42L51_INTF_CTL:
601 	case CS42L51_MIC_CTL:
602 	case CS42L51_ADC_CTL:
603 	case CS42L51_ADC_INPUT:
604 	case CS42L51_DAC_OUT_CTL:
605 	case CS42L51_DAC_CTL:
606 	case CS42L51_ALC_PGA_CTL:
607 	case CS42L51_ALC_PGB_CTL:
608 	case CS42L51_ADCA_ATT:
609 	case CS42L51_ADCB_ATT:
610 	case CS42L51_ADCA_VOL:
611 	case CS42L51_ADCB_VOL:
612 	case CS42L51_PCMA_VOL:
613 	case CS42L51_PCMB_VOL:
614 	case CS42L51_BEEP_FREQ:
615 	case CS42L51_BEEP_VOL:
616 	case CS42L51_BEEP_CONF:
617 	case CS42L51_TONE_CTL:
618 	case CS42L51_AOUTA_VOL:
619 	case CS42L51_AOUTB_VOL:
620 	case CS42L51_PCM_MIXER:
621 	case CS42L51_LIMIT_THRES_DIS:
622 	case CS42L51_LIMIT_REL:
623 	case CS42L51_LIMIT_ATT:
624 	case CS42L51_ALC_EN:
625 	case CS42L51_ALC_REL:
626 	case CS42L51_ALC_THRES:
627 	case CS42L51_NOISE_CONF:
628 	case CS42L51_CHARGE_FREQ:
629 		return true;
630 	default:
631 		return false;
632 	}
633 }
634 
cs42l51_volatile_reg(struct device * dev,unsigned int reg)635 static bool cs42l51_volatile_reg(struct device *dev, unsigned int reg)
636 {
637 	switch (reg) {
638 	case CS42L51_STATUS:
639 		return true;
640 	default:
641 		return false;
642 	}
643 }
644 
cs42l51_readable_reg(struct device * dev,unsigned int reg)645 static bool cs42l51_readable_reg(struct device *dev, unsigned int reg)
646 {
647 	switch (reg) {
648 	case CS42L51_CHIP_REV_ID:
649 	case CS42L51_POWER_CTL1:
650 	case CS42L51_MIC_POWER_CTL:
651 	case CS42L51_INTF_CTL:
652 	case CS42L51_MIC_CTL:
653 	case CS42L51_ADC_CTL:
654 	case CS42L51_ADC_INPUT:
655 	case CS42L51_DAC_OUT_CTL:
656 	case CS42L51_DAC_CTL:
657 	case CS42L51_ALC_PGA_CTL:
658 	case CS42L51_ALC_PGB_CTL:
659 	case CS42L51_ADCA_ATT:
660 	case CS42L51_ADCB_ATT:
661 	case CS42L51_ADCA_VOL:
662 	case CS42L51_ADCB_VOL:
663 	case CS42L51_PCMA_VOL:
664 	case CS42L51_PCMB_VOL:
665 	case CS42L51_BEEP_FREQ:
666 	case CS42L51_BEEP_VOL:
667 	case CS42L51_BEEP_CONF:
668 	case CS42L51_TONE_CTL:
669 	case CS42L51_AOUTA_VOL:
670 	case CS42L51_AOUTB_VOL:
671 	case CS42L51_PCM_MIXER:
672 	case CS42L51_LIMIT_THRES_DIS:
673 	case CS42L51_LIMIT_REL:
674 	case CS42L51_LIMIT_ATT:
675 	case CS42L51_ALC_EN:
676 	case CS42L51_ALC_REL:
677 	case CS42L51_ALC_THRES:
678 	case CS42L51_NOISE_CONF:
679 	case CS42L51_STATUS:
680 	case CS42L51_CHARGE_FREQ:
681 		return true;
682 	default:
683 		return false;
684 	}
685 }
686 
687 const struct regmap_config cs42l51_regmap = {
688 	.reg_bits = 8,
689 	.reg_stride = 1,
690 	.val_bits = 8,
691 	.use_single_write = true,
692 	.readable_reg = cs42l51_readable_reg,
693 	.volatile_reg = cs42l51_volatile_reg,
694 	.writeable_reg = cs42l51_writeable_reg,
695 	.max_register = CS42L51_CHARGE_FREQ,
696 	.cache_type = REGCACHE_RBTREE,
697 };
698 EXPORT_SYMBOL_GPL(cs42l51_regmap);
699 
cs42l51_probe(struct device * dev,struct regmap * regmap)700 int cs42l51_probe(struct device *dev, struct regmap *regmap)
701 {
702 	struct cs42l51_private *cs42l51;
703 	unsigned int val;
704 	int ret, i;
705 
706 	if (IS_ERR(regmap))
707 		return PTR_ERR(regmap);
708 
709 	cs42l51 = devm_kzalloc(dev, sizeof(struct cs42l51_private),
710 			       GFP_KERNEL);
711 	if (!cs42l51)
712 		return -ENOMEM;
713 
714 	dev_set_drvdata(dev, cs42l51);
715 	cs42l51->regmap = regmap;
716 
717 	cs42l51->mclk_handle = devm_clk_get(dev, "MCLK");
718 	if (IS_ERR(cs42l51->mclk_handle)) {
719 		if (PTR_ERR(cs42l51->mclk_handle) != -ENOENT)
720 			return PTR_ERR(cs42l51->mclk_handle);
721 		cs42l51->mclk_handle = NULL;
722 	}
723 
724 	for (i = 0; i < ARRAY_SIZE(cs42l51->supplies); i++)
725 		cs42l51->supplies[i].supply = cs42l51_supply_names[i];
726 
727 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs42l51->supplies),
728 				      cs42l51->supplies);
729 	if (ret != 0) {
730 		dev_err(dev, "Failed to request supplies: %d\n", ret);
731 		return ret;
732 	}
733 
734 	ret = regulator_bulk_enable(ARRAY_SIZE(cs42l51->supplies),
735 				    cs42l51->supplies);
736 	if (ret != 0) {
737 		dev_err(dev, "Failed to enable supplies: %d\n", ret);
738 		return ret;
739 	}
740 
741 	cs42l51->reset_gpio = devm_gpiod_get_optional(dev, "reset",
742 						      GPIOD_OUT_LOW);
743 	if (IS_ERR(cs42l51->reset_gpio))
744 		return PTR_ERR(cs42l51->reset_gpio);
745 
746 	if (cs42l51->reset_gpio) {
747 		dev_dbg(dev, "Release reset gpio\n");
748 		gpiod_set_value_cansleep(cs42l51->reset_gpio, 0);
749 		mdelay(2);
750 	}
751 
752 	/* Verify that we have a CS42L51 */
753 	ret = regmap_read(regmap, CS42L51_CHIP_REV_ID, &val);
754 	if (ret < 0) {
755 		dev_err(dev, "failed to read I2C\n");
756 		goto error;
757 	}
758 
759 	if ((val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) &&
760 	    (val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) {
761 		dev_err(dev, "Invalid chip id: %x\n", val);
762 		ret = -ENODEV;
763 		goto error;
764 	}
765 	dev_info(dev, "Cirrus Logic CS42L51, Revision: %02X\n",
766 		 val & CS42L51_CHIP_REV_MASK);
767 
768 	ret = devm_snd_soc_register_component(dev,
769 			&soc_component_device_cs42l51, &cs42l51_dai, 1);
770 	if (ret < 0)
771 		goto error;
772 
773 	return 0;
774 
775 error:
776 	regulator_bulk_disable(ARRAY_SIZE(cs42l51->supplies),
777 			       cs42l51->supplies);
778 	return ret;
779 }
780 EXPORT_SYMBOL_GPL(cs42l51_probe);
781 
cs42l51_remove(struct device * dev)782 int cs42l51_remove(struct device *dev)
783 {
784 	struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
785 
786 	gpiod_set_value_cansleep(cs42l51->reset_gpio, 1);
787 
788 	return regulator_bulk_disable(ARRAY_SIZE(cs42l51->supplies),
789 				      cs42l51->supplies);
790 }
791 EXPORT_SYMBOL_GPL(cs42l51_remove);
792 
cs42l51_suspend(struct device * dev)793 int __maybe_unused cs42l51_suspend(struct device *dev)
794 {
795 	struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
796 
797 	regcache_cache_only(cs42l51->regmap, true);
798 	regcache_mark_dirty(cs42l51->regmap);
799 
800 	return 0;
801 }
802 EXPORT_SYMBOL_GPL(cs42l51_suspend);
803 
cs42l51_resume(struct device * dev)804 int __maybe_unused cs42l51_resume(struct device *dev)
805 {
806 	struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
807 
808 	regcache_cache_only(cs42l51->regmap, false);
809 
810 	return regcache_sync(cs42l51->regmap);
811 }
812 EXPORT_SYMBOL_GPL(cs42l51_resume);
813 
814 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
815 MODULE_DESCRIPTION("Cirrus Logic CS42L51 ALSA SoC Codec Driver");
816 MODULE_LICENSE("GPL");
817