1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // nau8822.c -- NAU8822 ALSA Soc Audio driver
4 //
5 // Copyright 2017 Nuvoton Technology Crop.
6 //
7 // Author: David Lin <ctlin0@nuvoton.com>
8 // Co-author: John Hsu <kchsu0@nuvoton.com>
9 // Co-author: Seven Li <wtli@nuvoton.com>
10 //
11 // Based on WM8974.c
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28 #include <asm/div64.h>
29 #include "nau8822.h"
30
31 #define NAU_PLL_FREQ_MAX 100000000
32 #define NAU_PLL_FREQ_MIN 90000000
33 #define NAU_PLL_REF_MAX 33000000
34 #define NAU_PLL_REF_MIN 8000000
35 #define NAU_PLL_OPTOP_MIN 6
36
37 static const int nau8822_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 };
38
39 static const struct reg_default nau8822_reg_defaults[] = {
40 { NAU8822_REG_POWER_MANAGEMENT_1, 0x0000 },
41 { NAU8822_REG_POWER_MANAGEMENT_2, 0x0000 },
42 { NAU8822_REG_POWER_MANAGEMENT_3, 0x0000 },
43 { NAU8822_REG_AUDIO_INTERFACE, 0x0050 },
44 { NAU8822_REG_COMPANDING_CONTROL, 0x0000 },
45 { NAU8822_REG_CLOCKING, 0x0140 },
46 { NAU8822_REG_ADDITIONAL_CONTROL, 0x0000 },
47 { NAU8822_REG_GPIO_CONTROL, 0x0000 },
48 { NAU8822_REG_JACK_DETECT_CONTROL_1, 0x0000 },
49 { NAU8822_REG_DAC_CONTROL, 0x0000 },
50 { NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME, 0x00ff },
51 { NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0x00ff },
52 { NAU8822_REG_JACK_DETECT_CONTROL_2, 0x0000 },
53 { NAU8822_REG_ADC_CONTROL, 0x0100 },
54 { NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME, 0x00ff },
55 { NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0x00ff },
56 { NAU8822_REG_EQ1, 0x012c },
57 { NAU8822_REG_EQ2, 0x002c },
58 { NAU8822_REG_EQ3, 0x002c },
59 { NAU8822_REG_EQ4, 0x002c },
60 { NAU8822_REG_EQ5, 0x002c },
61 { NAU8822_REG_DAC_LIMITER_1, 0x0032 },
62 { NAU8822_REG_DAC_LIMITER_2, 0x0000 },
63 { NAU8822_REG_NOTCH_FILTER_1, 0x0000 },
64 { NAU8822_REG_NOTCH_FILTER_2, 0x0000 },
65 { NAU8822_REG_NOTCH_FILTER_3, 0x0000 },
66 { NAU8822_REG_NOTCH_FILTER_4, 0x0000 },
67 { NAU8822_REG_ALC_CONTROL_1, 0x0038 },
68 { NAU8822_REG_ALC_CONTROL_2, 0x000b },
69 { NAU8822_REG_ALC_CONTROL_3, 0x0032 },
70 { NAU8822_REG_NOISE_GATE, 0x0010 },
71 { NAU8822_REG_PLL_N, 0x0008 },
72 { NAU8822_REG_PLL_K1, 0x000c },
73 { NAU8822_REG_PLL_K2, 0x0093 },
74 { NAU8822_REG_PLL_K3, 0x00e9 },
75 { NAU8822_REG_3D_CONTROL, 0x0000 },
76 { NAU8822_REG_RIGHT_SPEAKER_CONTROL, 0x0000 },
77 { NAU8822_REG_INPUT_CONTROL, 0x0033 },
78 { NAU8822_REG_LEFT_INP_PGA_CONTROL, 0x0010 },
79 { NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0x0010 },
80 { NAU8822_REG_LEFT_ADC_BOOST_CONTROL, 0x0100 },
81 { NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0x0100 },
82 { NAU8822_REG_OUTPUT_CONTROL, 0x0002 },
83 { NAU8822_REG_LEFT_MIXER_CONTROL, 0x0001 },
84 { NAU8822_REG_RIGHT_MIXER_CONTROL, 0x0001 },
85 { NAU8822_REG_LHP_VOLUME, 0x0039 },
86 { NAU8822_REG_RHP_VOLUME, 0x0039 },
87 { NAU8822_REG_LSPKOUT_VOLUME, 0x0039 },
88 { NAU8822_REG_RSPKOUT_VOLUME, 0x0039 },
89 { NAU8822_REG_AUX2_MIXER, 0x0001 },
90 { NAU8822_REG_AUX1_MIXER, 0x0001 },
91 { NAU8822_REG_POWER_MANAGEMENT_4, 0x0000 },
92 { NAU8822_REG_LEFT_TIME_SLOT, 0x0000 },
93 { NAU8822_REG_MISC, 0x0020 },
94 { NAU8822_REG_RIGHT_TIME_SLOT, 0x0000 },
95 { NAU8822_REG_DEVICE_REVISION, 0x007f },
96 { NAU8822_REG_DEVICE_ID, 0x001a },
97 { NAU8822_REG_DAC_DITHER, 0x0114 },
98 { NAU8822_REG_ALC_ENHANCE_1, 0x0000 },
99 { NAU8822_REG_ALC_ENHANCE_2, 0x0000 },
100 { NAU8822_REG_192KHZ_SAMPLING, 0x0008 },
101 { NAU8822_REG_MISC_CONTROL, 0x0000 },
102 { NAU8822_REG_INPUT_TIEOFF, 0x0000 },
103 { NAU8822_REG_POWER_REDUCTION, 0x0000 },
104 { NAU8822_REG_AGC_PEAK2PEAK, 0x0000 },
105 { NAU8822_REG_AGC_PEAK_DETECT, 0x0000 },
106 { NAU8822_REG_AUTOMUTE_CONTROL, 0x0000 },
107 { NAU8822_REG_OUTPUT_TIEOFF, 0x0000 },
108 };
109
nau8822_readable_reg(struct device * dev,unsigned int reg)110 static bool nau8822_readable_reg(struct device *dev, unsigned int reg)
111 {
112 switch (reg) {
113 case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1:
114 case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME:
115 case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME:
116 case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5:
117 case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2:
118 case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4:
119 case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3:
120 case NAU8822_REG_3D_CONTROL:
121 case NAU8822_REG_RIGHT_SPEAKER_CONTROL:
122 case NAU8822_REG_INPUT_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL:
123 case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER:
124 case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID:
125 case NAU8822_REG_DAC_DITHER:
126 case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL:
127 case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF:
128 return true;
129 default:
130 return false;
131 }
132 }
133
nau8822_writeable_reg(struct device * dev,unsigned int reg)134 static bool nau8822_writeable_reg(struct device *dev, unsigned int reg)
135 {
136 switch (reg) {
137 case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1:
138 case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME:
139 case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME:
140 case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5:
141 case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2:
142 case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4:
143 case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3:
144 case NAU8822_REG_3D_CONTROL:
145 case NAU8822_REG_RIGHT_SPEAKER_CONTROL:
146 case NAU8822_REG_INPUT_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL:
147 case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER:
148 case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID:
149 case NAU8822_REG_DAC_DITHER:
150 case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL:
151 case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF:
152 return true;
153 default:
154 return false;
155 }
156 }
157
nau8822_volatile(struct device * dev,unsigned int reg)158 static bool nau8822_volatile(struct device *dev, unsigned int reg)
159 {
160 switch (reg) {
161 case NAU8822_REG_RESET:
162 case NAU8822_REG_DEVICE_REVISION:
163 case NAU8822_REG_DEVICE_ID:
164 case NAU8822_REG_AGC_PEAK2PEAK:
165 case NAU8822_REG_AGC_PEAK_DETECT:
166 case NAU8822_REG_AUTOMUTE_CONTROL:
167 return true;
168 default:
169 return false;
170 }
171 }
172
173 /* The EQ parameters get function is to get the 5 band equalizer control.
174 * The regmap raw read can't work here because regmap doesn't provide
175 * value format for value width of 9 bits. Therefore, the driver reads data
176 * from cache and makes value format according to the endianness of
177 * bytes type control element.
178 */
nau8822_eq_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)179 static int nau8822_eq_get(struct snd_kcontrol *kcontrol,
180 struct snd_ctl_elem_value *ucontrol)
181 {
182 struct snd_soc_component *component =
183 snd_soc_kcontrol_component(kcontrol);
184 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
185 int i, reg;
186 u16 reg_val, *val;
187 __be16 tmp;
188
189 val = (u16 *)ucontrol->value.bytes.data;
190 reg = NAU8822_REG_EQ1;
191 for (i = 0; i < params->max / sizeof(u16); i++) {
192 reg_val = snd_soc_component_read32(component, reg + i);
193 /* conversion of 16-bit integers between native CPU format
194 * and big endian format
195 */
196 tmp = cpu_to_be16(reg_val);
197 memcpy(val + i, &tmp, sizeof(tmp));
198 }
199
200 return 0;
201 }
202
203 /* The EQ parameters put function is to make configuration of 5 band equalizer
204 * control. These configuration includes central frequency, equalizer gain,
205 * cut-off frequency, bandwidth control, and equalizer path.
206 * The regmap raw write can't work here because regmap doesn't provide
207 * register and value format for register with address 7 bits and value 9 bits.
208 * Therefore, the driver makes value format according to the endianness of
209 * bytes type control element and writes data to codec.
210 */
nau8822_eq_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)211 static int nau8822_eq_put(struct snd_kcontrol *kcontrol,
212 struct snd_ctl_elem_value *ucontrol)
213 {
214 struct snd_soc_component *component =
215 snd_soc_kcontrol_component(kcontrol);
216 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
217 void *data;
218 u16 *val, value;
219 int i, reg, ret;
220 __be16 *tmp;
221
222 data = kmemdup(ucontrol->value.bytes.data,
223 params->max, GFP_KERNEL | GFP_DMA);
224 if (!data)
225 return -ENOMEM;
226
227 val = (u16 *)data;
228 reg = NAU8822_REG_EQ1;
229 for (i = 0; i < params->max / sizeof(u16); i++) {
230 /* conversion of 16-bit integers between native CPU format
231 * and big endian format
232 */
233 tmp = (__be16 *)(val + i);
234 value = be16_to_cpup(tmp);
235 ret = snd_soc_component_write(component, reg + i, value);
236 if (ret) {
237 dev_err(component->dev,
238 "EQ configuration fail, register: %x ret: %d\n",
239 reg + i, ret);
240 kfree(data);
241 return ret;
242 }
243 }
244 kfree(data);
245
246 return 0;
247 }
248
249 static const char * const nau8822_companding[] = {
250 "Off", "NC", "u-law", "A-law"};
251
252 static const struct soc_enum nau8822_companding_adc_enum =
253 SOC_ENUM_SINGLE(NAU8822_REG_COMPANDING_CONTROL, NAU8822_ADCCM_SFT,
254 ARRAY_SIZE(nau8822_companding), nau8822_companding);
255
256 static const struct soc_enum nau8822_companding_dac_enum =
257 SOC_ENUM_SINGLE(NAU8822_REG_COMPANDING_CONTROL, NAU8822_DACCM_SFT,
258 ARRAY_SIZE(nau8822_companding), nau8822_companding);
259
260 static const char * const nau8822_eqmode[] = {"Capture", "Playback"};
261
262 static const struct soc_enum nau8822_eqmode_enum =
263 SOC_ENUM_SINGLE(NAU8822_REG_EQ1, NAU8822_EQM_SFT,
264 ARRAY_SIZE(nau8822_eqmode), nau8822_eqmode);
265
266 static const char * const nau8822_alc1[] = {"Off", "Right", "Left", "Both"};
267 static const char * const nau8822_alc3[] = {"Normal", "Limiter"};
268
269 static const struct soc_enum nau8822_alc_enable_enum =
270 SOC_ENUM_SINGLE(NAU8822_REG_ALC_CONTROL_1, NAU8822_ALCEN_SFT,
271 ARRAY_SIZE(nau8822_alc1), nau8822_alc1);
272
273 static const struct soc_enum nau8822_alc_mode_enum =
274 SOC_ENUM_SINGLE(NAU8822_REG_ALC_CONTROL_3, NAU8822_ALCM_SFT,
275 ARRAY_SIZE(nau8822_alc3), nau8822_alc3);
276
277 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
278 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
279 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
280 static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
281 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
282 static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0);
283
284 static const struct snd_kcontrol_new nau8822_snd_controls[] = {
285 SOC_ENUM("ADC Companding", nau8822_companding_adc_enum),
286 SOC_ENUM("DAC Companding", nau8822_companding_dac_enum),
287
288 SOC_ENUM("EQ Function", nau8822_eqmode_enum),
289 SND_SOC_BYTES_EXT("EQ Parameters", 10,
290 nau8822_eq_get, nau8822_eq_put),
291
292 SOC_DOUBLE("DAC Inversion Switch",
293 NAU8822_REG_DAC_CONTROL, 0, 1, 1, 0),
294 SOC_DOUBLE_R_TLV("PCM Volume",
295 NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME,
296 NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0, 255, 0, digital_tlv),
297
298 SOC_SINGLE("High Pass Filter Switch",
299 NAU8822_REG_ADC_CONTROL, 8, 1, 0),
300 SOC_SINGLE("High Pass Cut Off",
301 NAU8822_REG_ADC_CONTROL, 4, 7, 0),
302
303 SOC_DOUBLE("ADC Inversion Switch",
304 NAU8822_REG_ADC_CONTROL, 0, 1, 1, 0),
305 SOC_DOUBLE_R_TLV("ADC Volume",
306 NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME,
307 NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0, 255, 0, digital_tlv),
308
309 SOC_SINGLE("DAC Limiter Switch",
310 NAU8822_REG_DAC_LIMITER_1, 8, 1, 0),
311 SOC_SINGLE("DAC Limiter Decay",
312 NAU8822_REG_DAC_LIMITER_1, 4, 15, 0),
313 SOC_SINGLE("DAC Limiter Attack",
314 NAU8822_REG_DAC_LIMITER_1, 0, 15, 0),
315 SOC_SINGLE("DAC Limiter Threshold",
316 NAU8822_REG_DAC_LIMITER_2, 4, 7, 0),
317 SOC_SINGLE_TLV("DAC Limiter Volume",
318 NAU8822_REG_DAC_LIMITER_2, 0, 12, 0, limiter_tlv),
319
320 SOC_ENUM("ALC Mode", nau8822_alc_mode_enum),
321 SOC_ENUM("ALC Enable Switch", nau8822_alc_enable_enum),
322 SOC_SINGLE("ALC Min Gain",
323 NAU8822_REG_ALC_CONTROL_1, 0, 7, 0),
324 SOC_SINGLE("ALC Max Gain",
325 NAU8822_REG_ALC_CONTROL_1, 3, 7, 0),
326 SOC_SINGLE("ALC Hold",
327 NAU8822_REG_ALC_CONTROL_2, 4, 10, 0),
328 SOC_SINGLE("ALC Target",
329 NAU8822_REG_ALC_CONTROL_2, 0, 15, 0),
330 SOC_SINGLE("ALC Decay",
331 NAU8822_REG_ALC_CONTROL_3, 4, 10, 0),
332 SOC_SINGLE("ALC Attack",
333 NAU8822_REG_ALC_CONTROL_3, 0, 10, 0),
334 SOC_SINGLE("ALC Noise Gate Switch",
335 NAU8822_REG_NOISE_GATE, 3, 1, 0),
336 SOC_SINGLE("ALC Noise Gate Threshold",
337 NAU8822_REG_NOISE_GATE, 0, 7, 0),
338
339 SOC_DOUBLE_R("PGA ZC Switch",
340 NAU8822_REG_LEFT_INP_PGA_CONTROL,
341 NAU8822_REG_RIGHT_INP_PGA_CONTROL,
342 7, 1, 0),
343 SOC_DOUBLE_R_TLV("PGA Volume",
344 NAU8822_REG_LEFT_INP_PGA_CONTROL,
345 NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0, 63, 0, inpga_tlv),
346
347 SOC_DOUBLE_R("Headphone ZC Switch",
348 NAU8822_REG_LHP_VOLUME,
349 NAU8822_REG_RHP_VOLUME, 7, 1, 0),
350 SOC_DOUBLE_R("Headphone Playback Switch",
351 NAU8822_REG_LHP_VOLUME,
352 NAU8822_REG_RHP_VOLUME, 6, 1, 1),
353 SOC_DOUBLE_R_TLV("Headphone Volume",
354 NAU8822_REG_LHP_VOLUME,
355 NAU8822_REG_RHP_VOLUME, 0, 63, 0, spk_tlv),
356
357 SOC_DOUBLE_R("Speaker ZC Switch",
358 NAU8822_REG_LSPKOUT_VOLUME,
359 NAU8822_REG_RSPKOUT_VOLUME, 7, 1, 0),
360 SOC_DOUBLE_R("Speaker Playback Switch",
361 NAU8822_REG_LSPKOUT_VOLUME,
362 NAU8822_REG_RSPKOUT_VOLUME, 6, 1, 1),
363 SOC_DOUBLE_R_TLV("Speaker Volume",
364 NAU8822_REG_LSPKOUT_VOLUME,
365 NAU8822_REG_RSPKOUT_VOLUME, 0, 63, 0, spk_tlv),
366
367 SOC_DOUBLE_R("AUXOUT Playback Switch",
368 NAU8822_REG_AUX2_MIXER,
369 NAU8822_REG_AUX1_MIXER, 6, 1, 1),
370
371 SOC_DOUBLE_R_TLV("PGA Boost Volume",
372 NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
373 NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 8, 1, 0, pga_boost_tlv),
374 SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
375 NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
376 NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 4, 7, 0, boost_tlv),
377 SOC_DOUBLE_R_TLV("Aux Boost Volume",
378 NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
379 NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0, 7, 0, boost_tlv),
380
381 SOC_SINGLE("DAC 128x Oversampling Switch",
382 NAU8822_REG_DAC_CONTROL, 5, 1, 0),
383 SOC_SINGLE("ADC 128x Oversampling Switch",
384 NAU8822_REG_ADC_CONTROL, 5, 1, 0),
385 };
386
387 /* LMAIN and RMAIN Mixer */
388 static const struct snd_kcontrol_new nau8822_left_out_mixer[] = {
389 SOC_DAPM_SINGLE("LINMIX Switch",
390 NAU8822_REG_LEFT_MIXER_CONTROL, 1, 1, 0),
391 SOC_DAPM_SINGLE("LAUX Switch",
392 NAU8822_REG_LEFT_MIXER_CONTROL, 5, 1, 0),
393 SOC_DAPM_SINGLE("LDAC Switch",
394 NAU8822_REG_LEFT_MIXER_CONTROL, 0, 1, 0),
395 SOC_DAPM_SINGLE("RDAC Switch",
396 NAU8822_REG_OUTPUT_CONTROL, 5, 1, 0),
397 };
398
399 static const struct snd_kcontrol_new nau8822_right_out_mixer[] = {
400 SOC_DAPM_SINGLE("RINMIX Switch",
401 NAU8822_REG_RIGHT_MIXER_CONTROL, 1, 1, 0),
402 SOC_DAPM_SINGLE("RAUX Switch",
403 NAU8822_REG_RIGHT_MIXER_CONTROL, 5, 1, 0),
404 SOC_DAPM_SINGLE("RDAC Switch",
405 NAU8822_REG_RIGHT_MIXER_CONTROL, 0, 1, 0),
406 SOC_DAPM_SINGLE("LDAC Switch",
407 NAU8822_REG_OUTPUT_CONTROL, 6, 1, 0),
408 };
409
410 /* AUX1 and AUX2 Mixer */
411 static const struct snd_kcontrol_new nau8822_auxout1_mixer[] = {
412 SOC_DAPM_SINGLE("RDAC Switch", NAU8822_REG_AUX1_MIXER, 0, 1, 0),
413 SOC_DAPM_SINGLE("RMIX Switch", NAU8822_REG_AUX1_MIXER, 1, 1, 0),
414 SOC_DAPM_SINGLE("RINMIX Switch", NAU8822_REG_AUX1_MIXER, 2, 1, 0),
415 SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX1_MIXER, 3, 1, 0),
416 SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX1_MIXER, 4, 1, 0),
417 };
418
419 static const struct snd_kcontrol_new nau8822_auxout2_mixer[] = {
420 SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX2_MIXER, 0, 1, 0),
421 SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX2_MIXER, 1, 1, 0),
422 SOC_DAPM_SINGLE("LINMIX Switch", NAU8822_REG_AUX2_MIXER, 2, 1, 0),
423 SOC_DAPM_SINGLE("AUX1MIX Output Switch",
424 NAU8822_REG_AUX2_MIXER, 3, 1, 0),
425 };
426
427 /* Input PGA */
428 static const struct snd_kcontrol_new nau8822_left_input_mixer[] = {
429 SOC_DAPM_SINGLE("L2 Switch", NAU8822_REG_INPUT_CONTROL, 2, 1, 0),
430 SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 1, 1, 0),
431 SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 0, 1, 0),
432 };
433 static const struct snd_kcontrol_new nau8822_right_input_mixer[] = {
434 SOC_DAPM_SINGLE("R2 Switch", NAU8822_REG_INPUT_CONTROL, 6, 1, 0),
435 SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 5, 1, 0),
436 SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 4, 1, 0),
437 };
438
439 /* Loopback Switch */
440 static const struct snd_kcontrol_new nau8822_loopback =
441 SOC_DAPM_SINGLE("Switch", NAU8822_REG_COMPANDING_CONTROL,
442 NAU8822_ADDAP_SFT, 1, 0);
443
check_mclk_select_pll(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)444 static int check_mclk_select_pll(struct snd_soc_dapm_widget *source,
445 struct snd_soc_dapm_widget *sink)
446 {
447 struct snd_soc_component *component =
448 snd_soc_dapm_to_component(source->dapm);
449 unsigned int value;
450
451 value = snd_soc_component_read32(component, NAU8822_REG_CLOCKING);
452
453 return (value & NAU8822_CLKM_MASK);
454 }
455
456 static const struct snd_soc_dapm_widget nau8822_dapm_widgets[] = {
457 SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
458 NAU8822_REG_POWER_MANAGEMENT_3, 0, 0),
459 SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
460 NAU8822_REG_POWER_MANAGEMENT_3, 1, 0),
461 SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
462 NAU8822_REG_POWER_MANAGEMENT_2, 0, 0),
463 SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
464 NAU8822_REG_POWER_MANAGEMENT_2, 1, 0),
465
466 SOC_MIXER_ARRAY("Left Output Mixer",
467 NAU8822_REG_POWER_MANAGEMENT_3, 2, 0, nau8822_left_out_mixer),
468 SOC_MIXER_ARRAY("Right Output Mixer",
469 NAU8822_REG_POWER_MANAGEMENT_3, 3, 0, nau8822_right_out_mixer),
470 SOC_MIXER_ARRAY("AUX1 Output Mixer",
471 NAU8822_REG_POWER_MANAGEMENT_1, 7, 0, nau8822_auxout1_mixer),
472 SOC_MIXER_ARRAY("AUX2 Output Mixer",
473 NAU8822_REG_POWER_MANAGEMENT_1, 6, 0, nau8822_auxout2_mixer),
474
475 SOC_MIXER_ARRAY("Left Input Mixer",
476 NAU8822_REG_POWER_MANAGEMENT_2,
477 2, 0, nau8822_left_input_mixer),
478 SOC_MIXER_ARRAY("Right Input Mixer",
479 NAU8822_REG_POWER_MANAGEMENT_2,
480 3, 0, nau8822_right_input_mixer),
481
482 SND_SOC_DAPM_PGA("Left Boost Mixer",
483 NAU8822_REG_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
484 SND_SOC_DAPM_PGA("Right Boost Mixer",
485 NAU8822_REG_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
486
487 SND_SOC_DAPM_PGA("Left Capture PGA",
488 NAU8822_REG_LEFT_INP_PGA_CONTROL, 6, 1, NULL, 0),
489 SND_SOC_DAPM_PGA("Right Capture PGA",
490 NAU8822_REG_RIGHT_INP_PGA_CONTROL, 6, 1, NULL, 0),
491
492 SND_SOC_DAPM_PGA("Left Headphone Out",
493 NAU8822_REG_POWER_MANAGEMENT_2, 7, 0, NULL, 0),
494 SND_SOC_DAPM_PGA("Right Headphone Out",
495 NAU8822_REG_POWER_MANAGEMENT_2, 8, 0, NULL, 0),
496
497 SND_SOC_DAPM_PGA("Left Speaker Out",
498 NAU8822_REG_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
499 SND_SOC_DAPM_PGA("Right Speaker Out",
500 NAU8822_REG_POWER_MANAGEMENT_3, 5, 0, NULL, 0),
501
502 SND_SOC_DAPM_PGA("AUX1 Out",
503 NAU8822_REG_POWER_MANAGEMENT_3, 8, 0, NULL, 0),
504 SND_SOC_DAPM_PGA("AUX2 Out",
505 NAU8822_REG_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
506
507 SND_SOC_DAPM_SUPPLY("Mic Bias",
508 NAU8822_REG_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
509 SND_SOC_DAPM_SUPPLY("PLL",
510 NAU8822_REG_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
511
512 SND_SOC_DAPM_SWITCH("Digital Loopback", SND_SOC_NOPM, 0, 0,
513 &nau8822_loopback),
514
515 SND_SOC_DAPM_INPUT("LMICN"),
516 SND_SOC_DAPM_INPUT("LMICP"),
517 SND_SOC_DAPM_INPUT("RMICN"),
518 SND_SOC_DAPM_INPUT("RMICP"),
519 SND_SOC_DAPM_INPUT("LAUX"),
520 SND_SOC_DAPM_INPUT("RAUX"),
521 SND_SOC_DAPM_INPUT("L2"),
522 SND_SOC_DAPM_INPUT("R2"),
523 SND_SOC_DAPM_OUTPUT("LHP"),
524 SND_SOC_DAPM_OUTPUT("RHP"),
525 SND_SOC_DAPM_OUTPUT("LSPK"),
526 SND_SOC_DAPM_OUTPUT("RSPK"),
527 SND_SOC_DAPM_OUTPUT("AUXOUT1"),
528 SND_SOC_DAPM_OUTPUT("AUXOUT2"),
529 };
530
531 static const struct snd_soc_dapm_route nau8822_dapm_routes[] = {
532 {"Right DAC", NULL, "PLL", check_mclk_select_pll},
533 {"Left DAC", NULL, "PLL", check_mclk_select_pll},
534
535 /* LMAIN and RMAIN Mixer */
536 {"Right Output Mixer", "LDAC Switch", "Left DAC"},
537 {"Right Output Mixer", "RDAC Switch", "Right DAC"},
538 {"Right Output Mixer", "RAUX Switch", "RAUX"},
539 {"Right Output Mixer", "RINMIX Switch", "Right Boost Mixer"},
540
541 {"Left Output Mixer", "LDAC Switch", "Left DAC"},
542 {"Left Output Mixer", "RDAC Switch", "Right DAC"},
543 {"Left Output Mixer", "LAUX Switch", "LAUX"},
544 {"Left Output Mixer", "LINMIX Switch", "Left Boost Mixer"},
545
546 /* AUX1 and AUX2 Mixer */
547 {"AUX1 Output Mixer", "RDAC Switch", "Right DAC"},
548 {"AUX1 Output Mixer", "RMIX Switch", "Right Output Mixer"},
549 {"AUX1 Output Mixer", "RINMIX Switch", "Right Boost Mixer"},
550 {"AUX1 Output Mixer", "LDAC Switch", "Left DAC"},
551 {"AUX1 Output Mixer", "LMIX Switch", "Left Output Mixer"},
552
553 {"AUX2 Output Mixer", "LDAC Switch", "Left DAC"},
554 {"AUX2 Output Mixer", "LMIX Switch", "Left Output Mixer"},
555 {"AUX2 Output Mixer", "LINMIX Switch", "Left Boost Mixer"},
556 {"AUX2 Output Mixer", "AUX1MIX Output Switch", "AUX1 Output Mixer"},
557
558 /* Outputs */
559 {"Right Headphone Out", NULL, "Right Output Mixer"},
560 {"RHP", NULL, "Right Headphone Out"},
561
562 {"Left Headphone Out", NULL, "Left Output Mixer"},
563 {"LHP", NULL, "Left Headphone Out"},
564
565 {"Right Speaker Out", NULL, "Right Output Mixer"},
566 {"RSPK", NULL, "Right Speaker Out"},
567
568 {"Left Speaker Out", NULL, "Left Output Mixer"},
569 {"LSPK", NULL, "Left Speaker Out"},
570
571 {"AUX1 Out", NULL, "AUX1 Output Mixer"},
572 {"AUX2 Out", NULL, "AUX2 Output Mixer"},
573 {"AUXOUT1", NULL, "AUX1 Out"},
574 {"AUXOUT2", NULL, "AUX2 Out"},
575
576 /* Boost Mixer */
577 {"Right ADC", NULL, "PLL", check_mclk_select_pll},
578 {"Left ADC", NULL, "PLL", check_mclk_select_pll},
579
580 {"Right ADC", NULL, "Right Boost Mixer"},
581
582 {"Right Boost Mixer", NULL, "RAUX"},
583 {"Right Boost Mixer", NULL, "Right Capture PGA"},
584 {"Right Boost Mixer", NULL, "R2"},
585
586 {"Left ADC", NULL, "Left Boost Mixer"},
587
588 {"Left Boost Mixer", NULL, "LAUX"},
589 {"Left Boost Mixer", NULL, "Left Capture PGA"},
590 {"Left Boost Mixer", NULL, "L2"},
591
592 /* Input PGA */
593 {"Right Capture PGA", NULL, "Right Input Mixer"},
594 {"Left Capture PGA", NULL, "Left Input Mixer"},
595
596 /* Enable Microphone Power */
597 {"Right Capture PGA", NULL, "Mic Bias"},
598 {"Left Capture PGA", NULL, "Mic Bias"},
599
600 {"Right Input Mixer", "R2 Switch", "R2"},
601 {"Right Input Mixer", "MicN Switch", "RMICN"},
602 {"Right Input Mixer", "MicP Switch", "RMICP"},
603
604 {"Left Input Mixer", "L2 Switch", "L2"},
605 {"Left Input Mixer", "MicN Switch", "LMICN"},
606 {"Left Input Mixer", "MicP Switch", "LMICP"},
607
608 /* Digital Loopback */
609 {"Digital Loopback", "Switch", "Left ADC"},
610 {"Digital Loopback", "Switch", "Right ADC"},
611 {"Left DAC", NULL, "Digital Loopback"},
612 {"Right DAC", NULL, "Digital Loopback"},
613 };
614
nau8822_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)615 static int nau8822_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
616 unsigned int freq, int dir)
617 {
618 struct snd_soc_component *component = dai->component;
619 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
620
621 nau8822->div_id = clk_id;
622 nau8822->sysclk = freq;
623 dev_dbg(component->dev, "master sysclk %dHz, source %s\n", freq,
624 clk_id == NAU8822_CLK_PLL ? "PLL" : "MCLK");
625
626 return 0;
627 }
628
nau8822_calc_pll(unsigned int pll_in,unsigned int fs,struct nau8822_pll * pll_param)629 static int nau8822_calc_pll(unsigned int pll_in, unsigned int fs,
630 struct nau8822_pll *pll_param)
631 {
632 u64 f2, f2_max, pll_ratio;
633 int i, scal_sel;
634
635 if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN)
636 return -EINVAL;
637 f2_max = 0;
638 scal_sel = ARRAY_SIZE(nau8822_mclk_scaler);
639
640 for (i = 0; i < scal_sel; i++) {
641 f2 = 256 * fs * 4 * nau8822_mclk_scaler[i] / 10;
642 if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX &&
643 f2_max < f2) {
644 f2_max = f2;
645 scal_sel = i;
646 }
647 }
648
649 if (ARRAY_SIZE(nau8822_mclk_scaler) == scal_sel)
650 return -EINVAL;
651 pll_param->mclk_scaler = scal_sel;
652 f2 = f2_max;
653
654 /* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional
655 * input; round up the 24+4bit.
656 */
657 pll_ratio = div_u64(f2 << 28, pll_in);
658 pll_param->pre_factor = 0;
659 if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) {
660 pll_ratio <<= 1;
661 pll_param->pre_factor = 1;
662 }
663 pll_param->pll_int = (pll_ratio >> 28) & 0xF;
664 pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);
665
666 return 0;
667 }
668
nau8822_config_clkdiv(struct snd_soc_dai * dai,int div,int rate)669 static int nau8822_config_clkdiv(struct snd_soc_dai *dai, int div, int rate)
670 {
671 struct snd_soc_component *component = dai->component;
672 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
673 struct nau8822_pll *pll = &nau8822->pll;
674 int i, sclk, imclk;
675
676 switch (nau8822->div_id) {
677 case NAU8822_CLK_MCLK:
678 /* Configure the master clock prescaler div to make system
679 * clock to approximate the internal master clock (IMCLK);
680 * and large or equal to IMCLK.
681 */
682 div = 0;
683 imclk = rate * 256;
684 for (i = 1; i < ARRAY_SIZE(nau8822_mclk_scaler); i++) {
685 sclk = (nau8822->sysclk * 10) / nau8822_mclk_scaler[i];
686 if (sclk < imclk)
687 break;
688 div = i;
689 }
690 dev_dbg(component->dev, "master clock prescaler %x for fs %d\n",
691 div, rate);
692
693 /* master clock from MCLK and disable PLL */
694 snd_soc_component_update_bits(component,
695 NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
696 (div << NAU8822_MCLKSEL_SFT));
697 snd_soc_component_update_bits(component,
698 NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK,
699 NAU8822_CLKM_MCLK);
700 break;
701
702 case NAU8822_CLK_PLL:
703 /* master clock from PLL and enable PLL */
704 if (pll->mclk_scaler != div) {
705 dev_err(component->dev,
706 "master clock prescaler not meet PLL parameters\n");
707 return -EINVAL;
708 }
709 snd_soc_component_update_bits(component,
710 NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
711 (div << NAU8822_MCLKSEL_SFT));
712 snd_soc_component_update_bits(component,
713 NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK,
714 NAU8822_CLKM_PLL);
715 break;
716
717 default:
718 return -EINVAL;
719 }
720
721 return 0;
722 }
723
nau8822_set_pll(struct snd_soc_dai * dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)724 static int nau8822_set_pll(struct snd_soc_dai *dai, int pll_id, int source,
725 unsigned int freq_in, unsigned int freq_out)
726 {
727 struct snd_soc_component *component = dai->component;
728 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
729 struct nau8822_pll *pll_param = &nau8822->pll;
730 int ret, fs;
731
732 fs = freq_out / 256;
733
734 ret = nau8822_calc_pll(freq_in, fs, pll_param);
735 if (ret < 0) {
736 dev_err(component->dev, "Unsupported input clock %d\n",
737 freq_in);
738 return ret;
739 }
740
741 dev_info(component->dev,
742 "pll_int=%x pll_frac=%x mclk_scaler=%x pre_factor=%x\n",
743 pll_param->pll_int, pll_param->pll_frac,
744 pll_param->mclk_scaler, pll_param->pre_factor);
745
746 snd_soc_component_update_bits(component,
747 NAU8822_REG_POWER_MANAGEMENT_1, NAU8822_PLL_EN_MASK, NAU8822_PLL_OFF);
748 snd_soc_component_update_bits(component,
749 NAU8822_REG_PLL_N, NAU8822_PLLMCLK_DIV2 | NAU8822_PLLN_MASK,
750 (pll_param->pre_factor ? NAU8822_PLLMCLK_DIV2 : 0) |
751 pll_param->pll_int);
752 snd_soc_component_write(component,
753 NAU8822_REG_PLL_K1, (pll_param->pll_frac >> NAU8822_PLLK1_SFT) &
754 NAU8822_PLLK1_MASK);
755 snd_soc_component_write(component,
756 NAU8822_REG_PLL_K2, (pll_param->pll_frac >> NAU8822_PLLK2_SFT) &
757 NAU8822_PLLK2_MASK);
758 snd_soc_component_write(component,
759 NAU8822_REG_PLL_K3, pll_param->pll_frac & NAU8822_PLLK3_MASK);
760 snd_soc_component_update_bits(component,
761 NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
762 pll_param->mclk_scaler << NAU8822_MCLKSEL_SFT);
763 snd_soc_component_update_bits(component,
764 NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK, NAU8822_CLKM_PLL);
765 snd_soc_component_update_bits(component,
766 NAU8822_REG_POWER_MANAGEMENT_1, NAU8822_PLL_EN_MASK, NAU8822_PLL_ON);
767
768 return 0;
769 }
770
nau8822_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)771 static int nau8822_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
772 {
773 struct snd_soc_component *component = dai->component;
774 u16 ctrl1_val = 0, ctrl2_val = 0;
775
776 dev_dbg(component->dev, "%s\n", __func__);
777
778 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
779 case SND_SOC_DAIFMT_CBM_CFM:
780 ctrl2_val |= 1;
781 break;
782 case SND_SOC_DAIFMT_CBS_CFS:
783 ctrl2_val &= ~1;
784 break;
785 default:
786 return -EINVAL;
787 }
788
789 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
790 case SND_SOC_DAIFMT_I2S:
791 ctrl1_val |= 0x10;
792 break;
793 case SND_SOC_DAIFMT_RIGHT_J:
794 break;
795 case SND_SOC_DAIFMT_LEFT_J:
796 ctrl1_val |= 0x8;
797 break;
798 case SND_SOC_DAIFMT_DSP_A:
799 ctrl1_val |= 0x18;
800 break;
801 default:
802 return -EINVAL;
803 }
804
805 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
806 case SND_SOC_DAIFMT_NB_NF:
807 break;
808 case SND_SOC_DAIFMT_IB_IF:
809 ctrl1_val |= 0x180;
810 break;
811 case SND_SOC_DAIFMT_IB_NF:
812 ctrl1_val |= 0x100;
813 break;
814 case SND_SOC_DAIFMT_NB_IF:
815 ctrl1_val |= 0x80;
816 break;
817 default:
818 return -EINVAL;
819 }
820
821 snd_soc_component_update_bits(component,
822 NAU8822_REG_AUDIO_INTERFACE,
823 NAU8822_AIFMT_MASK | NAU8822_LRP_MASK | NAU8822_BCLKP_MASK,
824 ctrl1_val);
825 snd_soc_component_update_bits(component,
826 NAU8822_REG_CLOCKING, NAU8822_CLKIOEN_MASK, ctrl2_val);
827
828 return 0;
829 }
830
nau8822_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)831 static int nau8822_hw_params(struct snd_pcm_substream *substream,
832 struct snd_pcm_hw_params *params,
833 struct snd_soc_dai *dai)
834 {
835 struct snd_soc_component *component = dai->component;
836 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
837 int val_len = 0, val_rate = 0;
838 unsigned int ctrl_val, bclk_fs, bclk_div;
839
840 /* make BCLK and LRC divide configuration if the codec as master. */
841 snd_soc_component_read(component, NAU8822_REG_CLOCKING, &ctrl_val);
842 if (ctrl_val & NAU8822_CLK_MASTER) {
843 /* get the bclk and fs ratio */
844 bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
845 if (bclk_fs <= 32)
846 bclk_div = NAU8822_BCLKDIV_8;
847 else if (bclk_fs <= 64)
848 bclk_div = NAU8822_BCLKDIV_4;
849 else if (bclk_fs <= 128)
850 bclk_div = NAU8822_BCLKDIV_2;
851 else
852 return -EINVAL;
853 snd_soc_component_update_bits(component, NAU8822_REG_CLOCKING,
854 NAU8822_BCLKSEL_MASK, bclk_div);
855 }
856
857 switch (params_format(params)) {
858 case SNDRV_PCM_FORMAT_S16_LE:
859 break;
860 case SNDRV_PCM_FORMAT_S20_3LE:
861 val_len |= NAU8822_WLEN_20;
862 break;
863 case SNDRV_PCM_FORMAT_S24_LE:
864 val_len |= NAU8822_WLEN_24;
865 break;
866 case SNDRV_PCM_FORMAT_S32_LE:
867 val_len |= NAU8822_WLEN_32;
868 break;
869 default:
870 return -EINVAL;
871 }
872
873 switch (params_rate(params)) {
874 case 8000:
875 val_rate |= NAU8822_SMPLR_8K;
876 break;
877 case 11025:
878 val_rate |= NAU8822_SMPLR_12K;
879 break;
880 case 16000:
881 val_rate |= NAU8822_SMPLR_16K;
882 break;
883 case 22050:
884 val_rate |= NAU8822_SMPLR_24K;
885 break;
886 case 32000:
887 val_rate |= NAU8822_SMPLR_32K;
888 break;
889 case 44100:
890 case 48000:
891 break;
892 default:
893 return -EINVAL;
894 }
895
896 snd_soc_component_update_bits(component,
897 NAU8822_REG_AUDIO_INTERFACE, NAU8822_WLEN_MASK, val_len);
898 snd_soc_component_update_bits(component,
899 NAU8822_REG_ADDITIONAL_CONTROL, NAU8822_SMPLR_MASK, val_rate);
900
901 /* If the master clock is from MCLK, provide the runtime FS for driver
902 * to get the master clock prescaler configuration.
903 */
904 if (nau8822->div_id == NAU8822_CLK_MCLK)
905 nau8822_config_clkdiv(dai, 0, params_rate(params));
906
907 return 0;
908 }
909
nau8822_mute(struct snd_soc_dai * dai,int mute)910 static int nau8822_mute(struct snd_soc_dai *dai, int mute)
911 {
912 struct snd_soc_component *component = dai->component;
913
914 dev_dbg(component->dev, "%s: %d\n", __func__, mute);
915
916 if (mute)
917 snd_soc_component_update_bits(component,
918 NAU8822_REG_DAC_CONTROL, 0x40, 0x40);
919 else
920 snd_soc_component_update_bits(component,
921 NAU8822_REG_DAC_CONTROL, 0x40, 0);
922
923 return 0;
924 }
925
nau8822_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)926 static int nau8822_set_bias_level(struct snd_soc_component *component,
927 enum snd_soc_bias_level level)
928 {
929 switch (level) {
930 case SND_SOC_BIAS_ON:
931 case SND_SOC_BIAS_PREPARE:
932 snd_soc_component_update_bits(component,
933 NAU8822_REG_POWER_MANAGEMENT_1,
934 NAU8822_REFIMP_MASK, NAU8822_REFIMP_80K);
935 break;
936
937 case SND_SOC_BIAS_STANDBY:
938 snd_soc_component_update_bits(component,
939 NAU8822_REG_POWER_MANAGEMENT_1,
940 NAU8822_IOBUF_EN | NAU8822_ABIAS_EN,
941 NAU8822_IOBUF_EN | NAU8822_ABIAS_EN);
942
943 if (snd_soc_component_get_bias_level(component) ==
944 SND_SOC_BIAS_OFF) {
945 snd_soc_component_update_bits(component,
946 NAU8822_REG_POWER_MANAGEMENT_1,
947 NAU8822_REFIMP_MASK, NAU8822_REFIMP_3K);
948 mdelay(100);
949 }
950 snd_soc_component_update_bits(component,
951 NAU8822_REG_POWER_MANAGEMENT_1,
952 NAU8822_REFIMP_MASK, NAU8822_REFIMP_300K);
953 break;
954
955 case SND_SOC_BIAS_OFF:
956 snd_soc_component_write(component,
957 NAU8822_REG_POWER_MANAGEMENT_1, 0);
958 snd_soc_component_write(component,
959 NAU8822_REG_POWER_MANAGEMENT_2, 0);
960 snd_soc_component_write(component,
961 NAU8822_REG_POWER_MANAGEMENT_3, 0);
962 break;
963 }
964
965 dev_dbg(component->dev, "%s: %d\n", __func__, level);
966
967 return 0;
968 }
969
970 #define NAU8822_RATES (SNDRV_PCM_RATE_8000_48000)
971
972 #define NAU8822_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
973 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
974
975 static const struct snd_soc_dai_ops nau8822_dai_ops = {
976 .hw_params = nau8822_hw_params,
977 .digital_mute = nau8822_mute,
978 .set_fmt = nau8822_set_dai_fmt,
979 .set_sysclk = nau8822_set_dai_sysclk,
980 .set_pll = nau8822_set_pll,
981 };
982
983 static struct snd_soc_dai_driver nau8822_dai = {
984 .name = "nau8822-hifi",
985 .playback = {
986 .stream_name = "Playback",
987 .channels_min = 1,
988 .channels_max = 2,
989 .rates = NAU8822_RATES,
990 .formats = NAU8822_FORMATS,
991 },
992 .capture = {
993 .stream_name = "Capture",
994 .channels_min = 1,
995 .channels_max = 2,
996 .rates = NAU8822_RATES,
997 .formats = NAU8822_FORMATS,
998 },
999 .ops = &nau8822_dai_ops,
1000 .symmetric_rates = 1,
1001 };
1002
nau8822_suspend(struct snd_soc_component * component)1003 static int nau8822_suspend(struct snd_soc_component *component)
1004 {
1005 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
1006
1007 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1008
1009 regcache_mark_dirty(nau8822->regmap);
1010
1011 return 0;
1012 }
1013
nau8822_resume(struct snd_soc_component * component)1014 static int nau8822_resume(struct snd_soc_component *component)
1015 {
1016 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
1017
1018 regcache_sync(nau8822->regmap);
1019
1020 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1021
1022 return 0;
1023 }
1024
1025 /*
1026 * These registers contain an "update" bit - bit 8. This means, for example,
1027 * that one can write new DAC digital volume for both channels, but only when
1028 * the update bit is set, will also the volume be updated - simultaneously for
1029 * both channels.
1030 */
1031 static const int update_reg[] = {
1032 NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME,
1033 NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME,
1034 NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME,
1035 NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME,
1036 NAU8822_REG_LEFT_INP_PGA_CONTROL,
1037 NAU8822_REG_RIGHT_INP_PGA_CONTROL,
1038 NAU8822_REG_LHP_VOLUME,
1039 NAU8822_REG_RHP_VOLUME,
1040 NAU8822_REG_LSPKOUT_VOLUME,
1041 NAU8822_REG_RSPKOUT_VOLUME,
1042 };
1043
nau8822_probe(struct snd_soc_component * component)1044 static int nau8822_probe(struct snd_soc_component *component)
1045 {
1046 int i;
1047
1048 /*
1049 * Set the update bit in all registers, that have one. This way all
1050 * writes to those registers will also cause the update bit to be
1051 * written.
1052 */
1053 for (i = 0; i < ARRAY_SIZE(update_reg); i++)
1054 snd_soc_component_update_bits(component,
1055 update_reg[i], 0x100, 0x100);
1056
1057 return 0;
1058 }
1059
1060 static const struct snd_soc_component_driver soc_component_dev_nau8822 = {
1061 .probe = nau8822_probe,
1062 .suspend = nau8822_suspend,
1063 .resume = nau8822_resume,
1064 .set_bias_level = nau8822_set_bias_level,
1065 .controls = nau8822_snd_controls,
1066 .num_controls = ARRAY_SIZE(nau8822_snd_controls),
1067 .dapm_widgets = nau8822_dapm_widgets,
1068 .num_dapm_widgets = ARRAY_SIZE(nau8822_dapm_widgets),
1069 .dapm_routes = nau8822_dapm_routes,
1070 .num_dapm_routes = ARRAY_SIZE(nau8822_dapm_routes),
1071 .idle_bias_on = 1,
1072 .use_pmdown_time = 1,
1073 .endianness = 1,
1074 .non_legacy_dai_naming = 1,
1075 };
1076
1077 static const struct regmap_config nau8822_regmap_config = {
1078 .reg_bits = 7,
1079 .val_bits = 9,
1080
1081 .max_register = NAU8822_REG_MAX_REGISTER,
1082 .volatile_reg = nau8822_volatile,
1083
1084 .readable_reg = nau8822_readable_reg,
1085 .writeable_reg = nau8822_writeable_reg,
1086
1087 .cache_type = REGCACHE_RBTREE,
1088 .reg_defaults = nau8822_reg_defaults,
1089 .num_reg_defaults = ARRAY_SIZE(nau8822_reg_defaults),
1090 };
1091
nau8822_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1092 static int nau8822_i2c_probe(struct i2c_client *i2c,
1093 const struct i2c_device_id *id)
1094 {
1095 struct device *dev = &i2c->dev;
1096 struct nau8822 *nau8822 = dev_get_platdata(dev);
1097 int ret;
1098
1099 if (!nau8822) {
1100 nau8822 = devm_kzalloc(dev, sizeof(*nau8822), GFP_KERNEL);
1101 if (nau8822 == NULL)
1102 return -ENOMEM;
1103 }
1104 i2c_set_clientdata(i2c, nau8822);
1105
1106 nau8822->regmap = devm_regmap_init_i2c(i2c, &nau8822_regmap_config);
1107 if (IS_ERR(nau8822->regmap)) {
1108 ret = PTR_ERR(nau8822->regmap);
1109 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
1110 return ret;
1111 }
1112 nau8822->dev = dev;
1113
1114 /* Reset the codec */
1115 ret = regmap_write(nau8822->regmap, NAU8822_REG_RESET, 0x00);
1116 if (ret != 0) {
1117 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
1118 return ret;
1119 }
1120
1121 ret = devm_snd_soc_register_component(dev, &soc_component_dev_nau8822,
1122 &nau8822_dai, 1);
1123 if (ret != 0) {
1124 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
1125 return ret;
1126 }
1127
1128 return 0;
1129 }
1130
1131 static const struct i2c_device_id nau8822_i2c_id[] = {
1132 { "nau8822", 0 },
1133 { }
1134 };
1135 MODULE_DEVICE_TABLE(i2c, nau8822_i2c_id);
1136
1137 #ifdef CONFIG_OF
1138 static const struct of_device_id nau8822_of_match[] = {
1139 { .compatible = "nuvoton,nau8822", },
1140 { }
1141 };
1142 MODULE_DEVICE_TABLE(of, nau8822_of_match);
1143 #endif
1144
1145 static struct i2c_driver nau8822_i2c_driver = {
1146 .driver = {
1147 .name = "nau8822",
1148 .of_match_table = of_match_ptr(nau8822_of_match),
1149 },
1150 .probe = nau8822_i2c_probe,
1151 .id_table = nau8822_i2c_id,
1152 };
1153 module_i2c_driver(nau8822_i2c_driver);
1154
1155 MODULE_DESCRIPTION("ASoC NAU8822 codec driver");
1156 MODULE_AUTHOR("David Lin <ctlin0@nuvoton.com>");
1157 MODULE_LICENSE("GPL v2");
1158