1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rt5682.c -- RT5682 ALSA SoC audio component driver
4 *
5 * Copyright 2018 Realtek Semiconductor Corp.
6 * Author: Bard Liao <bardliao@realtek.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/acpi.h>
18 #include <linux/gpio.h>
19 #include <linux/of_gpio.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/mutex.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/jack.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30 #include <sound/rt5682.h>
31
32 #include "rl6231.h"
33 #include "rt5682.h"
34
35 #define RT5682_NUM_SUPPLIES 3
36
37 static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
38 "AVDD",
39 "MICVDD",
40 "VBAT",
41 };
42
43 static const struct rt5682_platform_data i2s_default_platform_data = {
44 .dmic1_data_pin = RT5682_DMIC1_DATA_GPIO2,
45 .dmic1_clk_pin = RT5682_DMIC1_CLK_GPIO3,
46 .jd_src = RT5682_JD1,
47 };
48
49 struct rt5682_priv {
50 struct snd_soc_component *component;
51 struct rt5682_platform_data pdata;
52 struct regmap *regmap;
53 struct snd_soc_jack *hs_jack;
54 struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES];
55 struct delayed_work jack_detect_work;
56 struct delayed_work jd_check_work;
57 struct mutex calibrate_mutex;
58
59 int sysclk;
60 int sysclk_src;
61 int lrck[RT5682_AIFS];
62 int bclk[RT5682_AIFS];
63 int master[RT5682_AIFS];
64
65 int pll_src;
66 int pll_in;
67 int pll_out;
68
69 int jack_type;
70 };
71
72 static const struct reg_sequence patch_list[] = {
73 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
74 {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
75 {RT5682_I2C_CTRL, 0x000f},
76 };
77
78 static const struct reg_default rt5682_reg[] = {
79 {0x0002, 0x8080},
80 {0x0003, 0x8000},
81 {0x0005, 0x0000},
82 {0x0006, 0x0000},
83 {0x0008, 0x800f},
84 {0x000b, 0x0000},
85 {0x0010, 0x4040},
86 {0x0011, 0x0000},
87 {0x0012, 0x1404},
88 {0x0013, 0x1000},
89 {0x0014, 0xa00a},
90 {0x0015, 0x0404},
91 {0x0016, 0x0404},
92 {0x0019, 0xafaf},
93 {0x001c, 0x2f2f},
94 {0x001f, 0x0000},
95 {0x0022, 0x5757},
96 {0x0023, 0x0039},
97 {0x0024, 0x000b},
98 {0x0026, 0xc0c4},
99 {0x0029, 0x8080},
100 {0x002a, 0xa0a0},
101 {0x002b, 0x0300},
102 {0x0030, 0x0000},
103 {0x003c, 0x0080},
104 {0x0044, 0x0c0c},
105 {0x0049, 0x0000},
106 {0x0061, 0x0000},
107 {0x0062, 0x0000},
108 {0x0063, 0x003f},
109 {0x0064, 0x0000},
110 {0x0065, 0x0000},
111 {0x0066, 0x0030},
112 {0x0067, 0x0000},
113 {0x006b, 0x0000},
114 {0x006c, 0x0000},
115 {0x006d, 0x2200},
116 {0x006e, 0x0a10},
117 {0x0070, 0x8000},
118 {0x0071, 0x8000},
119 {0x0073, 0x0000},
120 {0x0074, 0x0000},
121 {0x0075, 0x0002},
122 {0x0076, 0x0001},
123 {0x0079, 0x0000},
124 {0x007a, 0x0000},
125 {0x007b, 0x0000},
126 {0x007c, 0x0100},
127 {0x007e, 0x0000},
128 {0x0080, 0x0000},
129 {0x0081, 0x0000},
130 {0x0082, 0x0000},
131 {0x0083, 0x0000},
132 {0x0084, 0x0000},
133 {0x0085, 0x0000},
134 {0x0086, 0x0005},
135 {0x0087, 0x0000},
136 {0x0088, 0x0000},
137 {0x008c, 0x0003},
138 {0x008d, 0x0000},
139 {0x008e, 0x0060},
140 {0x008f, 0x1000},
141 {0x0091, 0x0c26},
142 {0x0092, 0x0073},
143 {0x0093, 0x0000},
144 {0x0094, 0x0080},
145 {0x0098, 0x0000},
146 {0x009a, 0x0000},
147 {0x009b, 0x0000},
148 {0x009c, 0x0000},
149 {0x009d, 0x0000},
150 {0x009e, 0x100c},
151 {0x009f, 0x0000},
152 {0x00a0, 0x0000},
153 {0x00a3, 0x0002},
154 {0x00a4, 0x0001},
155 {0x00ae, 0x2040},
156 {0x00af, 0x0000},
157 {0x00b6, 0x0000},
158 {0x00b7, 0x0000},
159 {0x00b8, 0x0000},
160 {0x00b9, 0x0002},
161 {0x00be, 0x0000},
162 {0x00c0, 0x0160},
163 {0x00c1, 0x82a0},
164 {0x00c2, 0x0000},
165 {0x00d0, 0x0000},
166 {0x00d1, 0x2244},
167 {0x00d2, 0x3300},
168 {0x00d3, 0x2200},
169 {0x00d4, 0x0000},
170 {0x00d9, 0x0009},
171 {0x00da, 0x0000},
172 {0x00db, 0x0000},
173 {0x00dc, 0x00c0},
174 {0x00dd, 0x2220},
175 {0x00de, 0x3131},
176 {0x00df, 0x3131},
177 {0x00e0, 0x3131},
178 {0x00e2, 0x0000},
179 {0x00e3, 0x4000},
180 {0x00e4, 0x0aa0},
181 {0x00e5, 0x3131},
182 {0x00e6, 0x3131},
183 {0x00e7, 0x3131},
184 {0x00e8, 0x3131},
185 {0x00ea, 0xb320},
186 {0x00eb, 0x0000},
187 {0x00f0, 0x0000},
188 {0x00f1, 0x00d0},
189 {0x00f2, 0x00d0},
190 {0x00f6, 0x0000},
191 {0x00fa, 0x0000},
192 {0x00fb, 0x0000},
193 {0x00fc, 0x0000},
194 {0x00fd, 0x0000},
195 {0x00fe, 0x10ec},
196 {0x00ff, 0x6530},
197 {0x0100, 0xa0a0},
198 {0x010b, 0x0000},
199 {0x010c, 0xae00},
200 {0x010d, 0xaaa0},
201 {0x010e, 0x8aa2},
202 {0x010f, 0x02a2},
203 {0x0110, 0xc000},
204 {0x0111, 0x04a2},
205 {0x0112, 0x2800},
206 {0x0113, 0x0000},
207 {0x0117, 0x0100},
208 {0x0125, 0x0410},
209 {0x0132, 0x6026},
210 {0x0136, 0x5555},
211 {0x0138, 0x3700},
212 {0x013a, 0x2000},
213 {0x013b, 0x2000},
214 {0x013c, 0x2005},
215 {0x013f, 0x0000},
216 {0x0142, 0x0000},
217 {0x0145, 0x0002},
218 {0x0146, 0x0000},
219 {0x0147, 0x0000},
220 {0x0148, 0x0000},
221 {0x0149, 0x0000},
222 {0x0150, 0x79a1},
223 {0x0151, 0x0000},
224 {0x0160, 0x4ec0},
225 {0x0161, 0x0080},
226 {0x0162, 0x0200},
227 {0x0163, 0x0800},
228 {0x0164, 0x0000},
229 {0x0165, 0x0000},
230 {0x0166, 0x0000},
231 {0x0167, 0x000f},
232 {0x0168, 0x000f},
233 {0x0169, 0x0021},
234 {0x0190, 0x413d},
235 {0x0194, 0x0000},
236 {0x0195, 0x0000},
237 {0x0197, 0x0022},
238 {0x0198, 0x0000},
239 {0x0199, 0x0000},
240 {0x01af, 0x0000},
241 {0x01b0, 0x0400},
242 {0x01b1, 0x0000},
243 {0x01b2, 0x0000},
244 {0x01b3, 0x0000},
245 {0x01b4, 0x0000},
246 {0x01b5, 0x0000},
247 {0x01b6, 0x01c3},
248 {0x01b7, 0x02a0},
249 {0x01b8, 0x03e9},
250 {0x01b9, 0x1389},
251 {0x01ba, 0xc351},
252 {0x01bb, 0x0009},
253 {0x01bc, 0x0018},
254 {0x01bd, 0x002a},
255 {0x01be, 0x004c},
256 {0x01bf, 0x0097},
257 {0x01c0, 0x433d},
258 {0x01c2, 0x0000},
259 {0x01c3, 0x0000},
260 {0x01c4, 0x0000},
261 {0x01c5, 0x0000},
262 {0x01c6, 0x0000},
263 {0x01c7, 0x0000},
264 {0x01c8, 0x40af},
265 {0x01c9, 0x0702},
266 {0x01ca, 0x0000},
267 {0x01cb, 0x0000},
268 {0x01cc, 0x5757},
269 {0x01cd, 0x5757},
270 {0x01ce, 0x5757},
271 {0x01cf, 0x5757},
272 {0x01d0, 0x5757},
273 {0x01d1, 0x5757},
274 {0x01d2, 0x5757},
275 {0x01d3, 0x5757},
276 {0x01d4, 0x5757},
277 {0x01d5, 0x5757},
278 {0x01d6, 0x0000},
279 {0x01d7, 0x0008},
280 {0x01d8, 0x0029},
281 {0x01d9, 0x3333},
282 {0x01da, 0x0000},
283 {0x01db, 0x0004},
284 {0x01dc, 0x0000},
285 {0x01de, 0x7c00},
286 {0x01df, 0x0320},
287 {0x01e0, 0x06a1},
288 {0x01e1, 0x0000},
289 {0x01e2, 0x0000},
290 {0x01e3, 0x0000},
291 {0x01e4, 0x0000},
292 {0x01e6, 0x0001},
293 {0x01e7, 0x0000},
294 {0x01e8, 0x0000},
295 {0x01ea, 0x0000},
296 {0x01eb, 0x0000},
297 {0x01ec, 0x0000},
298 {0x01ed, 0x0000},
299 {0x01ee, 0x0000},
300 {0x01ef, 0x0000},
301 {0x01f0, 0x0000},
302 {0x01f1, 0x0000},
303 {0x01f2, 0x0000},
304 {0x01f3, 0x0000},
305 {0x01f4, 0x0000},
306 {0x0210, 0x6297},
307 {0x0211, 0xa005},
308 {0x0212, 0x824c},
309 {0x0213, 0xf7ff},
310 {0x0214, 0xf24c},
311 {0x0215, 0x0102},
312 {0x0216, 0x00a3},
313 {0x0217, 0x0048},
314 {0x0218, 0xa2c0},
315 {0x0219, 0x0400},
316 {0x021a, 0x00c8},
317 {0x021b, 0x00c0},
318 {0x021c, 0x0000},
319 {0x0250, 0x4500},
320 {0x0251, 0x40b3},
321 {0x0252, 0x0000},
322 {0x0253, 0x0000},
323 {0x0254, 0x0000},
324 {0x0255, 0x0000},
325 {0x0256, 0x0000},
326 {0x0257, 0x0000},
327 {0x0258, 0x0000},
328 {0x0259, 0x0000},
329 {0x025a, 0x0005},
330 {0x0270, 0x0000},
331 {0x02ff, 0x0110},
332 {0x0300, 0x001f},
333 {0x0301, 0x032c},
334 {0x0302, 0x5f21},
335 {0x0303, 0x4000},
336 {0x0304, 0x4000},
337 {0x0305, 0x06d5},
338 {0x0306, 0x8000},
339 {0x0307, 0x0700},
340 {0x0310, 0x4560},
341 {0x0311, 0xa4a8},
342 {0x0312, 0x7418},
343 {0x0313, 0x0000},
344 {0x0314, 0x0006},
345 {0x0315, 0xffff},
346 {0x0316, 0xc400},
347 {0x0317, 0x0000},
348 {0x03c0, 0x7e00},
349 {0x03c1, 0x8000},
350 {0x03c2, 0x8000},
351 {0x03c3, 0x8000},
352 {0x03c4, 0x8000},
353 {0x03c5, 0x8000},
354 {0x03c6, 0x8000},
355 {0x03c7, 0x8000},
356 {0x03c8, 0x8000},
357 {0x03c9, 0x8000},
358 {0x03ca, 0x8000},
359 {0x03cb, 0x8000},
360 {0x03cc, 0x8000},
361 {0x03d0, 0x0000},
362 {0x03d1, 0x0000},
363 {0x03d2, 0x0000},
364 {0x03d3, 0x0000},
365 {0x03d4, 0x2000},
366 {0x03d5, 0x2000},
367 {0x03d6, 0x0000},
368 {0x03d7, 0x0000},
369 {0x03d8, 0x2000},
370 {0x03d9, 0x2000},
371 {0x03da, 0x2000},
372 {0x03db, 0x2000},
373 {0x03dc, 0x0000},
374 {0x03dd, 0x0000},
375 {0x03de, 0x0000},
376 {0x03df, 0x2000},
377 {0x03e0, 0x0000},
378 {0x03e1, 0x0000},
379 {0x03e2, 0x0000},
380 {0x03e3, 0x0000},
381 {0x03e4, 0x0000},
382 {0x03e5, 0x0000},
383 {0x03e6, 0x0000},
384 {0x03e7, 0x0000},
385 {0x03e8, 0x0000},
386 {0x03e9, 0x0000},
387 {0x03ea, 0x0000},
388 {0x03eb, 0x0000},
389 {0x03ec, 0x0000},
390 {0x03ed, 0x0000},
391 {0x03ee, 0x0000},
392 {0x03ef, 0x0000},
393 {0x03f0, 0x0800},
394 {0x03f1, 0x0800},
395 {0x03f2, 0x0800},
396 {0x03f3, 0x0800},
397 };
398
rt5682_volatile_register(struct device * dev,unsigned int reg)399 static bool rt5682_volatile_register(struct device *dev, unsigned int reg)
400 {
401 switch (reg) {
402 case RT5682_RESET:
403 case RT5682_CBJ_CTRL_2:
404 case RT5682_INT_ST_1:
405 case RT5682_4BTN_IL_CMD_1:
406 case RT5682_AJD1_CTRL:
407 case RT5682_HP_CALIB_CTRL_1:
408 case RT5682_DEVICE_ID:
409 case RT5682_I2C_MODE:
410 case RT5682_HP_CALIB_CTRL_10:
411 case RT5682_EFUSE_CTRL_2:
412 case RT5682_JD_TOP_VC_VTRL:
413 case RT5682_HP_IMP_SENS_CTRL_19:
414 case RT5682_IL_CMD_1:
415 case RT5682_SAR_IL_CMD_2:
416 case RT5682_SAR_IL_CMD_4:
417 case RT5682_SAR_IL_CMD_10:
418 case RT5682_SAR_IL_CMD_11:
419 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
420 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
421 return true;
422 default:
423 return false;
424 }
425 }
426
rt5682_readable_register(struct device * dev,unsigned int reg)427 static bool rt5682_readable_register(struct device *dev, unsigned int reg)
428 {
429 switch (reg) {
430 case RT5682_RESET:
431 case RT5682_VERSION_ID:
432 case RT5682_VENDOR_ID:
433 case RT5682_DEVICE_ID:
434 case RT5682_HP_CTRL_1:
435 case RT5682_HP_CTRL_2:
436 case RT5682_HPL_GAIN:
437 case RT5682_HPR_GAIN:
438 case RT5682_I2C_CTRL:
439 case RT5682_CBJ_BST_CTRL:
440 case RT5682_CBJ_CTRL_1:
441 case RT5682_CBJ_CTRL_2:
442 case RT5682_CBJ_CTRL_3:
443 case RT5682_CBJ_CTRL_4:
444 case RT5682_CBJ_CTRL_5:
445 case RT5682_CBJ_CTRL_6:
446 case RT5682_CBJ_CTRL_7:
447 case RT5682_DAC1_DIG_VOL:
448 case RT5682_STO1_ADC_DIG_VOL:
449 case RT5682_STO1_ADC_BOOST:
450 case RT5682_HP_IMP_GAIN_1:
451 case RT5682_HP_IMP_GAIN_2:
452 case RT5682_SIDETONE_CTRL:
453 case RT5682_STO1_ADC_MIXER:
454 case RT5682_AD_DA_MIXER:
455 case RT5682_STO1_DAC_MIXER:
456 case RT5682_A_DAC1_MUX:
457 case RT5682_DIG_INF2_DATA:
458 case RT5682_REC_MIXER:
459 case RT5682_CAL_REC:
460 case RT5682_ALC_BACK_GAIN:
461 case RT5682_PWR_DIG_1:
462 case RT5682_PWR_DIG_2:
463 case RT5682_PWR_ANLG_1:
464 case RT5682_PWR_ANLG_2:
465 case RT5682_PWR_ANLG_3:
466 case RT5682_PWR_MIXER:
467 case RT5682_PWR_VOL:
468 case RT5682_CLK_DET:
469 case RT5682_RESET_LPF_CTRL:
470 case RT5682_RESET_HPF_CTRL:
471 case RT5682_DMIC_CTRL_1:
472 case RT5682_I2S1_SDP:
473 case RT5682_I2S2_SDP:
474 case RT5682_ADDA_CLK_1:
475 case RT5682_ADDA_CLK_2:
476 case RT5682_I2S1_F_DIV_CTRL_1:
477 case RT5682_I2S1_F_DIV_CTRL_2:
478 case RT5682_TDM_CTRL:
479 case RT5682_TDM_ADDA_CTRL_1:
480 case RT5682_TDM_ADDA_CTRL_2:
481 case RT5682_DATA_SEL_CTRL_1:
482 case RT5682_TDM_TCON_CTRL:
483 case RT5682_GLB_CLK:
484 case RT5682_PLL_CTRL_1:
485 case RT5682_PLL_CTRL_2:
486 case RT5682_PLL_TRACK_1:
487 case RT5682_PLL_TRACK_2:
488 case RT5682_PLL_TRACK_3:
489 case RT5682_PLL_TRACK_4:
490 case RT5682_PLL_TRACK_5:
491 case RT5682_PLL_TRACK_6:
492 case RT5682_PLL_TRACK_11:
493 case RT5682_SDW_REF_CLK:
494 case RT5682_DEPOP_1:
495 case RT5682_DEPOP_2:
496 case RT5682_HP_CHARGE_PUMP_1:
497 case RT5682_HP_CHARGE_PUMP_2:
498 case RT5682_MICBIAS_1:
499 case RT5682_MICBIAS_2:
500 case RT5682_PLL_TRACK_12:
501 case RT5682_PLL_TRACK_14:
502 case RT5682_PLL2_CTRL_1:
503 case RT5682_PLL2_CTRL_2:
504 case RT5682_PLL2_CTRL_3:
505 case RT5682_PLL2_CTRL_4:
506 case RT5682_RC_CLK_CTRL:
507 case RT5682_I2S_M_CLK_CTRL_1:
508 case RT5682_I2S2_F_DIV_CTRL_1:
509 case RT5682_I2S2_F_DIV_CTRL_2:
510 case RT5682_EQ_CTRL_1:
511 case RT5682_EQ_CTRL_2:
512 case RT5682_IRQ_CTRL_1:
513 case RT5682_IRQ_CTRL_2:
514 case RT5682_IRQ_CTRL_3:
515 case RT5682_IRQ_CTRL_4:
516 case RT5682_INT_ST_1:
517 case RT5682_GPIO_CTRL_1:
518 case RT5682_GPIO_CTRL_2:
519 case RT5682_GPIO_CTRL_3:
520 case RT5682_HP_AMP_DET_CTRL_1:
521 case RT5682_HP_AMP_DET_CTRL_2:
522 case RT5682_MID_HP_AMP_DET:
523 case RT5682_LOW_HP_AMP_DET:
524 case RT5682_DELAY_BUF_CTRL:
525 case RT5682_SV_ZCD_1:
526 case RT5682_SV_ZCD_2:
527 case RT5682_IL_CMD_1:
528 case RT5682_IL_CMD_2:
529 case RT5682_IL_CMD_3:
530 case RT5682_IL_CMD_4:
531 case RT5682_IL_CMD_5:
532 case RT5682_IL_CMD_6:
533 case RT5682_4BTN_IL_CMD_1:
534 case RT5682_4BTN_IL_CMD_2:
535 case RT5682_4BTN_IL_CMD_3:
536 case RT5682_4BTN_IL_CMD_4:
537 case RT5682_4BTN_IL_CMD_5:
538 case RT5682_4BTN_IL_CMD_6:
539 case RT5682_4BTN_IL_CMD_7:
540 case RT5682_ADC_STO1_HP_CTRL_1:
541 case RT5682_ADC_STO1_HP_CTRL_2:
542 case RT5682_AJD1_CTRL:
543 case RT5682_JD1_THD:
544 case RT5682_JD2_THD:
545 case RT5682_JD_CTRL_1:
546 case RT5682_DUMMY_1:
547 case RT5682_DUMMY_2:
548 case RT5682_DUMMY_3:
549 case RT5682_DAC_ADC_DIG_VOL1:
550 case RT5682_BIAS_CUR_CTRL_2:
551 case RT5682_BIAS_CUR_CTRL_3:
552 case RT5682_BIAS_CUR_CTRL_4:
553 case RT5682_BIAS_CUR_CTRL_5:
554 case RT5682_BIAS_CUR_CTRL_6:
555 case RT5682_BIAS_CUR_CTRL_7:
556 case RT5682_BIAS_CUR_CTRL_8:
557 case RT5682_BIAS_CUR_CTRL_9:
558 case RT5682_BIAS_CUR_CTRL_10:
559 case RT5682_VREF_REC_OP_FB_CAP_CTRL:
560 case RT5682_CHARGE_PUMP_1:
561 case RT5682_DIG_IN_CTRL_1:
562 case RT5682_PAD_DRIVING_CTRL:
563 case RT5682_SOFT_RAMP_DEPOP:
564 case RT5682_CHOP_DAC:
565 case RT5682_CHOP_ADC:
566 case RT5682_CALIB_ADC_CTRL:
567 case RT5682_VOL_TEST:
568 case RT5682_SPKVDD_DET_STA:
569 case RT5682_TEST_MODE_CTRL_1:
570 case RT5682_TEST_MODE_CTRL_2:
571 case RT5682_TEST_MODE_CTRL_3:
572 case RT5682_TEST_MODE_CTRL_4:
573 case RT5682_TEST_MODE_CTRL_5:
574 case RT5682_PLL1_INTERNAL:
575 case RT5682_PLL2_INTERNAL:
576 case RT5682_STO_NG2_CTRL_1:
577 case RT5682_STO_NG2_CTRL_2:
578 case RT5682_STO_NG2_CTRL_3:
579 case RT5682_STO_NG2_CTRL_4:
580 case RT5682_STO_NG2_CTRL_5:
581 case RT5682_STO_NG2_CTRL_6:
582 case RT5682_STO_NG2_CTRL_7:
583 case RT5682_STO_NG2_CTRL_8:
584 case RT5682_STO_NG2_CTRL_9:
585 case RT5682_STO_NG2_CTRL_10:
586 case RT5682_STO1_DAC_SIL_DET:
587 case RT5682_SIL_PSV_CTRL1:
588 case RT5682_SIL_PSV_CTRL2:
589 case RT5682_SIL_PSV_CTRL3:
590 case RT5682_SIL_PSV_CTRL4:
591 case RT5682_SIL_PSV_CTRL5:
592 case RT5682_HP_IMP_SENS_CTRL_01:
593 case RT5682_HP_IMP_SENS_CTRL_02:
594 case RT5682_HP_IMP_SENS_CTRL_03:
595 case RT5682_HP_IMP_SENS_CTRL_04:
596 case RT5682_HP_IMP_SENS_CTRL_05:
597 case RT5682_HP_IMP_SENS_CTRL_06:
598 case RT5682_HP_IMP_SENS_CTRL_07:
599 case RT5682_HP_IMP_SENS_CTRL_08:
600 case RT5682_HP_IMP_SENS_CTRL_09:
601 case RT5682_HP_IMP_SENS_CTRL_10:
602 case RT5682_HP_IMP_SENS_CTRL_11:
603 case RT5682_HP_IMP_SENS_CTRL_12:
604 case RT5682_HP_IMP_SENS_CTRL_13:
605 case RT5682_HP_IMP_SENS_CTRL_14:
606 case RT5682_HP_IMP_SENS_CTRL_15:
607 case RT5682_HP_IMP_SENS_CTRL_16:
608 case RT5682_HP_IMP_SENS_CTRL_17:
609 case RT5682_HP_IMP_SENS_CTRL_18:
610 case RT5682_HP_IMP_SENS_CTRL_19:
611 case RT5682_HP_IMP_SENS_CTRL_20:
612 case RT5682_HP_IMP_SENS_CTRL_21:
613 case RT5682_HP_IMP_SENS_CTRL_22:
614 case RT5682_HP_IMP_SENS_CTRL_23:
615 case RT5682_HP_IMP_SENS_CTRL_24:
616 case RT5682_HP_IMP_SENS_CTRL_25:
617 case RT5682_HP_IMP_SENS_CTRL_26:
618 case RT5682_HP_IMP_SENS_CTRL_27:
619 case RT5682_HP_IMP_SENS_CTRL_28:
620 case RT5682_HP_IMP_SENS_CTRL_29:
621 case RT5682_HP_IMP_SENS_CTRL_30:
622 case RT5682_HP_IMP_SENS_CTRL_31:
623 case RT5682_HP_IMP_SENS_CTRL_32:
624 case RT5682_HP_IMP_SENS_CTRL_33:
625 case RT5682_HP_IMP_SENS_CTRL_34:
626 case RT5682_HP_IMP_SENS_CTRL_35:
627 case RT5682_HP_IMP_SENS_CTRL_36:
628 case RT5682_HP_IMP_SENS_CTRL_37:
629 case RT5682_HP_IMP_SENS_CTRL_38:
630 case RT5682_HP_IMP_SENS_CTRL_39:
631 case RT5682_HP_IMP_SENS_CTRL_40:
632 case RT5682_HP_IMP_SENS_CTRL_41:
633 case RT5682_HP_IMP_SENS_CTRL_42:
634 case RT5682_HP_IMP_SENS_CTRL_43:
635 case RT5682_HP_LOGIC_CTRL_1:
636 case RT5682_HP_LOGIC_CTRL_2:
637 case RT5682_HP_LOGIC_CTRL_3:
638 case RT5682_HP_CALIB_CTRL_1:
639 case RT5682_HP_CALIB_CTRL_2:
640 case RT5682_HP_CALIB_CTRL_3:
641 case RT5682_HP_CALIB_CTRL_4:
642 case RT5682_HP_CALIB_CTRL_5:
643 case RT5682_HP_CALIB_CTRL_6:
644 case RT5682_HP_CALIB_CTRL_7:
645 case RT5682_HP_CALIB_CTRL_9:
646 case RT5682_HP_CALIB_CTRL_10:
647 case RT5682_HP_CALIB_CTRL_11:
648 case RT5682_HP_CALIB_STA_1:
649 case RT5682_HP_CALIB_STA_2:
650 case RT5682_HP_CALIB_STA_3:
651 case RT5682_HP_CALIB_STA_4:
652 case RT5682_HP_CALIB_STA_5:
653 case RT5682_HP_CALIB_STA_6:
654 case RT5682_HP_CALIB_STA_7:
655 case RT5682_HP_CALIB_STA_8:
656 case RT5682_HP_CALIB_STA_9:
657 case RT5682_HP_CALIB_STA_10:
658 case RT5682_HP_CALIB_STA_11:
659 case RT5682_SAR_IL_CMD_1:
660 case RT5682_SAR_IL_CMD_2:
661 case RT5682_SAR_IL_CMD_3:
662 case RT5682_SAR_IL_CMD_4:
663 case RT5682_SAR_IL_CMD_5:
664 case RT5682_SAR_IL_CMD_6:
665 case RT5682_SAR_IL_CMD_7:
666 case RT5682_SAR_IL_CMD_8:
667 case RT5682_SAR_IL_CMD_9:
668 case RT5682_SAR_IL_CMD_10:
669 case RT5682_SAR_IL_CMD_11:
670 case RT5682_SAR_IL_CMD_12:
671 case RT5682_SAR_IL_CMD_13:
672 case RT5682_EFUSE_CTRL_1:
673 case RT5682_EFUSE_CTRL_2:
674 case RT5682_EFUSE_CTRL_3:
675 case RT5682_EFUSE_CTRL_4:
676 case RT5682_EFUSE_CTRL_5:
677 case RT5682_EFUSE_CTRL_6:
678 case RT5682_EFUSE_CTRL_7:
679 case RT5682_EFUSE_CTRL_8:
680 case RT5682_EFUSE_CTRL_9:
681 case RT5682_EFUSE_CTRL_10:
682 case RT5682_EFUSE_CTRL_11:
683 case RT5682_JD_TOP_VC_VTRL:
684 case RT5682_DRC1_CTRL_0:
685 case RT5682_DRC1_CTRL_1:
686 case RT5682_DRC1_CTRL_2:
687 case RT5682_DRC1_CTRL_3:
688 case RT5682_DRC1_CTRL_4:
689 case RT5682_DRC1_CTRL_5:
690 case RT5682_DRC1_CTRL_6:
691 case RT5682_DRC1_HARD_LMT_CTRL_1:
692 case RT5682_DRC1_HARD_LMT_CTRL_2:
693 case RT5682_DRC1_PRIV_1:
694 case RT5682_DRC1_PRIV_2:
695 case RT5682_DRC1_PRIV_3:
696 case RT5682_DRC1_PRIV_4:
697 case RT5682_DRC1_PRIV_5:
698 case RT5682_DRC1_PRIV_6:
699 case RT5682_DRC1_PRIV_7:
700 case RT5682_DRC1_PRIV_8:
701 case RT5682_EQ_AUTO_RCV_CTRL1:
702 case RT5682_EQ_AUTO_RCV_CTRL2:
703 case RT5682_EQ_AUTO_RCV_CTRL3:
704 case RT5682_EQ_AUTO_RCV_CTRL4:
705 case RT5682_EQ_AUTO_RCV_CTRL5:
706 case RT5682_EQ_AUTO_RCV_CTRL6:
707 case RT5682_EQ_AUTO_RCV_CTRL7:
708 case RT5682_EQ_AUTO_RCV_CTRL8:
709 case RT5682_EQ_AUTO_RCV_CTRL9:
710 case RT5682_EQ_AUTO_RCV_CTRL10:
711 case RT5682_EQ_AUTO_RCV_CTRL11:
712 case RT5682_EQ_AUTO_RCV_CTRL12:
713 case RT5682_EQ_AUTO_RCV_CTRL13:
714 case RT5682_ADC_L_EQ_LPF1_A1:
715 case RT5682_R_EQ_LPF1_A1:
716 case RT5682_L_EQ_LPF1_H0:
717 case RT5682_R_EQ_LPF1_H0:
718 case RT5682_L_EQ_BPF1_A1:
719 case RT5682_R_EQ_BPF1_A1:
720 case RT5682_L_EQ_BPF1_A2:
721 case RT5682_R_EQ_BPF1_A2:
722 case RT5682_L_EQ_BPF1_H0:
723 case RT5682_R_EQ_BPF1_H0:
724 case RT5682_L_EQ_BPF2_A1:
725 case RT5682_R_EQ_BPF2_A1:
726 case RT5682_L_EQ_BPF2_A2:
727 case RT5682_R_EQ_BPF2_A2:
728 case RT5682_L_EQ_BPF2_H0:
729 case RT5682_R_EQ_BPF2_H0:
730 case RT5682_L_EQ_BPF3_A1:
731 case RT5682_R_EQ_BPF3_A1:
732 case RT5682_L_EQ_BPF3_A2:
733 case RT5682_R_EQ_BPF3_A2:
734 case RT5682_L_EQ_BPF3_H0:
735 case RT5682_R_EQ_BPF3_H0:
736 case RT5682_L_EQ_BPF4_A1:
737 case RT5682_R_EQ_BPF4_A1:
738 case RT5682_L_EQ_BPF4_A2:
739 case RT5682_R_EQ_BPF4_A2:
740 case RT5682_L_EQ_BPF4_H0:
741 case RT5682_R_EQ_BPF4_H0:
742 case RT5682_L_EQ_HPF1_A1:
743 case RT5682_R_EQ_HPF1_A1:
744 case RT5682_L_EQ_HPF1_H0:
745 case RT5682_R_EQ_HPF1_H0:
746 case RT5682_L_EQ_PRE_VOL:
747 case RT5682_R_EQ_PRE_VOL:
748 case RT5682_L_EQ_POST_VOL:
749 case RT5682_R_EQ_POST_VOL:
750 case RT5682_I2C_MODE:
751 return true;
752 default:
753 return false;
754 }
755 }
756
757 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
758 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
759 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
760
761 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
762 static const DECLARE_TLV_DB_RANGE(bst_tlv,
763 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
764 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
765 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
766 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
767 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
768 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
769 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
770 );
771
772 /* Interface data select */
773 static const char * const rt5682_data_select[] = {
774 "L/R", "R/L", "L/L", "R/R"
775 };
776
777 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
778 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
779
780 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
781 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
782
783 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
784 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
785
786 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
787 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
788
789 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
790 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
791
792 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
793 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
794
795 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
796 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
797
798 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
799 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
800
801 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
802 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
803
804 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
805 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
806
rt5682_reset(struct regmap * regmap)807 static void rt5682_reset(struct regmap *regmap)
808 {
809 regmap_write(regmap, RT5682_RESET, 0);
810 regmap_write(regmap, RT5682_I2C_MODE, 1);
811 }
812 /**
813 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
814 * @component: SoC audio component device.
815 * @filter_mask: mask of filters.
816 * @clk_src: clock source
817 *
818 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
819 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
820 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
821 * ASRC function will track i2s clock and generate a corresponding system clock
822 * for codec. This function provides an API to select the clock source for a
823 * set of filters specified by the mask. And the component driver will turn on
824 * ASRC for these filters if ASRC is selected as their clock source.
825 */
rt5682_sel_asrc_clk_src(struct snd_soc_component * component,unsigned int filter_mask,unsigned int clk_src)826 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
827 unsigned int filter_mask, unsigned int clk_src)
828 {
829
830 switch (clk_src) {
831 case RT5682_CLK_SEL_SYS:
832 case RT5682_CLK_SEL_I2S1_ASRC:
833 case RT5682_CLK_SEL_I2S2_ASRC:
834 break;
835
836 default:
837 return -EINVAL;
838 }
839
840 if (filter_mask & RT5682_DA_STEREO1_FILTER) {
841 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
842 RT5682_FILTER_CLK_SEL_MASK,
843 clk_src << RT5682_FILTER_CLK_SEL_SFT);
844 }
845
846 if (filter_mask & RT5682_AD_STEREO1_FILTER) {
847 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
848 RT5682_FILTER_CLK_SEL_MASK,
849 clk_src << RT5682_FILTER_CLK_SEL_SFT);
850 }
851
852 return 0;
853 }
854 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
855
rt5682_button_detect(struct snd_soc_component * component)856 static int rt5682_button_detect(struct snd_soc_component *component)
857 {
858 int btn_type, val;
859
860 val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1);
861 btn_type = val & 0xfff0;
862 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
863 pr_debug("%s btn_type=%x\n", __func__, btn_type);
864 snd_soc_component_update_bits(component,
865 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
866
867 return btn_type;
868 }
869
rt5682_enable_push_button_irq(struct snd_soc_component * component,bool enable)870 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
871 bool enable)
872 {
873 if (enable) {
874 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
875 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
876 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
877 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
878 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
879 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
880 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
881 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
882 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
883 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN);
884 } else {
885 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
886 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
887 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
888 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
889 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
890 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
891 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
892 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
893 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
894 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
895 }
896 }
897
898 /**
899 * rt5682_headset_detect - Detect headset.
900 * @component: SoC audio component device.
901 * @jack_insert: Jack insert or not.
902 *
903 * Detect whether is headset or not when jack inserted.
904 *
905 * Returns detect status.
906 */
rt5682_headset_detect(struct snd_soc_component * component,int jack_insert)907 static int rt5682_headset_detect(struct snd_soc_component *component,
908 int jack_insert)
909 {
910 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
911 unsigned int val, count;
912
913 if (jack_insert) {
914
915 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
916 RT5682_PWR_VREF2 | RT5682_PWR_MB,
917 RT5682_PWR_VREF2 | RT5682_PWR_MB);
918 snd_soc_component_update_bits(component,
919 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
920 usleep_range(15000, 20000);
921 snd_soc_component_update_bits(component,
922 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
923 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
924 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
925
926 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
927 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
928
929 count = 0;
930 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2)
931 & RT5682_JACK_TYPE_MASK;
932 while (val == 0 && count < 50) {
933 usleep_range(10000, 15000);
934 val = snd_soc_component_read32(component,
935 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
936 count++;
937 }
938
939 switch (val) {
940 case 0x1:
941 case 0x2:
942 rt5682->jack_type = SND_JACK_HEADSET;
943 rt5682_enable_push_button_irq(component, true);
944 break;
945 default:
946 rt5682->jack_type = SND_JACK_HEADPHONE;
947 }
948
949 } else {
950 rt5682_enable_push_button_irq(component, false);
951 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
952 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
953 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
954 RT5682_PWR_VREF2 | RT5682_PWR_MB, 0);
955 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
956 RT5682_PWR_CBJ, 0);
957
958 rt5682->jack_type = 0;
959 }
960
961 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
962 return rt5682->jack_type;
963 }
964
rt5682_irq(int irq,void * data)965 static irqreturn_t rt5682_irq(int irq, void *data)
966 {
967 struct rt5682_priv *rt5682 = data;
968
969 mod_delayed_work(system_power_efficient_wq,
970 &rt5682->jack_detect_work, msecs_to_jiffies(250));
971
972 return IRQ_HANDLED;
973 }
974
rt5682_jd_check_handler(struct work_struct * work)975 static void rt5682_jd_check_handler(struct work_struct *work)
976 {
977 struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv,
978 jd_check_work.work);
979
980 if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
981 & RT5682_JDH_RS_MASK) {
982 /* jack out */
983 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
984
985 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
986 SND_JACK_HEADSET |
987 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
988 SND_JACK_BTN_2 | SND_JACK_BTN_3);
989 } else {
990 schedule_delayed_work(&rt5682->jd_check_work, 500);
991 }
992 }
993
rt5682_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)994 static int rt5682_set_jack_detect(struct snd_soc_component *component,
995 struct snd_soc_jack *hs_jack, void *data)
996 {
997 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
998
999 rt5682->hs_jack = hs_jack;
1000
1001 if (!hs_jack) {
1002 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1003 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1004 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1005 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1006 return 0;
1007 }
1008
1009 switch (rt5682->pdata.jd_src) {
1010 case RT5682_JD1:
1011 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2,
1012 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
1013 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042);
1014 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3,
1015 RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
1016 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
1017 RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
1018 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1019 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1020 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1021 RT5682_POW_IRQ | RT5682_POW_JDH |
1022 RT5682_POW_ANA, RT5682_POW_IRQ |
1023 RT5682_POW_JDH | RT5682_POW_ANA);
1024 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1025 RT5682_PWR_JDH | RT5682_PWR_JDL,
1026 RT5682_PWR_JDH | RT5682_PWR_JDL);
1027 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1028 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1029 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1030 mod_delayed_work(system_power_efficient_wq,
1031 &rt5682->jack_detect_work, msecs_to_jiffies(250));
1032 break;
1033
1034 case RT5682_JD_NULL:
1035 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1036 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1037 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1038 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1039 break;
1040
1041 default:
1042 dev_warn(component->dev, "Wrong JD source\n");
1043 break;
1044 }
1045
1046 return 0;
1047 }
1048
rt5682_jack_detect_handler(struct work_struct * work)1049 static void rt5682_jack_detect_handler(struct work_struct *work)
1050 {
1051 struct rt5682_priv *rt5682 =
1052 container_of(work, struct rt5682_priv, jack_detect_work.work);
1053 int val, btn_type;
1054
1055 if (!rt5682->component || !rt5682->component->card ||
1056 !rt5682->component->card->instantiated) {
1057 /* card not yet ready, try later */
1058 mod_delayed_work(system_power_efficient_wq,
1059 &rt5682->jack_detect_work, msecs_to_jiffies(15));
1060 return;
1061 }
1062
1063 mutex_lock(&rt5682->calibrate_mutex);
1064
1065 val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
1066 & RT5682_JDH_RS_MASK;
1067 if (!val) {
1068 /* jack in */
1069 if (rt5682->jack_type == 0) {
1070 /* jack was out, report jack type */
1071 rt5682->jack_type =
1072 rt5682_headset_detect(rt5682->component, 1);
1073 } else {
1074 /* jack is already in, report button event */
1075 rt5682->jack_type = SND_JACK_HEADSET;
1076 btn_type = rt5682_button_detect(rt5682->component);
1077 /**
1078 * rt5682 can report three kinds of button behavior,
1079 * one click, double click and hold. However,
1080 * currently we will report button pressed/released
1081 * event. So all the three button behaviors are
1082 * treated as button pressed.
1083 */
1084 switch (btn_type) {
1085 case 0x8000:
1086 case 0x4000:
1087 case 0x2000:
1088 rt5682->jack_type |= SND_JACK_BTN_0;
1089 break;
1090 case 0x1000:
1091 case 0x0800:
1092 case 0x0400:
1093 rt5682->jack_type |= SND_JACK_BTN_1;
1094 break;
1095 case 0x0200:
1096 case 0x0100:
1097 case 0x0080:
1098 rt5682->jack_type |= SND_JACK_BTN_2;
1099 break;
1100 case 0x0040:
1101 case 0x0020:
1102 case 0x0010:
1103 rt5682->jack_type |= SND_JACK_BTN_3;
1104 break;
1105 case 0x0000: /* unpressed */
1106 break;
1107 default:
1108 btn_type = 0;
1109 dev_err(rt5682->component->dev,
1110 "Unexpected button code 0x%04x\n",
1111 btn_type);
1112 break;
1113 }
1114 }
1115 } else {
1116 /* jack out */
1117 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1118 }
1119
1120 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1121 SND_JACK_HEADSET |
1122 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1123 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1124
1125 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1126 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1127 schedule_delayed_work(&rt5682->jd_check_work, 0);
1128 else
1129 cancel_delayed_work_sync(&rt5682->jd_check_work);
1130
1131 mutex_unlock(&rt5682->calibrate_mutex);
1132 }
1133
1134 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1135 /* DAC Digital Volume */
1136 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1137 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 86, 0, dac_vol_tlv),
1138
1139 /* IN Boost Volume */
1140 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1141 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1142
1143 /* ADC Digital Volume Control */
1144 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1145 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1146 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1147 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1148
1149 /* ADC Boost Volume Control */
1150 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1151 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1152 3, 0, adc_bst_tlv),
1153 };
1154
1155
rt5682_div_sel(struct rt5682_priv * rt5682,int target,const int div[],int size)1156 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1157 int target, const int div[], int size)
1158 {
1159 int i;
1160
1161 if (rt5682->sysclk < target) {
1162 pr_err("sysclk rate %d is too low\n",
1163 rt5682->sysclk);
1164 return 0;
1165 }
1166
1167 for (i = 0; i < size - 1; i++) {
1168 pr_info("div[%d]=%d\n", i, div[i]);
1169 if (target * div[i] == rt5682->sysclk)
1170 return i;
1171 if (target * div[i + 1] > rt5682->sysclk) {
1172 pr_err("can't find div for sysclk %d\n",
1173 rt5682->sysclk);
1174 return i;
1175 }
1176 }
1177
1178 if (target * div[i] < rt5682->sysclk)
1179 pr_err("sysclk rate %d is too high\n",
1180 rt5682->sysclk);
1181
1182 return size - 1;
1183
1184 }
1185
1186 /**
1187 * set_dmic_clk - Set parameter of dmic.
1188 *
1189 * @w: DAPM widget.
1190 * @kcontrol: The kcontrol of this widget.
1191 * @event: Event id.
1192 *
1193 * Choose dmic clock between 1MHz and 3MHz.
1194 * It is better for clock to approximate 3MHz.
1195 */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1196 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1197 struct snd_kcontrol *kcontrol, int event)
1198 {
1199 struct snd_soc_component *component =
1200 snd_soc_dapm_to_component(w->dapm);
1201 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1202 int idx = -EINVAL;
1203 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1204
1205 idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div));
1206
1207 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1208 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1209
1210 return 0;
1211 }
1212
set_filter_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1213 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1214 struct snd_kcontrol *kcontrol, int event)
1215 {
1216 struct snd_soc_component *component =
1217 snd_soc_dapm_to_component(w->dapm);
1218 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1219 int ref, val, reg, idx = -EINVAL;
1220 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1221 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1222
1223 val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) &
1224 RT5682_GP4_PIN_MASK;
1225 if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1226 val == RT5682_GP4_PIN_ADCDAT2)
1227 ref = 256 * rt5682->lrck[RT5682_AIF2];
1228 else
1229 ref = 256 * rt5682->lrck[RT5682_AIF1];
1230
1231 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1232
1233 if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1234 reg = RT5682_PLL_TRACK_3;
1235 else
1236 reg = RT5682_PLL_TRACK_2;
1237
1238 snd_soc_component_update_bits(component, reg,
1239 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1240
1241 /* select over sample rate */
1242 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1243 if (rt5682->sysclk <= 12288000 * div_o[idx])
1244 break;
1245 }
1246
1247 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1248 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1249 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1250
1251 return 0;
1252 }
1253
is_sys_clk_from_pll1(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1254 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1255 struct snd_soc_dapm_widget *sink)
1256 {
1257 unsigned int val;
1258 struct snd_soc_component *component =
1259 snd_soc_dapm_to_component(w->dapm);
1260
1261 val = snd_soc_component_read32(component, RT5682_GLB_CLK);
1262 val &= RT5682_SCLK_SRC_MASK;
1263 if (val == RT5682_SCLK_SRC_PLL1)
1264 return 1;
1265 else
1266 return 0;
1267 }
1268
is_using_asrc(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1269 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1270 struct snd_soc_dapm_widget *sink)
1271 {
1272 unsigned int reg, shift, val;
1273 struct snd_soc_component *component =
1274 snd_soc_dapm_to_component(w->dapm);
1275
1276 switch (w->shift) {
1277 case RT5682_ADC_STO1_ASRC_SFT:
1278 reg = RT5682_PLL_TRACK_3;
1279 shift = RT5682_FILTER_CLK_SEL_SFT;
1280 break;
1281 case RT5682_DAC_STO1_ASRC_SFT:
1282 reg = RT5682_PLL_TRACK_2;
1283 shift = RT5682_FILTER_CLK_SEL_SFT;
1284 break;
1285 default:
1286 return 0;
1287 }
1288
1289 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
1290 switch (val) {
1291 case RT5682_CLK_SEL_I2S1_ASRC:
1292 case RT5682_CLK_SEL_I2S2_ASRC:
1293 return 1;
1294 default:
1295 return 0;
1296 }
1297
1298 }
1299
1300 /* Digital Mixer */
1301 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1302 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1303 RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1304 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1305 RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1306 };
1307
1308 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1309 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1310 RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1311 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1312 RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1313 };
1314
1315 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1316 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1317 RT5682_M_ADCMIX_L_SFT, 1, 1),
1318 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1319 RT5682_M_DAC1_L_SFT, 1, 1),
1320 };
1321
1322 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1323 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1324 RT5682_M_ADCMIX_R_SFT, 1, 1),
1325 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1326 RT5682_M_DAC1_R_SFT, 1, 1),
1327 };
1328
1329 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1330 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1331 RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1332 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1333 RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1334 };
1335
1336 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1337 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1338 RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1339 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1340 RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1341 };
1342
1343 /* Analog Input Mixer */
1344 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1345 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1346 RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1347 };
1348
1349 /* STO1 ADC1 Source */
1350 /* MX-26 [13] [5] */
1351 static const char * const rt5682_sto1_adc1_src[] = {
1352 "DAC MIX", "ADC"
1353 };
1354
1355 static SOC_ENUM_SINGLE_DECL(
1356 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1357 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1358
1359 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1360 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1361
1362 static SOC_ENUM_SINGLE_DECL(
1363 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1364 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1365
1366 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1367 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1368
1369 /* STO1 ADC Source */
1370 /* MX-26 [11:10] [3:2] */
1371 static const char * const rt5682_sto1_adc_src[] = {
1372 "ADC1 L", "ADC1 R"
1373 };
1374
1375 static SOC_ENUM_SINGLE_DECL(
1376 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1377 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1378
1379 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1380 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1381
1382 static SOC_ENUM_SINGLE_DECL(
1383 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1384 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1385
1386 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1387 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1388
1389 /* STO1 ADC2 Source */
1390 /* MX-26 [12] [4] */
1391 static const char * const rt5682_sto1_adc2_src[] = {
1392 "DAC MIX", "DMIC"
1393 };
1394
1395 static SOC_ENUM_SINGLE_DECL(
1396 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1397 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1398
1399 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1400 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1401
1402 static SOC_ENUM_SINGLE_DECL(
1403 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1404 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1405
1406 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1407 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1408
1409 /* MX-79 [6:4] I2S1 ADC data location */
1410 static const unsigned int rt5682_if1_adc_slot_values[] = {
1411 0,
1412 2,
1413 4,
1414 6,
1415 };
1416
1417 static const char * const rt5682_if1_adc_slot_src[] = {
1418 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1419 };
1420
1421 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1422 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1423 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1424
1425 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1426 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1427
1428 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1429 /* MX-2B [4], MX-2B [0]*/
1430 static const char * const rt5682_alg_dac1_src[] = {
1431 "Stereo1 DAC Mixer", "DAC1"
1432 };
1433
1434 static SOC_ENUM_SINGLE_DECL(
1435 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1436 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1437
1438 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1439 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1440
1441 static SOC_ENUM_SINGLE_DECL(
1442 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1443 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1444
1445 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1446 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1447
1448 /* Out Switch */
1449 static const struct snd_kcontrol_new hpol_switch =
1450 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1451 RT5682_L_MUTE_SFT, 1, 1);
1452 static const struct snd_kcontrol_new hpor_switch =
1453 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1454 RT5682_R_MUTE_SFT, 1, 1);
1455
rt5682_charge_pump_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1456 static int rt5682_charge_pump_event(struct snd_soc_dapm_widget *w,
1457 struct snd_kcontrol *kcontrol, int event)
1458 {
1459 struct snd_soc_component *component =
1460 snd_soc_dapm_to_component(w->dapm);
1461
1462 switch (event) {
1463 case SND_SOC_DAPM_PRE_PMU:
1464 snd_soc_component_update_bits(component,
1465 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
1466 break;
1467 case SND_SOC_DAPM_POST_PMD:
1468 snd_soc_component_update_bits(component,
1469 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_LV);
1470 break;
1471 default:
1472 return 0;
1473 }
1474
1475 return 0;
1476 }
1477
rt5682_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1478 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1479 struct snd_kcontrol *kcontrol, int event)
1480 {
1481 struct snd_soc_component *component =
1482 snd_soc_dapm_to_component(w->dapm);
1483
1484 switch (event) {
1485 case SND_SOC_DAPM_PRE_PMU:
1486 snd_soc_component_write(component,
1487 RT5682_HP_LOGIC_CTRL_2, 0x0012);
1488 snd_soc_component_write(component,
1489 RT5682_HP_CTRL_2, 0x6000);
1490 snd_soc_component_update_bits(component,
1491 RT5682_DEPOP_1, 0x60, 0x60);
1492 snd_soc_component_update_bits(component,
1493 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1494 break;
1495
1496 case SND_SOC_DAPM_POST_PMD:
1497 snd_soc_component_update_bits(component,
1498 RT5682_DEPOP_1, 0x60, 0x0);
1499 snd_soc_component_write(component,
1500 RT5682_HP_CTRL_2, 0x0000);
1501 snd_soc_component_update_bits(component,
1502 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1503 break;
1504
1505 default:
1506 return 0;
1507 }
1508
1509 return 0;
1510
1511 }
1512
set_dmic_power(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1513 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1514 struct snd_kcontrol *kcontrol, int event)
1515 {
1516 switch (event) {
1517 case SND_SOC_DAPM_POST_PMU:
1518 /*Add delay to avoid pop noise*/
1519 msleep(150);
1520 break;
1521
1522 default:
1523 return 0;
1524 }
1525
1526 return 0;
1527 }
1528
rt5655_set_verf(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1529 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
1530 struct snd_kcontrol *kcontrol, int event)
1531 {
1532 struct snd_soc_component *component =
1533 snd_soc_dapm_to_component(w->dapm);
1534
1535 switch (event) {
1536 case SND_SOC_DAPM_PRE_PMU:
1537 switch (w->shift) {
1538 case RT5682_PWR_VREF1_BIT:
1539 snd_soc_component_update_bits(component,
1540 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1541 break;
1542
1543 case RT5682_PWR_VREF2_BIT:
1544 snd_soc_component_update_bits(component,
1545 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1546 break;
1547
1548 default:
1549 break;
1550 }
1551 break;
1552
1553 case SND_SOC_DAPM_POST_PMU:
1554 usleep_range(15000, 20000);
1555 switch (w->shift) {
1556 case RT5682_PWR_VREF1_BIT:
1557 snd_soc_component_update_bits(component,
1558 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1559 RT5682_PWR_FV1);
1560 break;
1561
1562 case RT5682_PWR_VREF2_BIT:
1563 snd_soc_component_update_bits(component,
1564 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1565 RT5682_PWR_FV2);
1566 break;
1567
1568 default:
1569 break;
1570 }
1571 break;
1572
1573 default:
1574 return 0;
1575 }
1576
1577 return 0;
1578 }
1579
1580 static const unsigned int rt5682_adcdat_pin_values[] = {
1581 1,
1582 3,
1583 };
1584
1585 static const char * const rt5682_adcdat_pin_select[] = {
1586 "ADCDAT1",
1587 "ADCDAT2",
1588 };
1589
1590 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1591 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1592 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1593
1594 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1595 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1596
1597 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1598 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1599 0, NULL, 0),
1600 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1601 0, NULL, 0),
1602 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1603 0, NULL, 0),
1604 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1605 0, NULL, 0),
1606 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1607 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1608
1609 /* ASRC */
1610 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1611 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1612 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1613 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1614 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1615 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1616 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1617 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1618 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1619 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1620
1621 /* Input Side */
1622 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1623 0, NULL, 0),
1624 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1625 0, NULL, 0),
1626
1627 /* Input Lines */
1628 SND_SOC_DAPM_INPUT("DMIC L1"),
1629 SND_SOC_DAPM_INPUT("DMIC R1"),
1630
1631 SND_SOC_DAPM_INPUT("IN1P"),
1632
1633 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1634 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1635 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1636 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1637
1638 /* Boost */
1639 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1640 0, 0, NULL, 0),
1641
1642 /* REC Mixer */
1643 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1644 ARRAY_SIZE(rt5682_rec1_l_mix)),
1645 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1646 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1647
1648 /* ADCs */
1649 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1650 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1651
1652 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1653 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1654 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1655 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1656 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1657 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1658
1659 /* ADC Mux */
1660 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1661 &rt5682_sto1_adc1l_mux),
1662 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1663 &rt5682_sto1_adc1r_mux),
1664 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1665 &rt5682_sto1_adc2l_mux),
1666 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1667 &rt5682_sto1_adc2r_mux),
1668 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1669 &rt5682_sto1_adcl_mux),
1670 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1671 &rt5682_sto1_adcr_mux),
1672 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1673 &rt5682_if1_adc_slot_mux),
1674
1675 /* ADC Mixer */
1676 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1677 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1678 SND_SOC_DAPM_PRE_PMU),
1679 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1680 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1681 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1682 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1683 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1684 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1685 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1686 14, 1, NULL, 0),
1687
1688 /* ADC PGA */
1689 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1690
1691 /* Digital Interface */
1692 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1693 0, NULL, 0),
1694 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1695 0, NULL, 0),
1696 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1697 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1698 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1699
1700 /* Digital Interface Select */
1701 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1702 &rt5682_if1_01_adc_swap_mux),
1703 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1704 &rt5682_if1_23_adc_swap_mux),
1705 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1706 &rt5682_if1_45_adc_swap_mux),
1707 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1708 &rt5682_if1_67_adc_swap_mux),
1709 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1710 &rt5682_if2_adc_swap_mux),
1711
1712 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1713 &rt5682_adcdat_pin_ctrl),
1714
1715 /* Audio Interface */
1716 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1717 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1718 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1719 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1720 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1721
1722 /* Output Side */
1723 /* DAC mixer before sound effect */
1724 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1725 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1726 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1727 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1728
1729 /* DAC channel Mux */
1730 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1731 &rt5682_alg_dac_l1_mux),
1732 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1733 &rt5682_alg_dac_r1_mux),
1734
1735 /* DAC Mixer */
1736 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1737 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1738 SND_SOC_DAPM_PRE_PMU),
1739 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1740 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1741 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1742 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1743
1744 /* DACs */
1745 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1746 RT5682_PWR_DAC_L1_BIT, 0),
1747 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1748 RT5682_PWR_DAC_R1_BIT, 0),
1749 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1750 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1751
1752 /* HPO */
1753 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1754 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1755
1756 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1757 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1758 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1759 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1760 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1761 RT5682_PUMP_EN_SFT, 0, rt5682_charge_pump_event,
1762 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1763 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1764 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1765
1766 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1767 &hpol_switch),
1768 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1769 &hpor_switch),
1770
1771 /* CLK DET */
1772 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1773 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1774 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1775 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1776 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1777 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1778 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1779 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1780
1781 /* Output Lines */
1782 SND_SOC_DAPM_OUTPUT("HPOL"),
1783 SND_SOC_DAPM_OUTPUT("HPOR"),
1784
1785 };
1786
1787 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1788 /*PLL*/
1789 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1790 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1791
1792 /*ASRC*/
1793 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1794 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1795 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1796 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1797 {"ADC STO1 ASRC", NULL, "CLKDET"},
1798 {"DAC STO1 ASRC", NULL, "AD ASRC"},
1799 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1800 {"DAC STO1 ASRC", NULL, "CLKDET"},
1801
1802 /*Vref*/
1803 {"MICBIAS1", NULL, "Vref1"},
1804 {"MICBIAS2", NULL, "Vref1"},
1805
1806 {"CLKDET SYS", NULL, "CLKDET"},
1807
1808 {"IN1P", NULL, "LDO2"},
1809
1810 {"BST1 CBJ", NULL, "IN1P"},
1811
1812 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1813 {"RECMIX1L", NULL, "RECMIX1L Power"},
1814
1815 {"ADC1 L", NULL, "RECMIX1L"},
1816 {"ADC1 L", NULL, "ADC1 L Power"},
1817 {"ADC1 L", NULL, "ADC1 clock"},
1818
1819 {"DMIC L1", NULL, "DMIC CLK"},
1820 {"DMIC L1", NULL, "DMIC1 Power"},
1821 {"DMIC R1", NULL, "DMIC CLK"},
1822 {"DMIC R1", NULL, "DMIC1 Power"},
1823 {"DMIC CLK", NULL, "DMIC ASRC"},
1824
1825 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1826 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1827 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1828 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1829
1830 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1831 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1832 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1833 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1834
1835 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1836 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1837 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1838 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1839
1840 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1841 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1842 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1843
1844 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1845 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1846 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1847
1848 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1849
1850 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1851 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1852
1853 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1854 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1855 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1856 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1857 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1858 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1859 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1860 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1861 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1862 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1863 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1864 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1865 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1866 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1867 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1868 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1869
1870 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1871 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1872 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1873 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1874 {"IF1_ADC Mux", NULL, "I2S1"},
1875 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1876 {"AIF1TX", NULL, "ADCDAT Mux"},
1877 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1878 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1879 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1880 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1881 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1882 {"AIF2TX", NULL, "ADCDAT Mux"},
1883
1884 {"IF1 DAC1 L", NULL, "AIF1RX"},
1885 {"IF1 DAC1 L", NULL, "I2S1"},
1886 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1887 {"IF1 DAC1 R", NULL, "AIF1RX"},
1888 {"IF1 DAC1 R", NULL, "I2S1"},
1889 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1890
1891 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1892 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1893 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1894 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1895
1896 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1897 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1898
1899 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1900 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1901
1902 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1903 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1904 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1905 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1906
1907 {"DAC L1", NULL, "DAC L1 Source"},
1908 {"DAC R1", NULL, "DAC R1 Source"},
1909
1910 {"DAC L1", NULL, "DAC 1 Clock"},
1911 {"DAC R1", NULL, "DAC 1 Clock"},
1912
1913 {"HP Amp", NULL, "DAC L1"},
1914 {"HP Amp", NULL, "DAC R1"},
1915 {"HP Amp", NULL, "HP Amp L"},
1916 {"HP Amp", NULL, "HP Amp R"},
1917 {"HP Amp", NULL, "Capless"},
1918 {"HP Amp", NULL, "Charge Pump"},
1919 {"HP Amp", NULL, "CLKDET SYS"},
1920 {"HP Amp", NULL, "Vref1"},
1921 {"HPOL Playback", "Switch", "HP Amp"},
1922 {"HPOR Playback", "Switch", "HP Amp"},
1923 {"HPOL", NULL, "HPOL Playback"},
1924 {"HPOR", NULL, "HPOR Playback"},
1925 };
1926
rt5682_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1927 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1928 unsigned int rx_mask, int slots, int slot_width)
1929 {
1930 struct snd_soc_component *component = dai->component;
1931 unsigned int cl, val = 0;
1932
1933 if (tx_mask || rx_mask)
1934 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1935 RT5682_TDM_EN, RT5682_TDM_EN);
1936 else
1937 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1938 RT5682_TDM_EN, 0);
1939
1940 switch (slots) {
1941 case 4:
1942 val |= RT5682_TDM_TX_CH_4;
1943 val |= RT5682_TDM_RX_CH_4;
1944 break;
1945 case 6:
1946 val |= RT5682_TDM_TX_CH_6;
1947 val |= RT5682_TDM_RX_CH_6;
1948 break;
1949 case 8:
1950 val |= RT5682_TDM_TX_CH_8;
1951 val |= RT5682_TDM_RX_CH_8;
1952 break;
1953 case 2:
1954 break;
1955 default:
1956 return -EINVAL;
1957 }
1958
1959 snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
1960 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
1961
1962 switch (slot_width) {
1963 case 8:
1964 if (tx_mask || rx_mask)
1965 return -EINVAL;
1966 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
1967 break;
1968 case 16:
1969 val = RT5682_TDM_CL_16;
1970 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
1971 break;
1972 case 20:
1973 val = RT5682_TDM_CL_20;
1974 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
1975 break;
1976 case 24:
1977 val = RT5682_TDM_CL_24;
1978 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
1979 break;
1980 case 32:
1981 val = RT5682_TDM_CL_32;
1982 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
1983 break;
1984 default:
1985 return -EINVAL;
1986 }
1987
1988 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
1989 RT5682_TDM_CL_MASK, val);
1990 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
1991 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
1992
1993 return 0;
1994 }
1995
1996
rt5682_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1997 static int rt5682_hw_params(struct snd_pcm_substream *substream,
1998 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1999 {
2000 struct snd_soc_component *component = dai->component;
2001 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2002 unsigned int len_1 = 0, len_2 = 0;
2003 int pre_div, frame_size;
2004
2005 rt5682->lrck[dai->id] = params_rate(params);
2006 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2007
2008 frame_size = snd_soc_params_to_frame_size(params);
2009 if (frame_size < 0) {
2010 dev_err(component->dev, "Unsupported frame size: %d\n",
2011 frame_size);
2012 return -EINVAL;
2013 }
2014
2015 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2016 rt5682->lrck[dai->id], pre_div, dai->id);
2017
2018 switch (params_width(params)) {
2019 case 16:
2020 break;
2021 case 20:
2022 len_1 |= RT5682_I2S1_DL_20;
2023 len_2 |= RT5682_I2S2_DL_20;
2024 break;
2025 case 24:
2026 len_1 |= RT5682_I2S1_DL_24;
2027 len_2 |= RT5682_I2S2_DL_24;
2028 break;
2029 case 32:
2030 len_1 |= RT5682_I2S1_DL_32;
2031 len_2 |= RT5682_I2S2_DL_24;
2032 break;
2033 case 8:
2034 len_1 |= RT5682_I2S2_DL_8;
2035 len_2 |= RT5682_I2S2_DL_8;
2036 break;
2037 default:
2038 return -EINVAL;
2039 }
2040
2041 switch (dai->id) {
2042 case RT5682_AIF1:
2043 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2044 RT5682_I2S1_DL_MASK, len_1);
2045 if (rt5682->master[RT5682_AIF1]) {
2046 snd_soc_component_update_bits(component,
2047 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK,
2048 pre_div << RT5682_I2S_M_DIV_SFT);
2049 }
2050 if (params_channels(params) == 1) /* mono mode */
2051 snd_soc_component_update_bits(component,
2052 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2053 RT5682_I2S1_MONO_EN);
2054 else
2055 snd_soc_component_update_bits(component,
2056 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2057 RT5682_I2S1_MONO_DIS);
2058 break;
2059 case RT5682_AIF2:
2060 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2061 RT5682_I2S2_DL_MASK, len_2);
2062 if (rt5682->master[RT5682_AIF2]) {
2063 snd_soc_component_update_bits(component,
2064 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2065 pre_div << RT5682_I2S2_M_PD_SFT);
2066 }
2067 if (params_channels(params) == 1) /* mono mode */
2068 snd_soc_component_update_bits(component,
2069 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2070 RT5682_I2S2_MONO_EN);
2071 else
2072 snd_soc_component_update_bits(component,
2073 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2074 RT5682_I2S2_MONO_DIS);
2075 break;
2076 default:
2077 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2078 return -EINVAL;
2079 }
2080
2081 return 0;
2082 }
2083
rt5682_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)2084 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2085 {
2086 struct snd_soc_component *component = dai->component;
2087 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2088 unsigned int reg_val = 0, tdm_ctrl = 0;
2089
2090 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2091 case SND_SOC_DAIFMT_CBM_CFM:
2092 rt5682->master[dai->id] = 1;
2093 break;
2094 case SND_SOC_DAIFMT_CBS_CFS:
2095 rt5682->master[dai->id] = 0;
2096 break;
2097 default:
2098 return -EINVAL;
2099 }
2100
2101 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2102 case SND_SOC_DAIFMT_NB_NF:
2103 break;
2104 case SND_SOC_DAIFMT_IB_NF:
2105 reg_val |= RT5682_I2S_BP_INV;
2106 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2107 break;
2108 case SND_SOC_DAIFMT_NB_IF:
2109 if (dai->id == RT5682_AIF1)
2110 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2111 else
2112 return -EINVAL;
2113 break;
2114 case SND_SOC_DAIFMT_IB_IF:
2115 if (dai->id == RT5682_AIF1)
2116 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2117 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2118 else
2119 return -EINVAL;
2120 break;
2121 default:
2122 return -EINVAL;
2123 }
2124
2125 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2126 case SND_SOC_DAIFMT_I2S:
2127 break;
2128 case SND_SOC_DAIFMT_LEFT_J:
2129 reg_val |= RT5682_I2S_DF_LEFT;
2130 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2131 break;
2132 case SND_SOC_DAIFMT_DSP_A:
2133 reg_val |= RT5682_I2S_DF_PCM_A;
2134 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2135 break;
2136 case SND_SOC_DAIFMT_DSP_B:
2137 reg_val |= RT5682_I2S_DF_PCM_B;
2138 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2139 break;
2140 default:
2141 return -EINVAL;
2142 }
2143
2144 switch (dai->id) {
2145 case RT5682_AIF1:
2146 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2147 RT5682_I2S_DF_MASK, reg_val);
2148 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2149 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2150 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2151 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2152 tdm_ctrl | rt5682->master[dai->id]);
2153 break;
2154 case RT5682_AIF2:
2155 if (rt5682->master[dai->id] == 0)
2156 reg_val |= RT5682_I2S2_MS_S;
2157 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2158 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2159 RT5682_I2S_DF_MASK, reg_val);
2160 break;
2161 default:
2162 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2163 return -EINVAL;
2164 }
2165 return 0;
2166 }
2167
rt5682_set_component_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)2168 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2169 int clk_id, int source, unsigned int freq, int dir)
2170 {
2171 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2172 unsigned int reg_val = 0, src = 0;
2173
2174 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2175 return 0;
2176
2177 switch (clk_id) {
2178 case RT5682_SCLK_S_MCLK:
2179 reg_val |= RT5682_SCLK_SRC_MCLK;
2180 src = RT5682_CLK_SRC_MCLK;
2181 break;
2182 case RT5682_SCLK_S_PLL1:
2183 reg_val |= RT5682_SCLK_SRC_PLL1;
2184 src = RT5682_CLK_SRC_PLL1;
2185 break;
2186 case RT5682_SCLK_S_PLL2:
2187 reg_val |= RT5682_SCLK_SRC_PLL2;
2188 src = RT5682_CLK_SRC_PLL2;
2189 break;
2190 case RT5682_SCLK_S_RCCLK:
2191 reg_val |= RT5682_SCLK_SRC_RCCLK;
2192 src = RT5682_CLK_SRC_RCCLK;
2193 break;
2194 default:
2195 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2196 return -EINVAL;
2197 }
2198 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2199 RT5682_SCLK_SRC_MASK, reg_val);
2200
2201 if (rt5682->master[RT5682_AIF2]) {
2202 snd_soc_component_update_bits(component,
2203 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2204 src << RT5682_I2S2_SRC_SFT);
2205 }
2206
2207 rt5682->sysclk = freq;
2208 rt5682->sysclk_src = clk_id;
2209
2210 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2211 freq, clk_id);
2212
2213 return 0;
2214 }
2215
rt5682_set_component_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)2216 static int rt5682_set_component_pll(struct snd_soc_component *component,
2217 int pll_id, int source, unsigned int freq_in,
2218 unsigned int freq_out)
2219 {
2220 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2221 struct rl6231_pll_code pll_code;
2222 int ret;
2223
2224 if (source == rt5682->pll_src && freq_in == rt5682->pll_in &&
2225 freq_out == rt5682->pll_out)
2226 return 0;
2227
2228 if (!freq_in || !freq_out) {
2229 dev_dbg(component->dev, "PLL disabled\n");
2230
2231 rt5682->pll_in = 0;
2232 rt5682->pll_out = 0;
2233 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2234 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2235 return 0;
2236 }
2237
2238 switch (source) {
2239 case RT5682_PLL1_S_MCLK:
2240 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2241 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK);
2242 break;
2243 case RT5682_PLL1_S_BCLK1:
2244 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2245 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1);
2246 break;
2247 default:
2248 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2249 return -EINVAL;
2250 }
2251
2252 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2253 if (ret < 0) {
2254 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2255 return ret;
2256 }
2257
2258 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2259 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2260 pll_code.n_code, pll_code.k_code);
2261
2262 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2263 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2264 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2265 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2266 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2267
2268 rt5682->pll_in = freq_in;
2269 rt5682->pll_out = freq_out;
2270 rt5682->pll_src = source;
2271
2272 return 0;
2273 }
2274
rt5682_set_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)2275 static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2276 {
2277 struct snd_soc_component *component = dai->component;
2278 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2279
2280 rt5682->bclk[dai->id] = ratio;
2281
2282 switch (ratio) {
2283 case 64:
2284 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2285 RT5682_I2S2_BCLK_MS2_MASK,
2286 RT5682_I2S2_BCLK_MS2_64);
2287 break;
2288 case 32:
2289 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2290 RT5682_I2S2_BCLK_MS2_MASK,
2291 RT5682_I2S2_BCLK_MS2_32);
2292 break;
2293 default:
2294 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
2295 return -EINVAL;
2296 }
2297
2298 return 0;
2299 }
2300
rt5682_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)2301 static int rt5682_set_bias_level(struct snd_soc_component *component,
2302 enum snd_soc_bias_level level)
2303 {
2304 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2305
2306 switch (level) {
2307 case SND_SOC_BIAS_PREPARE:
2308 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2309 RT5682_PWR_BG, RT5682_PWR_BG);
2310 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2311 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2312 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2313 break;
2314
2315 case SND_SOC_BIAS_STANDBY:
2316 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2317 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2318 break;
2319 case SND_SOC_BIAS_OFF:
2320 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2321 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2322 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2323 RT5682_PWR_BG, 0);
2324 break;
2325
2326 default:
2327 break;
2328 }
2329
2330 return 0;
2331 }
2332
rt5682_probe(struct snd_soc_component * component)2333 static int rt5682_probe(struct snd_soc_component *component)
2334 {
2335 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2336
2337 rt5682->component = component;
2338
2339 return 0;
2340 }
2341
rt5682_remove(struct snd_soc_component * component)2342 static void rt5682_remove(struct snd_soc_component *component)
2343 {
2344 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2345
2346 rt5682_reset(rt5682->regmap);
2347 }
2348
2349 #ifdef CONFIG_PM
rt5682_suspend(struct snd_soc_component * component)2350 static int rt5682_suspend(struct snd_soc_component *component)
2351 {
2352 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2353
2354 regcache_cache_only(rt5682->regmap, true);
2355 regcache_mark_dirty(rt5682->regmap);
2356 return 0;
2357 }
2358
rt5682_resume(struct snd_soc_component * component)2359 static int rt5682_resume(struct snd_soc_component *component)
2360 {
2361 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2362
2363 regcache_cache_only(rt5682->regmap, false);
2364 regcache_sync(rt5682->regmap);
2365
2366 rt5682_irq(0, rt5682);
2367
2368 return 0;
2369 }
2370 #else
2371 #define rt5682_suspend NULL
2372 #define rt5682_resume NULL
2373 #endif
2374
2375 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2376 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2377 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2378
2379 static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2380 .hw_params = rt5682_hw_params,
2381 .set_fmt = rt5682_set_dai_fmt,
2382 .set_tdm_slot = rt5682_set_tdm_slot,
2383 };
2384
2385 static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2386 .hw_params = rt5682_hw_params,
2387 .set_fmt = rt5682_set_dai_fmt,
2388 .set_bclk_ratio = rt5682_set_bclk_ratio,
2389 };
2390
2391 static struct snd_soc_dai_driver rt5682_dai[] = {
2392 {
2393 .name = "rt5682-aif1",
2394 .id = RT5682_AIF1,
2395 .playback = {
2396 .stream_name = "AIF1 Playback",
2397 .channels_min = 1,
2398 .channels_max = 2,
2399 .rates = RT5682_STEREO_RATES,
2400 .formats = RT5682_FORMATS,
2401 },
2402 .capture = {
2403 .stream_name = "AIF1 Capture",
2404 .channels_min = 1,
2405 .channels_max = 2,
2406 .rates = RT5682_STEREO_RATES,
2407 .formats = RT5682_FORMATS,
2408 },
2409 .ops = &rt5682_aif1_dai_ops,
2410 },
2411 {
2412 .name = "rt5682-aif2",
2413 .id = RT5682_AIF2,
2414 .capture = {
2415 .stream_name = "AIF2 Capture",
2416 .channels_min = 1,
2417 .channels_max = 2,
2418 .rates = RT5682_STEREO_RATES,
2419 .formats = RT5682_FORMATS,
2420 },
2421 .ops = &rt5682_aif2_dai_ops,
2422 },
2423 };
2424
2425 static const struct snd_soc_component_driver soc_component_dev_rt5682 = {
2426 .probe = rt5682_probe,
2427 .remove = rt5682_remove,
2428 .suspend = rt5682_suspend,
2429 .resume = rt5682_resume,
2430 .set_bias_level = rt5682_set_bias_level,
2431 .controls = rt5682_snd_controls,
2432 .num_controls = ARRAY_SIZE(rt5682_snd_controls),
2433 .dapm_widgets = rt5682_dapm_widgets,
2434 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2435 .dapm_routes = rt5682_dapm_routes,
2436 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2437 .set_sysclk = rt5682_set_component_sysclk,
2438 .set_pll = rt5682_set_component_pll,
2439 .set_jack = rt5682_set_jack_detect,
2440 .use_pmdown_time = 1,
2441 .endianness = 1,
2442 .non_legacy_dai_naming = 1,
2443 };
2444
2445 static const struct regmap_config rt5682_regmap = {
2446 .reg_bits = 16,
2447 .val_bits = 16,
2448 .max_register = RT5682_I2C_MODE,
2449 .volatile_reg = rt5682_volatile_register,
2450 .readable_reg = rt5682_readable_register,
2451 .cache_type = REGCACHE_RBTREE,
2452 .reg_defaults = rt5682_reg,
2453 .num_reg_defaults = ARRAY_SIZE(rt5682_reg),
2454 .use_single_read = true,
2455 .use_single_write = true,
2456 };
2457
2458 static const struct i2c_device_id rt5682_i2c_id[] = {
2459 {"rt5682", 0},
2460 {}
2461 };
2462 MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id);
2463
rt5682_parse_dt(struct rt5682_priv * rt5682,struct device * dev)2464 static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2465 {
2466
2467 device_property_read_u32(dev, "realtek,dmic1-data-pin",
2468 &rt5682->pdata.dmic1_data_pin);
2469 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2470 &rt5682->pdata.dmic1_clk_pin);
2471 device_property_read_u32(dev, "realtek,jd-src",
2472 &rt5682->pdata.jd_src);
2473
2474 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2475 "realtek,ldo1-en-gpios", 0);
2476
2477 return 0;
2478 }
2479
rt5682_calibrate(struct rt5682_priv * rt5682)2480 static void rt5682_calibrate(struct rt5682_priv *rt5682)
2481 {
2482 int value, count;
2483
2484 mutex_lock(&rt5682->calibrate_mutex);
2485
2486 rt5682_reset(rt5682->regmap);
2487 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
2488 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
2489 usleep_range(15000, 20000);
2490 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
2491 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
2492 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
2493 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
2494 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
2495 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
2496 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
2497 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
2498 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
2499 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
2500 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
2501 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2502 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
2503 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
2504 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2505
2506 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
2507
2508 for (count = 0; count < 60; count++) {
2509 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
2510 if (!(value & 0x8000))
2511 break;
2512
2513 usleep_range(10000, 10005);
2514 }
2515
2516 if (count >= 60)
2517 pr_err("HP Calibration Failure\n");
2518
2519 /* restore settings */
2520 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x02af);
2521 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
2522 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
2523 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
2524 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
2525 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
2526 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
2527
2528 mutex_unlock(&rt5682->calibrate_mutex);
2529
2530 }
2531
rt5682_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)2532 static int rt5682_i2c_probe(struct i2c_client *i2c,
2533 const struct i2c_device_id *id)
2534 {
2535 struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev);
2536 struct rt5682_priv *rt5682;
2537 int i, ret;
2538 unsigned int val;
2539
2540 rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv),
2541 GFP_KERNEL);
2542
2543 if (rt5682 == NULL)
2544 return -ENOMEM;
2545
2546 i2c_set_clientdata(i2c, rt5682);
2547
2548 rt5682->pdata = i2s_default_platform_data;
2549
2550 if (pdata)
2551 rt5682->pdata = *pdata;
2552 else
2553 rt5682_parse_dt(rt5682, &i2c->dev);
2554
2555 rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap);
2556 if (IS_ERR(rt5682->regmap)) {
2557 ret = PTR_ERR(rt5682->regmap);
2558 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2559 ret);
2560 return ret;
2561 }
2562
2563 for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++)
2564 rt5682->supplies[i].supply = rt5682_supply_names[i];
2565
2566 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies),
2567 rt5682->supplies);
2568 if (ret != 0) {
2569 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2570 return ret;
2571 }
2572
2573 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies),
2574 rt5682->supplies);
2575 if (ret != 0) {
2576 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2577 return ret;
2578 }
2579
2580 if (gpio_is_valid(rt5682->pdata.ldo1_en)) {
2581 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en,
2582 GPIOF_OUT_INIT_HIGH, "rt5682"))
2583 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
2584 }
2585
2586 /* Sleep for 300 ms miniumum */
2587 usleep_range(300000, 350000);
2588
2589 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1);
2590 usleep_range(10000, 15000);
2591
2592 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
2593 if (val != DEVICE_ID) {
2594 pr_err("Device with ID register %x is not rt5682\n", val);
2595 return -ENODEV;
2596 }
2597
2598 rt5682_reset(rt5682->regmap);
2599
2600 mutex_init(&rt5682->calibrate_mutex);
2601 rt5682_calibrate(rt5682);
2602
2603 ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
2604 ARRAY_SIZE(patch_list));
2605 if (ret != 0)
2606 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2607
2608 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
2609
2610 /* DMIC pin*/
2611 if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) {
2612 switch (rt5682->pdata.dmic1_data_pin) {
2613 case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */
2614 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2615 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2);
2616 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2617 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA);
2618 break;
2619
2620 case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
2621 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2622 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5);
2623 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2624 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA);
2625 break;
2626
2627 default:
2628 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
2629 break;
2630 }
2631
2632 switch (rt5682->pdata.dmic1_clk_pin) {
2633 case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */
2634 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2635 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK);
2636 break;
2637
2638 case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */
2639 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2640 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK);
2641 break;
2642
2643 default:
2644 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
2645 break;
2646 }
2647 }
2648
2649 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2650 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
2651 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
2652 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
2653 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2654 RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK,
2655 RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1);
2656 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
2657 regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
2658 RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
2659 regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
2660 RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
2661
2662 INIT_DELAYED_WORK(&rt5682->jack_detect_work,
2663 rt5682_jack_detect_handler);
2664 INIT_DELAYED_WORK(&rt5682->jd_check_work,
2665 rt5682_jd_check_handler);
2666
2667
2668 if (i2c->irq) {
2669 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2670 rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2671 | IRQF_ONESHOT, "rt5682", rt5682);
2672 if (ret)
2673 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2674
2675 }
2676
2677 return devm_snd_soc_register_component(&i2c->dev,
2678 &soc_component_dev_rt5682,
2679 rt5682_dai, ARRAY_SIZE(rt5682_dai));
2680 }
2681
rt5682_i2c_shutdown(struct i2c_client * client)2682 static void rt5682_i2c_shutdown(struct i2c_client *client)
2683 {
2684 struct rt5682_priv *rt5682 = i2c_get_clientdata(client);
2685
2686 rt5682_reset(rt5682->regmap);
2687 }
2688
2689 #ifdef CONFIG_OF
2690 static const struct of_device_id rt5682_of_match[] = {
2691 {.compatible = "realtek,rt5682i"},
2692 {},
2693 };
2694 MODULE_DEVICE_TABLE(of, rt5682_of_match);
2695 #endif
2696
2697 #ifdef CONFIG_ACPI
2698 static const struct acpi_device_id rt5682_acpi_match[] = {
2699 {"10EC5682", 0,},
2700 {},
2701 };
2702 MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match);
2703 #endif
2704
2705 static struct i2c_driver rt5682_i2c_driver = {
2706 .driver = {
2707 .name = "rt5682",
2708 .of_match_table = of_match_ptr(rt5682_of_match),
2709 .acpi_match_table = ACPI_PTR(rt5682_acpi_match),
2710 },
2711 .probe = rt5682_i2c_probe,
2712 .shutdown = rt5682_i2c_shutdown,
2713 .id_table = rt5682_i2c_id,
2714 };
2715 module_i2c_driver(rt5682_i2c_driver);
2716
2717 MODULE_DESCRIPTION("ASoC RT5682 driver");
2718 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2719 MODULE_LICENSE("GPL v2");
2720