1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright 2018 NXP
3
4 #include <linux/clk.h>
5 #include <linux/device.h>
6 #include <linux/interrupt.h>
7 #include <linux/kobject.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_irq.h>
13 #include <linux/of_platform.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/sysfs.h>
17 #include <linux/types.h>
18 #include <sound/dmaengine_pcm.h>
19 #include <sound/pcm.h>
20 #include <sound/soc.h>
21 #include <sound/tlv.h>
22 #include <sound/core.h>
23
24 #include "fsl_micfil.h"
25 #include "imx-pcm.h"
26
27 #define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
28 #define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
29
30 struct fsl_micfil {
31 struct platform_device *pdev;
32 struct regmap *regmap;
33 const struct fsl_micfil_soc_data *soc;
34 struct clk *mclk;
35 struct snd_dmaengine_dai_dma_data dma_params_rx;
36 unsigned int dataline;
37 char name[32];
38 int irq[MICFIL_IRQ_LINES];
39 unsigned int mclk_streams;
40 int quality; /*QUALITY 2-0 bits */
41 bool slave_mode;
42 int channel_gain[8];
43 };
44
45 struct fsl_micfil_soc_data {
46 unsigned int fifos;
47 unsigned int fifo_depth;
48 unsigned int dataline;
49 bool imx;
50 };
51
52 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
53 .imx = true,
54 .fifos = 8,
55 .fifo_depth = 8,
56 .dataline = 0xf,
57 };
58
59 static const struct of_device_id fsl_micfil_dt_ids[] = {
60 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
61 {}
62 };
63 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
64
65 /* Table 5. Quality Modes
66 * Medium 0 0 0
67 * High 0 0 1
68 * Very Low 2 1 0 0
69 * Very Low 1 1 0 1
70 * Very Low 0 1 1 0
71 * Low 1 1 1
72 */
73 static const char * const micfil_quality_select_texts[] = {
74 "Medium", "High",
75 "N/A", "N/A",
76 "VLow2", "VLow1",
77 "VLow0", "Low",
78 };
79
80 static const struct soc_enum fsl_micfil_quality_enum =
81 SOC_ENUM_SINGLE(REG_MICFIL_CTRL2,
82 MICFIL_CTRL2_QSEL_SHIFT,
83 ARRAY_SIZE(micfil_quality_select_texts),
84 micfil_quality_select_texts);
85
86 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
87
88 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
89 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
90 MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv),
91 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
92 MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv),
93 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
94 MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv),
95 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
96 MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv),
97 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
98 MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv),
99 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
100 MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv),
101 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
102 MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv),
103 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
104 MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv),
105 SOC_ENUM_EXT("MICFIL Quality Select",
106 fsl_micfil_quality_enum,
107 snd_soc_get_enum_double, snd_soc_put_enum_double),
108 };
109
get_pdm_clk(struct fsl_micfil * micfil,unsigned int rate)110 static inline int get_pdm_clk(struct fsl_micfil *micfil,
111 unsigned int rate)
112 {
113 u32 ctrl2_reg;
114 int qsel, osr;
115 int bclk;
116
117 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
118 osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
119 >> MICFIL_CTRL2_CICOSR_SHIFT);
120
121 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
122 qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
123
124 switch (qsel) {
125 case MICFIL_HIGH_QUALITY:
126 bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
127 break;
128 case MICFIL_MEDIUM_QUALITY:
129 case MICFIL_VLOW0_QUALITY:
130 bclk = rate * 4 * osr * 1; /* kfactor = 1 */
131 break;
132 case MICFIL_LOW_QUALITY:
133 case MICFIL_VLOW1_QUALITY:
134 bclk = rate * 2 * osr * 2; /* kfactor = 2 */
135 break;
136 case MICFIL_VLOW2_QUALITY:
137 bclk = rate * osr * 4; /* kfactor = 4 */
138 break;
139 default:
140 dev_err(&micfil->pdev->dev,
141 "Please make sure you select a valid quality.\n");
142 bclk = -1;
143 break;
144 }
145
146 return bclk;
147 }
148
get_clk_div(struct fsl_micfil * micfil,unsigned int rate)149 static inline int get_clk_div(struct fsl_micfil *micfil,
150 unsigned int rate)
151 {
152 u32 ctrl2_reg;
153 long mclk_rate;
154 int clk_div;
155
156 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
157
158 mclk_rate = clk_get_rate(micfil->mclk);
159
160 clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
161
162 return clk_div;
163 }
164
165 /* The SRES is a self-negated bit which provides the CPU with the
166 * capability to initialize the PDM Interface module through the
167 * slave-bus interface. This bit always reads as zero, and this
168 * bit is only effective when MDIS is cleared
169 */
fsl_micfil_reset(struct device * dev)170 static int fsl_micfil_reset(struct device *dev)
171 {
172 struct fsl_micfil *micfil = dev_get_drvdata(dev);
173 int ret;
174
175 ret = regmap_update_bits(micfil->regmap,
176 REG_MICFIL_CTRL1,
177 MICFIL_CTRL1_MDIS_MASK,
178 0);
179 if (ret) {
180 dev_err(dev, "failed to clear MDIS bit %d\n", ret);
181 return ret;
182 }
183
184 ret = regmap_update_bits(micfil->regmap,
185 REG_MICFIL_CTRL1,
186 MICFIL_CTRL1_SRES_MASK,
187 MICFIL_CTRL1_SRES);
188 if (ret) {
189 dev_err(dev, "failed to reset MICFIL: %d\n", ret);
190 return ret;
191 }
192
193 return 0;
194 }
195
fsl_micfil_set_mclk_rate(struct fsl_micfil * micfil,unsigned int freq)196 static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
197 unsigned int freq)
198 {
199 struct device *dev = &micfil->pdev->dev;
200 int ret;
201
202 clk_disable_unprepare(micfil->mclk);
203
204 ret = clk_set_rate(micfil->mclk, freq * 1024);
205 if (ret)
206 dev_warn(dev, "failed to set rate (%u): %d\n",
207 freq * 1024, ret);
208
209 clk_prepare_enable(micfil->mclk);
210
211 return ret;
212 }
213
fsl_micfil_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)214 static int fsl_micfil_startup(struct snd_pcm_substream *substream,
215 struct snd_soc_dai *dai)
216 {
217 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
218
219 if (!micfil) {
220 dev_err(dai->dev,
221 "micfil dai priv_data not set\n");
222 return -EINVAL;
223 }
224
225 return 0;
226 }
227
fsl_micfil_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)228 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
229 struct snd_soc_dai *dai)
230 {
231 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
232 struct device *dev = &micfil->pdev->dev;
233 int ret;
234
235 switch (cmd) {
236 case SNDRV_PCM_TRIGGER_START:
237 case SNDRV_PCM_TRIGGER_RESUME:
238 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
239 ret = fsl_micfil_reset(dev);
240 if (ret) {
241 dev_err(dev, "failed to soft reset\n");
242 return ret;
243 }
244
245 /* DMA Interrupt Selection - DISEL bits
246 * 00 - DMA and IRQ disabled
247 * 01 - DMA req enabled
248 * 10 - IRQ enabled
249 * 11 - reserved
250 */
251 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
252 MICFIL_CTRL1_DISEL_MASK,
253 (1 << MICFIL_CTRL1_DISEL_SHIFT));
254 if (ret) {
255 dev_err(dev, "failed to update DISEL bits\n");
256 return ret;
257 }
258
259 /* Enable the module */
260 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
261 MICFIL_CTRL1_PDMIEN_MASK,
262 MICFIL_CTRL1_PDMIEN);
263 if (ret) {
264 dev_err(dev, "failed to enable the module\n");
265 return ret;
266 }
267
268 break;
269 case SNDRV_PCM_TRIGGER_STOP:
270 case SNDRV_PCM_TRIGGER_SUSPEND:
271 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
272 /* Disable the module */
273 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
274 MICFIL_CTRL1_PDMIEN_MASK,
275 0);
276 if (ret) {
277 dev_err(dev, "failed to enable the module\n");
278 return ret;
279 }
280
281 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
282 MICFIL_CTRL1_DISEL_MASK,
283 (0 << MICFIL_CTRL1_DISEL_SHIFT));
284 if (ret) {
285 dev_err(dev, "failed to update DISEL bits\n");
286 return ret;
287 }
288 break;
289 default:
290 return -EINVAL;
291 }
292 return 0;
293 }
294
fsl_set_clock_params(struct device * dev,unsigned int rate)295 static int fsl_set_clock_params(struct device *dev, unsigned int rate)
296 {
297 struct fsl_micfil *micfil = dev_get_drvdata(dev);
298 int clk_div;
299 int ret = 0;
300
301 ret = fsl_micfil_set_mclk_rate(micfil, rate);
302 if (ret < 0)
303 dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
304 clk_get_rate(micfil->mclk), rate);
305
306 /* set CICOSR */
307 ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
308 MICFIL_CTRL2_CICOSR_MASK,
309 MICFIL_CTRL2_OSR_DEFAULT);
310 if (ret)
311 dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
312 REG_MICFIL_CTRL2);
313
314 /* set CLK_DIV */
315 clk_div = get_clk_div(micfil, rate);
316 if (clk_div < 0)
317 ret = -EINVAL;
318
319 ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
320 MICFIL_CTRL2_CLKDIV_MASK, clk_div);
321 if (ret)
322 dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
323 REG_MICFIL_CTRL2);
324
325 return ret;
326 }
327
fsl_micfil_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)328 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
329 struct snd_pcm_hw_params *params,
330 struct snd_soc_dai *dai)
331 {
332 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
333 unsigned int channels = params_channels(params);
334 unsigned int rate = params_rate(params);
335 struct device *dev = &micfil->pdev->dev;
336 int ret;
337
338 /* 1. Disable the module */
339 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
340 MICFIL_CTRL1_PDMIEN_MASK, 0);
341 if (ret) {
342 dev_err(dev, "failed to disable the module\n");
343 return ret;
344 }
345
346 /* enable channels */
347 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
348 0xFF, ((1 << channels) - 1));
349 if (ret) {
350 dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret,
351 REG_MICFIL_CTRL1);
352 return ret;
353 }
354
355 ret = fsl_set_clock_params(dev, rate);
356 if (ret < 0) {
357 dev_err(dev, "Failed to set clock parameters [%d]\n", ret);
358 return ret;
359 }
360
361 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
362
363 return 0;
364 }
365
fsl_micfil_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)366 static int fsl_micfil_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
367 unsigned int freq, int dir)
368 {
369 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
370 struct device *dev = &micfil->pdev->dev;
371
372 int ret;
373
374 if (!freq)
375 return 0;
376
377 ret = fsl_micfil_set_mclk_rate(micfil, freq);
378 if (ret < 0)
379 dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
380 clk_get_rate(micfil->mclk), freq);
381
382 return ret;
383 }
384
385 static struct snd_soc_dai_ops fsl_micfil_dai_ops = {
386 .startup = fsl_micfil_startup,
387 .trigger = fsl_micfil_trigger,
388 .hw_params = fsl_micfil_hw_params,
389 .set_sysclk = fsl_micfil_set_dai_sysclk,
390 };
391
fsl_micfil_dai_probe(struct snd_soc_dai * cpu_dai)392 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
393 {
394 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
395 struct device *dev = cpu_dai->dev;
396 unsigned int val;
397 int ret;
398 int i;
399
400 /* set qsel to medium */
401 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
402 MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY);
403 if (ret) {
404 dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
405 REG_MICFIL_CTRL2);
406 return ret;
407 }
408
409 /* set default gain to max_gain */
410 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
411 for (i = 0; i < 8; i++)
412 micfil->channel_gain[i] = 0xF;
413
414 snd_soc_dai_init_dma_data(cpu_dai, NULL,
415 &micfil->dma_params_rx);
416
417 /* FIFO Watermark Control - FIFOWMK*/
418 val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1;
419 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
420 MICFIL_FIFO_CTRL_FIFOWMK_MASK,
421 val);
422 if (ret) {
423 dev_err(dev, "failed to set FIFOWMK\n");
424 return ret;
425 }
426
427 snd_soc_dai_set_drvdata(cpu_dai, micfil);
428
429 return 0;
430 }
431
432 static struct snd_soc_dai_driver fsl_micfil_dai = {
433 .probe = fsl_micfil_dai_probe,
434 .capture = {
435 .stream_name = "CPU-Capture",
436 .channels_min = 1,
437 .channels_max = 8,
438 .rates = FSL_MICFIL_RATES,
439 .formats = FSL_MICFIL_FORMATS,
440 },
441 .ops = &fsl_micfil_dai_ops,
442 };
443
444 static const struct snd_soc_component_driver fsl_micfil_component = {
445 .name = "fsl-micfil-dai",
446 .controls = fsl_micfil_snd_controls,
447 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
448
449 };
450
451 /* REGMAP */
452 static const struct reg_default fsl_micfil_reg_defaults[] = {
453 {REG_MICFIL_CTRL1, 0x00000000},
454 {REG_MICFIL_CTRL2, 0x00000000},
455 {REG_MICFIL_STAT, 0x00000000},
456 {REG_MICFIL_FIFO_CTRL, 0x00000007},
457 {REG_MICFIL_FIFO_STAT, 0x00000000},
458 {REG_MICFIL_DATACH0, 0x00000000},
459 {REG_MICFIL_DATACH1, 0x00000000},
460 {REG_MICFIL_DATACH2, 0x00000000},
461 {REG_MICFIL_DATACH3, 0x00000000},
462 {REG_MICFIL_DATACH4, 0x00000000},
463 {REG_MICFIL_DATACH5, 0x00000000},
464 {REG_MICFIL_DATACH6, 0x00000000},
465 {REG_MICFIL_DATACH7, 0x00000000},
466 {REG_MICFIL_DC_CTRL, 0x00000000},
467 {REG_MICFIL_OUT_CTRL, 0x00000000},
468 {REG_MICFIL_OUT_STAT, 0x00000000},
469 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
470 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
471 {REG_MICFIL_VAD0_STAT, 0x00000000},
472 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
473 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
474 {REG_MICFIL_VAD0_NDATA, 0x00000000},
475 {REG_MICFIL_VAD0_ZCD, 0x00000004},
476 };
477
fsl_micfil_readable_reg(struct device * dev,unsigned int reg)478 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
479 {
480 switch (reg) {
481 case REG_MICFIL_CTRL1:
482 case REG_MICFIL_CTRL2:
483 case REG_MICFIL_STAT:
484 case REG_MICFIL_FIFO_CTRL:
485 case REG_MICFIL_FIFO_STAT:
486 case REG_MICFIL_DATACH0:
487 case REG_MICFIL_DATACH1:
488 case REG_MICFIL_DATACH2:
489 case REG_MICFIL_DATACH3:
490 case REG_MICFIL_DATACH4:
491 case REG_MICFIL_DATACH5:
492 case REG_MICFIL_DATACH6:
493 case REG_MICFIL_DATACH7:
494 case REG_MICFIL_DC_CTRL:
495 case REG_MICFIL_OUT_CTRL:
496 case REG_MICFIL_OUT_STAT:
497 case REG_MICFIL_VAD0_CTRL1:
498 case REG_MICFIL_VAD0_CTRL2:
499 case REG_MICFIL_VAD0_STAT:
500 case REG_MICFIL_VAD0_SCONFIG:
501 case REG_MICFIL_VAD0_NCONFIG:
502 case REG_MICFIL_VAD0_NDATA:
503 case REG_MICFIL_VAD0_ZCD:
504 return true;
505 default:
506 return false;
507 }
508 }
509
fsl_micfil_writeable_reg(struct device * dev,unsigned int reg)510 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
511 {
512 switch (reg) {
513 case REG_MICFIL_CTRL1:
514 case REG_MICFIL_CTRL2:
515 case REG_MICFIL_STAT: /* Write 1 to Clear */
516 case REG_MICFIL_FIFO_CTRL:
517 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
518 case REG_MICFIL_DC_CTRL:
519 case REG_MICFIL_OUT_CTRL:
520 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
521 case REG_MICFIL_VAD0_CTRL1:
522 case REG_MICFIL_VAD0_CTRL2:
523 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
524 case REG_MICFIL_VAD0_SCONFIG:
525 case REG_MICFIL_VAD0_NCONFIG:
526 case REG_MICFIL_VAD0_ZCD:
527 return true;
528 default:
529 return false;
530 }
531 }
532
fsl_micfil_volatile_reg(struct device * dev,unsigned int reg)533 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
534 {
535 switch (reg) {
536 case REG_MICFIL_STAT:
537 case REG_MICFIL_DATACH0:
538 case REG_MICFIL_DATACH1:
539 case REG_MICFIL_DATACH2:
540 case REG_MICFIL_DATACH3:
541 case REG_MICFIL_DATACH4:
542 case REG_MICFIL_DATACH5:
543 case REG_MICFIL_DATACH6:
544 case REG_MICFIL_DATACH7:
545 case REG_MICFIL_VAD0_STAT:
546 case REG_MICFIL_VAD0_NDATA:
547 return true;
548 default:
549 return false;
550 }
551 }
552
553 static const struct regmap_config fsl_micfil_regmap_config = {
554 .reg_bits = 32,
555 .reg_stride = 4,
556 .val_bits = 32,
557
558 .max_register = REG_MICFIL_VAD0_ZCD,
559 .reg_defaults = fsl_micfil_reg_defaults,
560 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
561 .readable_reg = fsl_micfil_readable_reg,
562 .volatile_reg = fsl_micfil_volatile_reg,
563 .writeable_reg = fsl_micfil_writeable_reg,
564 .cache_type = REGCACHE_RBTREE,
565 };
566
567 /* END OF REGMAP */
568
micfil_isr(int irq,void * devid)569 static irqreturn_t micfil_isr(int irq, void *devid)
570 {
571 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
572 struct platform_device *pdev = micfil->pdev;
573 u32 stat_reg;
574 u32 fifo_stat_reg;
575 u32 ctrl1_reg;
576 bool dma_enabled;
577 int i;
578
579 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
580 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
581 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
582
583 dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg);
584
585 /* Channel 0-7 Output Data Flags */
586 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
587 if (stat_reg & MICFIL_STAT_CHXF_MASK(i))
588 dev_dbg(&pdev->dev,
589 "Data available in Data Channel %d\n", i);
590 /* if DMA is not enabled, field must be written with 1
591 * to clear
592 */
593 if (!dma_enabled)
594 regmap_write_bits(micfil->regmap,
595 REG_MICFIL_STAT,
596 MICFIL_STAT_CHXF_MASK(i),
597 1);
598 }
599
600 for (i = 0; i < MICFIL_FIFO_NUM; i++) {
601 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER_MASK(i))
602 dev_dbg(&pdev->dev,
603 "FIFO Overflow Exception flag for channel %d\n",
604 i);
605
606 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(i))
607 dev_dbg(&pdev->dev,
608 "FIFO Underflow Exception flag for channel %d\n",
609 i);
610 }
611
612 return IRQ_HANDLED;
613 }
614
micfil_err_isr(int irq,void * devid)615 static irqreturn_t micfil_err_isr(int irq, void *devid)
616 {
617 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
618 struct platform_device *pdev = micfil->pdev;
619 u32 stat_reg;
620
621 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
622
623 if (stat_reg & MICFIL_STAT_BSY_FIL_MASK)
624 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
625
626 if (stat_reg & MICFIL_STAT_FIR_RDY_MASK)
627 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
628
629 if (stat_reg & MICFIL_STAT_LOWFREQF_MASK) {
630 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
631 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
632 MICFIL_STAT_LOWFREQF_MASK, 1);
633 }
634
635 return IRQ_HANDLED;
636 }
637
fsl_micfil_probe(struct platform_device * pdev)638 static int fsl_micfil_probe(struct platform_device *pdev)
639 {
640 struct device_node *np = pdev->dev.of_node;
641 const struct of_device_id *of_id;
642 struct fsl_micfil *micfil;
643 struct resource *res;
644 void __iomem *regs;
645 int ret, i;
646 unsigned long irqflag = 0;
647
648 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
649 if (!micfil)
650 return -ENOMEM;
651
652 micfil->pdev = pdev;
653 strncpy(micfil->name, np->name, sizeof(micfil->name) - 1);
654
655 of_id = of_match_device(fsl_micfil_dt_ids, &pdev->dev);
656 if (!of_id || !of_id->data)
657 return -EINVAL;
658
659 micfil->soc = of_id->data;
660
661 /* ipg_clk is used to control the registers
662 * ipg_clk_app is used to operate the filter
663 */
664 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
665 if (IS_ERR(micfil->mclk)) {
666 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
667 PTR_ERR(micfil->mclk));
668 return PTR_ERR(micfil->mclk);
669 }
670
671 /* init regmap */
672 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
673 regs = devm_ioremap_resource(&pdev->dev, res);
674 if (IS_ERR(regs))
675 return PTR_ERR(regs);
676
677 micfil->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
678 "ipg_clk",
679 regs,
680 &fsl_micfil_regmap_config);
681 if (IS_ERR(micfil->regmap)) {
682 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
683 PTR_ERR(micfil->regmap));
684 return PTR_ERR(micfil->regmap);
685 }
686
687 /* dataline mask for RX */
688 ret = of_property_read_u32_index(np,
689 "fsl,dataline",
690 0,
691 &micfil->dataline);
692 if (ret)
693 micfil->dataline = 1;
694
695 if (micfil->dataline & ~micfil->soc->dataline) {
696 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
697 micfil->soc->dataline);
698 return -EINVAL;
699 }
700
701 /* get IRQs */
702 for (i = 0; i < MICFIL_IRQ_LINES; i++) {
703 micfil->irq[i] = platform_get_irq(pdev, i);
704 dev_err(&pdev->dev, "GET IRQ: %d\n", micfil->irq[i]);
705 if (micfil->irq[i] < 0) {
706 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
707 return micfil->irq[i];
708 }
709 }
710
711 if (of_property_read_bool(np, "fsl,shared-interrupt"))
712 irqflag = IRQF_SHARED;
713
714 /* Digital Microphone interface interrupt - IRQ 109 */
715 ret = devm_request_irq(&pdev->dev, micfil->irq[0],
716 micfil_isr, irqflag,
717 micfil->name, micfil);
718 if (ret) {
719 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
720 micfil->irq[0]);
721 return ret;
722 }
723
724 /* Digital Microphone interface error interrupt - IRQ 110 */
725 ret = devm_request_irq(&pdev->dev, micfil->irq[1],
726 micfil_err_isr, irqflag,
727 micfil->name, micfil);
728 if (ret) {
729 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
730 micfil->irq[1]);
731 return ret;
732 }
733
734 micfil->dma_params_rx.chan_name = "rx";
735 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
736 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
737
738
739 platform_set_drvdata(pdev, micfil);
740
741 pm_runtime_enable(&pdev->dev);
742
743 /*
744 * Register platform component before registering cpu dai for there
745 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
746 */
747 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
748 if (ret) {
749 dev_err(&pdev->dev, "failed to pcm register\n");
750 return ret;
751 }
752
753 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
754 &fsl_micfil_dai, 1);
755 if (ret) {
756 dev_err(&pdev->dev, "failed to register component %s\n",
757 fsl_micfil_component.name);
758 }
759
760 return ret;
761 }
762
763 #ifdef CONFIG_PM
fsl_micfil_runtime_suspend(struct device * dev)764 static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev)
765 {
766 struct fsl_micfil *micfil = dev_get_drvdata(dev);
767
768 regcache_cache_only(micfil->regmap, true);
769
770 clk_disable_unprepare(micfil->mclk);
771
772 return 0;
773 }
774
fsl_micfil_runtime_resume(struct device * dev)775 static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev)
776 {
777 struct fsl_micfil *micfil = dev_get_drvdata(dev);
778 int ret;
779
780 ret = clk_prepare_enable(micfil->mclk);
781 if (ret < 0)
782 return ret;
783
784 regcache_cache_only(micfil->regmap, false);
785 regcache_mark_dirty(micfil->regmap);
786 regcache_sync(micfil->regmap);
787
788 return 0;
789 }
790 #endif /* CONFIG_PM*/
791
792 #ifdef CONFIG_PM_SLEEP
fsl_micfil_suspend(struct device * dev)793 static int __maybe_unused fsl_micfil_suspend(struct device *dev)
794 {
795 pm_runtime_force_suspend(dev);
796
797 return 0;
798 }
799
fsl_micfil_resume(struct device * dev)800 static int __maybe_unused fsl_micfil_resume(struct device *dev)
801 {
802 pm_runtime_force_resume(dev);
803
804 return 0;
805 }
806 #endif /* CONFIG_PM_SLEEP */
807
808 static const struct dev_pm_ops fsl_micfil_pm_ops = {
809 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
810 fsl_micfil_runtime_resume,
811 NULL)
812 SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend,
813 fsl_micfil_resume)
814 };
815
816 static struct platform_driver fsl_micfil_driver = {
817 .probe = fsl_micfil_probe,
818 .driver = {
819 .name = "fsl-micfil-dai",
820 .pm = &fsl_micfil_pm_ops,
821 .of_match_table = fsl_micfil_dt_ids,
822 },
823 };
824 module_platform_driver(fsl_micfil_driver);
825
826 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
827 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
828 MODULE_LICENSE("GPL v2");
829