1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
4 //
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
6
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/module.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <linux/slab.h>
16 #include <linux/time.h>
17 #include <sound/core.h>
18 #include <sound/dmaengine_pcm.h>
19 #include <sound/pcm_params.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
22
23 #include "fsl_sai.h"
24 #include "imx-pcm.h"
25
26 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
27 FSL_SAI_CSR_FEIE)
28
29 static const unsigned int fsl_sai_rates[] = {
30 8000, 11025, 12000, 16000, 22050,
31 24000, 32000, 44100, 48000, 64000,
32 88200, 96000, 176400, 192000
33 };
34
35 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
36 .count = ARRAY_SIZE(fsl_sai_rates),
37 .list = fsl_sai_rates,
38 };
39
40 /**
41 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
42 *
43 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
44 * or Receiver's for both streams. This function is used to check if clocks of
45 * the stream's are synced by the opposite stream.
46 *
47 * @sai: SAI context
48 * @dir: stream direction
49 */
fsl_sai_dir_is_synced(struct fsl_sai * sai,int dir)50 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir)
51 {
52 int adir = (dir == TX) ? RX : TX;
53
54 /* current dir in async mode while opposite dir in sync mode */
55 return !sai->synchronous[dir] && sai->synchronous[adir];
56 }
57
fsl_sai_isr(int irq,void * devid)58 static irqreturn_t fsl_sai_isr(int irq, void *devid)
59 {
60 struct fsl_sai *sai = (struct fsl_sai *)devid;
61 unsigned int ofs = sai->soc_data->reg_offset;
62 struct device *dev = &sai->pdev->dev;
63 u32 flags, xcsr, mask;
64 bool irq_none = true;
65
66 /*
67 * Both IRQ status bits and IRQ mask bits are in the xCSR but
68 * different shifts. And we here create a mask only for those
69 * IRQs that we activated.
70 */
71 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
72
73 /* Tx IRQ */
74 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
75 flags = xcsr & mask;
76
77 if (flags)
78 irq_none = false;
79 else
80 goto irq_rx;
81
82 if (flags & FSL_SAI_CSR_WSF)
83 dev_dbg(dev, "isr: Start of Tx word detected\n");
84
85 if (flags & FSL_SAI_CSR_SEF)
86 dev_dbg(dev, "isr: Tx Frame sync error detected\n");
87
88 if (flags & FSL_SAI_CSR_FEF) {
89 dev_dbg(dev, "isr: Transmit underrun detected\n");
90 /* FIFO reset for safety */
91 xcsr |= FSL_SAI_CSR_FR;
92 }
93
94 if (flags & FSL_SAI_CSR_FWF)
95 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
96
97 if (flags & FSL_SAI_CSR_FRF)
98 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
99
100 flags &= FSL_SAI_CSR_xF_W_MASK;
101 xcsr &= ~FSL_SAI_CSR_xF_MASK;
102
103 if (flags)
104 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
105
106 irq_rx:
107 /* Rx IRQ */
108 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
109 flags = xcsr & mask;
110
111 if (flags)
112 irq_none = false;
113 else
114 goto out;
115
116 if (flags & FSL_SAI_CSR_WSF)
117 dev_dbg(dev, "isr: Start of Rx word detected\n");
118
119 if (flags & FSL_SAI_CSR_SEF)
120 dev_dbg(dev, "isr: Rx Frame sync error detected\n");
121
122 if (flags & FSL_SAI_CSR_FEF) {
123 dev_dbg(dev, "isr: Receive overflow detected\n");
124 /* FIFO reset for safety */
125 xcsr |= FSL_SAI_CSR_FR;
126 }
127
128 if (flags & FSL_SAI_CSR_FWF)
129 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
130
131 if (flags & FSL_SAI_CSR_FRF)
132 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
133
134 flags &= FSL_SAI_CSR_xF_W_MASK;
135 xcsr &= ~FSL_SAI_CSR_xF_MASK;
136
137 if (flags)
138 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
139
140 out:
141 if (irq_none)
142 return IRQ_NONE;
143 else
144 return IRQ_HANDLED;
145 }
146
fsl_sai_set_dai_tdm_slot(struct snd_soc_dai * cpu_dai,u32 tx_mask,u32 rx_mask,int slots,int slot_width)147 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
148 u32 rx_mask, int slots, int slot_width)
149 {
150 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
151
152 sai->slots = slots;
153 sai->slot_width = slot_width;
154
155 return 0;
156 }
157
fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)158 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
159 unsigned int ratio)
160 {
161 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
162
163 sai->bclk_ratio = ratio;
164
165 return 0;
166 }
167
fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int fsl_dir)168 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
169 int clk_id, unsigned int freq, int fsl_dir)
170 {
171 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
172 unsigned int ofs = sai->soc_data->reg_offset;
173 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
174 u32 val_cr2 = 0;
175
176 switch (clk_id) {
177 case FSL_SAI_CLK_BUS:
178 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
179 break;
180 case FSL_SAI_CLK_MAST1:
181 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
182 break;
183 case FSL_SAI_CLK_MAST2:
184 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
185 break;
186 case FSL_SAI_CLK_MAST3:
187 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
188 break;
189 default:
190 return -EINVAL;
191 }
192
193 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
194 FSL_SAI_CR2_MSEL_MASK, val_cr2);
195
196 return 0;
197 }
198
fsl_sai_set_dai_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)199 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
200 int clk_id, unsigned int freq, int dir)
201 {
202 int ret;
203
204 if (dir == SND_SOC_CLOCK_IN)
205 return 0;
206
207 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
208 FSL_FMT_TRANSMITTER);
209 if (ret) {
210 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
211 return ret;
212 }
213
214 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
215 FSL_FMT_RECEIVER);
216 if (ret)
217 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
218
219 return ret;
220 }
221
fsl_sai_set_dai_fmt_tr(struct snd_soc_dai * cpu_dai,unsigned int fmt,int fsl_dir)222 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
223 unsigned int fmt, int fsl_dir)
224 {
225 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
226 unsigned int ofs = sai->soc_data->reg_offset;
227 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
228 u32 val_cr2 = 0, val_cr4 = 0;
229
230 if (!sai->is_lsb_first)
231 val_cr4 |= FSL_SAI_CR4_MF;
232
233 sai->is_dsp_mode = false;
234 /* DAI mode */
235 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
236 case SND_SOC_DAIFMT_I2S:
237 /*
238 * Frame low, 1clk before data, one word length for frame sync,
239 * frame sync starts one serial clock cycle earlier,
240 * that is, together with the last bit of the previous
241 * data word.
242 */
243 val_cr2 |= FSL_SAI_CR2_BCP;
244 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
245 break;
246 case SND_SOC_DAIFMT_LEFT_J:
247 /*
248 * Frame high, one word length for frame sync,
249 * frame sync asserts with the first bit of the frame.
250 */
251 val_cr2 |= FSL_SAI_CR2_BCP;
252 break;
253 case SND_SOC_DAIFMT_DSP_A:
254 /*
255 * Frame high, 1clk before data, one bit for frame sync,
256 * frame sync starts one serial clock cycle earlier,
257 * that is, together with the last bit of the previous
258 * data word.
259 */
260 val_cr2 |= FSL_SAI_CR2_BCP;
261 val_cr4 |= FSL_SAI_CR4_FSE;
262 sai->is_dsp_mode = true;
263 break;
264 case SND_SOC_DAIFMT_DSP_B:
265 /*
266 * Frame high, one bit for frame sync,
267 * frame sync asserts with the first bit of the frame.
268 */
269 val_cr2 |= FSL_SAI_CR2_BCP;
270 sai->is_dsp_mode = true;
271 break;
272 case SND_SOC_DAIFMT_RIGHT_J:
273 /* To be done */
274 default:
275 return -EINVAL;
276 }
277
278 /* DAI clock inversion */
279 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
280 case SND_SOC_DAIFMT_IB_IF:
281 /* Invert both clocks */
282 val_cr2 ^= FSL_SAI_CR2_BCP;
283 val_cr4 ^= FSL_SAI_CR4_FSP;
284 break;
285 case SND_SOC_DAIFMT_IB_NF:
286 /* Invert bit clock */
287 val_cr2 ^= FSL_SAI_CR2_BCP;
288 break;
289 case SND_SOC_DAIFMT_NB_IF:
290 /* Invert frame clock */
291 val_cr4 ^= FSL_SAI_CR4_FSP;
292 break;
293 case SND_SOC_DAIFMT_NB_NF:
294 /* Nothing to do for both normal cases */
295 break;
296 default:
297 return -EINVAL;
298 }
299
300 /* DAI clock master masks */
301 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
302 case SND_SOC_DAIFMT_CBS_CFS:
303 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
304 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
305 sai->is_slave_mode = false;
306 break;
307 case SND_SOC_DAIFMT_CBM_CFM:
308 sai->is_slave_mode = true;
309 break;
310 case SND_SOC_DAIFMT_CBS_CFM:
311 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
312 sai->is_slave_mode = false;
313 break;
314 case SND_SOC_DAIFMT_CBM_CFS:
315 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
316 sai->is_slave_mode = true;
317 break;
318 default:
319 return -EINVAL;
320 }
321
322 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
323 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
324 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
325 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
326 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
327
328 return 0;
329 }
330
fsl_sai_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)331 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
332 {
333 int ret;
334
335 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
336 if (ret) {
337 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
338 return ret;
339 }
340
341 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
342 if (ret)
343 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
344
345 return ret;
346 }
347
fsl_sai_set_bclk(struct snd_soc_dai * dai,bool tx,u32 freq)348 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
349 {
350 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
351 unsigned int ofs = sai->soc_data->reg_offset;
352 unsigned long clk_rate;
353 u32 savediv = 0, ratio, savesub = freq;
354 u32 id;
355 int ret = 0;
356
357 /* Don't apply to slave mode */
358 if (sai->is_slave_mode)
359 return 0;
360
361 for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
362 clk_rate = clk_get_rate(sai->mclk_clk[id]);
363 if (!clk_rate)
364 continue;
365
366 ratio = clk_rate / freq;
367
368 ret = clk_rate - ratio * freq;
369
370 /*
371 * Drop the source that can not be
372 * divided into the required rate.
373 */
374 if (ret != 0 && clk_rate / ret < 1000)
375 continue;
376
377 dev_dbg(dai->dev,
378 "ratio %d for freq %dHz based on clock %ldHz\n",
379 ratio, freq, clk_rate);
380
381 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
382 ratio /= 2;
383 else
384 continue;
385
386 if (ret < savesub) {
387 savediv = ratio;
388 sai->mclk_id[tx] = id;
389 savesub = ret;
390 }
391
392 if (ret == 0)
393 break;
394 }
395
396 if (savediv == 0) {
397 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
398 tx ? 'T' : 'R', freq);
399 return -EINVAL;
400 }
401
402 /*
403 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
404 * set TCR2 register for playback.
405 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
406 * and capture.
407 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
408 * and capture.
409 * 4) For Tx and Rx are both Synchronous with another SAI, we just
410 * ignore it.
411 */
412 if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
413 (!tx && !sai->synchronous[RX])) {
414 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs),
415 FSL_SAI_CR2_MSEL_MASK,
416 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
417 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs),
418 FSL_SAI_CR2_DIV_MASK, savediv - 1);
419 } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
420 (tx && !sai->synchronous[TX])) {
421 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs),
422 FSL_SAI_CR2_MSEL_MASK,
423 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
424 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs),
425 FSL_SAI_CR2_DIV_MASK, savediv - 1);
426 }
427
428 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
429 sai->mclk_id[tx], savediv, savesub);
430
431 return 0;
432 }
433
fsl_sai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)434 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
435 struct snd_pcm_hw_params *params,
436 struct snd_soc_dai *cpu_dai)
437 {
438 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
439 unsigned int ofs = sai->soc_data->reg_offset;
440 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
441 unsigned int channels = params_channels(params);
442 u32 word_width = params_width(params);
443 u32 val_cr4 = 0, val_cr5 = 0;
444 u32 slots = (channels == 1) ? 2 : channels;
445 u32 slot_width = word_width;
446 int ret;
447
448 if (sai->slots)
449 slots = sai->slots;
450
451 if (sai->slot_width)
452 slot_width = sai->slot_width;
453
454 if (!sai->is_slave_mode) {
455 if (sai->bclk_ratio)
456 ret = fsl_sai_set_bclk(cpu_dai, tx,
457 sai->bclk_ratio *
458 params_rate(params));
459 else
460 ret = fsl_sai_set_bclk(cpu_dai, tx,
461 slots * slot_width *
462 params_rate(params));
463 if (ret)
464 return ret;
465
466 /* Do not enable the clock if it is already enabled */
467 if (!(sai->mclk_streams & BIT(substream->stream))) {
468 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
469 if (ret)
470 return ret;
471
472 sai->mclk_streams |= BIT(substream->stream);
473 }
474 }
475
476 if (!sai->is_dsp_mode)
477 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
478
479 val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
480 val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
481
482 if (sai->is_lsb_first)
483 val_cr5 |= FSL_SAI_CR5_FBT(0);
484 else
485 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
486
487 val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
488
489 /*
490 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
491 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
492 * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
493 * error.
494 */
495
496 if (!sai->is_slave_mode) {
497 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
498 regmap_update_bits(sai->regmap, FSL_SAI_TCR4(ofs),
499 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
500 val_cr4);
501 regmap_update_bits(sai->regmap, FSL_SAI_TCR5(ofs),
502 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
503 FSL_SAI_CR5_FBT_MASK, val_cr5);
504 regmap_write(sai->regmap, FSL_SAI_TMR,
505 ~0UL - ((1 << channels) - 1));
506 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
507 regmap_update_bits(sai->regmap, FSL_SAI_RCR4(ofs),
508 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
509 val_cr4);
510 regmap_update_bits(sai->regmap, FSL_SAI_RCR5(ofs),
511 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
512 FSL_SAI_CR5_FBT_MASK, val_cr5);
513 regmap_write(sai->regmap, FSL_SAI_RMR,
514 ~0UL - ((1 << channels) - 1));
515 }
516 }
517
518 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
519 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
520 val_cr4);
521 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
522 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
523 FSL_SAI_CR5_FBT_MASK, val_cr5);
524 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
525
526 return 0;
527 }
528
fsl_sai_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)529 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
530 struct snd_soc_dai *cpu_dai)
531 {
532 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
533 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
534
535 if (!sai->is_slave_mode &&
536 sai->mclk_streams & BIT(substream->stream)) {
537 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
538 sai->mclk_streams &= ~BIT(substream->stream);
539 }
540
541 return 0;
542 }
543
fsl_sai_config_disable(struct fsl_sai * sai,int dir)544 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir)
545 {
546 unsigned int ofs = sai->soc_data->reg_offset;
547 bool tx = dir == TX;
548 u32 xcsr, count = 100;
549
550 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
551 FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE, 0);
552
553 /* TERE will remain set till the end of current frame */
554 do {
555 udelay(10);
556 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);
557 } while (--count && xcsr & FSL_SAI_CSR_TERE);
558
559 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
560 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
561
562 /*
563 * For sai master mode, after several open/close sai,
564 * there will be no frame clock, and can't recover
565 * anymore. Add software reset to fix this issue.
566 * This is a hardware bug, and will be fix in the
567 * next sai version.
568 */
569 if (!sai->is_slave_mode) {
570 /* Software Reset */
571 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR);
572 /* Clear SR bit to finish the reset */
573 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0);
574 }
575 }
576
fsl_sai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)577 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
578 struct snd_soc_dai *cpu_dai)
579 {
580 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
581 unsigned int ofs = sai->soc_data->reg_offset;
582
583 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
584 int adir = tx ? RX : TX;
585 int dir = tx ? TX : RX;
586 u32 xcsr;
587
588 /*
589 * Asynchronous mode: Clear SYNC for both Tx and Rx.
590 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
591 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
592 */
593 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
594 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
595 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
596 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
597
598 /*
599 * It is recommended that the transmitter is the last enabled
600 * and the first disabled.
601 */
602 switch (cmd) {
603 case SNDRV_PCM_TRIGGER_START:
604 case SNDRV_PCM_TRIGGER_RESUME:
605 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
606 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
607 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
608
609 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
610 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
611 /*
612 * Enable the opposite direction for synchronous mode
613 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
614 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
615 *
616 * RM recommends to enable RE after TE for case 1 and to enable
617 * TE after RE for case 2, but we here may not always guarantee
618 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
619 * TE after RE, which is against what RM recommends but should
620 * be safe to do, judging by years of testing results.
621 */
622 if (fsl_sai_dir_is_synced(sai, adir))
623 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),
624 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
625
626 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
627 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
628 break;
629 case SNDRV_PCM_TRIGGER_STOP:
630 case SNDRV_PCM_TRIGGER_SUSPEND:
631 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
632 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
633 FSL_SAI_CSR_FRDE, 0);
634 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
635 FSL_SAI_CSR_xIE_MASK, 0);
636
637 /* Check if the opposite FRDE is also disabled */
638 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
639
640 /*
641 * If opposite stream provides clocks for synchronous mode and
642 * it is inactive, disable it before disabling the current one
643 */
644 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE))
645 fsl_sai_config_disable(sai, adir);
646
647 /*
648 * Disable current stream if either of:
649 * 1. current stream doesn't provide clocks for synchronous mode
650 * 2. current stream provides clocks for synchronous mode but no
651 * more stream is active.
652 */
653 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE))
654 fsl_sai_config_disable(sai, dir);
655
656 break;
657 default:
658 return -EINVAL;
659 }
660
661 return 0;
662 }
663
fsl_sai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)664 static int fsl_sai_startup(struct snd_pcm_substream *substream,
665 struct snd_soc_dai *cpu_dai)
666 {
667 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
668 unsigned int ofs = sai->soc_data->reg_offset;
669 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
670 int ret;
671
672 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
673 FSL_SAI_CR3_TRCE_MASK,
674 FSL_SAI_CR3_TRCE);
675
676 /*
677 * EDMA controller needs period size to be a multiple of
678 * tx/rx maxburst
679 */
680 if (sai->soc_data->use_edma)
681 snd_pcm_hw_constraint_step(substream->runtime, 0,
682 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
683 tx ? sai->dma_params_tx.maxburst :
684 sai->dma_params_rx.maxburst);
685
686 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
687 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
688
689 return ret;
690 }
691
fsl_sai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)692 static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
693 struct snd_soc_dai *cpu_dai)
694 {
695 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
696 unsigned int ofs = sai->soc_data->reg_offset;
697 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
698
699 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
700 FSL_SAI_CR3_TRCE_MASK, 0);
701 }
702
703 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
704 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
705 .set_sysclk = fsl_sai_set_dai_sysclk,
706 .set_fmt = fsl_sai_set_dai_fmt,
707 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
708 .hw_params = fsl_sai_hw_params,
709 .hw_free = fsl_sai_hw_free,
710 .trigger = fsl_sai_trigger,
711 .startup = fsl_sai_startup,
712 .shutdown = fsl_sai_shutdown,
713 };
714
fsl_sai_dai_probe(struct snd_soc_dai * cpu_dai)715 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
716 {
717 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
718 unsigned int ofs = sai->soc_data->reg_offset;
719
720 /* Software Reset for both Tx and Rx */
721 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
722 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
723 /* Clear SR bit to finish the reset */
724 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
725 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
726
727 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
728 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
729 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX);
730 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
731 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
732 FSL_SAI_MAXBURST_RX - 1);
733
734 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
735 &sai->dma_params_rx);
736
737 snd_soc_dai_set_drvdata(cpu_dai, sai);
738
739 return 0;
740 }
741
742 static struct snd_soc_dai_driver fsl_sai_dai_template = {
743 .probe = fsl_sai_dai_probe,
744 .playback = {
745 .stream_name = "CPU-Playback",
746 .channels_min = 1,
747 .channels_max = 32,
748 .rate_min = 8000,
749 .rate_max = 192000,
750 .rates = SNDRV_PCM_RATE_KNOT,
751 .formats = FSL_SAI_FORMATS,
752 },
753 .capture = {
754 .stream_name = "CPU-Capture",
755 .channels_min = 1,
756 .channels_max = 32,
757 .rate_min = 8000,
758 .rate_max = 192000,
759 .rates = SNDRV_PCM_RATE_KNOT,
760 .formats = FSL_SAI_FORMATS,
761 },
762 .ops = &fsl_sai_pcm_dai_ops,
763 };
764
765 static const struct snd_soc_component_driver fsl_component = {
766 .name = "fsl-sai",
767 };
768
769 static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
770 {FSL_SAI_TCR1(0), 0},
771 {FSL_SAI_TCR2(0), 0},
772 {FSL_SAI_TCR3(0), 0},
773 {FSL_SAI_TCR4(0), 0},
774 {FSL_SAI_TCR5(0), 0},
775 {FSL_SAI_TDR0, 0},
776 {FSL_SAI_TDR1, 0},
777 {FSL_SAI_TDR2, 0},
778 {FSL_SAI_TDR3, 0},
779 {FSL_SAI_TDR4, 0},
780 {FSL_SAI_TDR5, 0},
781 {FSL_SAI_TDR6, 0},
782 {FSL_SAI_TDR7, 0},
783 {FSL_SAI_TMR, 0},
784 {FSL_SAI_RCR1(0), 0},
785 {FSL_SAI_RCR2(0), 0},
786 {FSL_SAI_RCR3(0), 0},
787 {FSL_SAI_RCR4(0), 0},
788 {FSL_SAI_RCR5(0), 0},
789 {FSL_SAI_RMR, 0},
790 };
791
792 static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
793 {FSL_SAI_TCR1(8), 0},
794 {FSL_SAI_TCR2(8), 0},
795 {FSL_SAI_TCR3(8), 0},
796 {FSL_SAI_TCR4(8), 0},
797 {FSL_SAI_TCR5(8), 0},
798 {FSL_SAI_TDR0, 0},
799 {FSL_SAI_TDR1, 0},
800 {FSL_SAI_TDR2, 0},
801 {FSL_SAI_TDR3, 0},
802 {FSL_SAI_TDR4, 0},
803 {FSL_SAI_TDR5, 0},
804 {FSL_SAI_TDR6, 0},
805 {FSL_SAI_TDR7, 0},
806 {FSL_SAI_TMR, 0},
807 {FSL_SAI_RCR1(8), 0},
808 {FSL_SAI_RCR2(8), 0},
809 {FSL_SAI_RCR3(8), 0},
810 {FSL_SAI_RCR4(8), 0},
811 {FSL_SAI_RCR5(8), 0},
812 {FSL_SAI_RMR, 0},
813 {FSL_SAI_MCTL, 0},
814 {FSL_SAI_MDIV, 0},
815 };
816
fsl_sai_readable_reg(struct device * dev,unsigned int reg)817 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
818 {
819 struct fsl_sai *sai = dev_get_drvdata(dev);
820 unsigned int ofs = sai->soc_data->reg_offset;
821
822 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
823 return true;
824
825 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
826 return true;
827
828 switch (reg) {
829 case FSL_SAI_TFR0:
830 case FSL_SAI_TFR1:
831 case FSL_SAI_TFR2:
832 case FSL_SAI_TFR3:
833 case FSL_SAI_TFR4:
834 case FSL_SAI_TFR5:
835 case FSL_SAI_TFR6:
836 case FSL_SAI_TFR7:
837 case FSL_SAI_TMR:
838 case FSL_SAI_RDR0:
839 case FSL_SAI_RDR1:
840 case FSL_SAI_RDR2:
841 case FSL_SAI_RDR3:
842 case FSL_SAI_RDR4:
843 case FSL_SAI_RDR5:
844 case FSL_SAI_RDR6:
845 case FSL_SAI_RDR7:
846 case FSL_SAI_RFR0:
847 case FSL_SAI_RFR1:
848 case FSL_SAI_RFR2:
849 case FSL_SAI_RFR3:
850 case FSL_SAI_RFR4:
851 case FSL_SAI_RFR5:
852 case FSL_SAI_RFR6:
853 case FSL_SAI_RFR7:
854 case FSL_SAI_RMR:
855 case FSL_SAI_MCTL:
856 case FSL_SAI_MDIV:
857 case FSL_SAI_VERID:
858 case FSL_SAI_PARAM:
859 case FSL_SAI_TTCTN:
860 case FSL_SAI_RTCTN:
861 case FSL_SAI_TTCTL:
862 case FSL_SAI_TBCTN:
863 case FSL_SAI_TTCAP:
864 case FSL_SAI_RTCTL:
865 case FSL_SAI_RBCTN:
866 case FSL_SAI_RTCAP:
867 return true;
868 default:
869 return false;
870 }
871 }
872
fsl_sai_volatile_reg(struct device * dev,unsigned int reg)873 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
874 {
875 struct fsl_sai *sai = dev_get_drvdata(dev);
876 unsigned int ofs = sai->soc_data->reg_offset;
877
878 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
879 return true;
880
881 /* Set VERID and PARAM be volatile for reading value in probe */
882 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM))
883 return true;
884
885 switch (reg) {
886 case FSL_SAI_TFR0:
887 case FSL_SAI_TFR1:
888 case FSL_SAI_TFR2:
889 case FSL_SAI_TFR3:
890 case FSL_SAI_TFR4:
891 case FSL_SAI_TFR5:
892 case FSL_SAI_TFR6:
893 case FSL_SAI_TFR7:
894 case FSL_SAI_RFR0:
895 case FSL_SAI_RFR1:
896 case FSL_SAI_RFR2:
897 case FSL_SAI_RFR3:
898 case FSL_SAI_RFR4:
899 case FSL_SAI_RFR5:
900 case FSL_SAI_RFR6:
901 case FSL_SAI_RFR7:
902 case FSL_SAI_RDR0:
903 case FSL_SAI_RDR1:
904 case FSL_SAI_RDR2:
905 case FSL_SAI_RDR3:
906 case FSL_SAI_RDR4:
907 case FSL_SAI_RDR5:
908 case FSL_SAI_RDR6:
909 case FSL_SAI_RDR7:
910 return true;
911 default:
912 return false;
913 }
914 }
915
fsl_sai_writeable_reg(struct device * dev,unsigned int reg)916 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
917 {
918 struct fsl_sai *sai = dev_get_drvdata(dev);
919 unsigned int ofs = sai->soc_data->reg_offset;
920
921 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
922 return true;
923
924 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
925 return true;
926
927 switch (reg) {
928 case FSL_SAI_TDR0:
929 case FSL_SAI_TDR1:
930 case FSL_SAI_TDR2:
931 case FSL_SAI_TDR3:
932 case FSL_SAI_TDR4:
933 case FSL_SAI_TDR5:
934 case FSL_SAI_TDR6:
935 case FSL_SAI_TDR7:
936 case FSL_SAI_TMR:
937 case FSL_SAI_RMR:
938 case FSL_SAI_MCTL:
939 case FSL_SAI_MDIV:
940 case FSL_SAI_TTCTL:
941 case FSL_SAI_RTCTL:
942 return true;
943 default:
944 return false;
945 }
946 }
947
948 static struct regmap_config fsl_sai_regmap_config = {
949 .reg_bits = 32,
950 .reg_stride = 4,
951 .val_bits = 32,
952 .fast_io = true,
953
954 .max_register = FSL_SAI_RMR,
955 .reg_defaults = fsl_sai_reg_defaults_ofs0,
956 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
957 .readable_reg = fsl_sai_readable_reg,
958 .volatile_reg = fsl_sai_volatile_reg,
959 .writeable_reg = fsl_sai_writeable_reg,
960 .cache_type = REGCACHE_FLAT,
961 };
962
fsl_sai_probe(struct platform_device * pdev)963 static int fsl_sai_probe(struct platform_device *pdev)
964 {
965 struct device_node *np = pdev->dev.of_node;
966 struct fsl_sai *sai;
967 struct regmap *gpr;
968 struct resource *res;
969 void __iomem *base;
970 char tmp[8];
971 int irq, ret, i;
972 int index;
973
974 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
975 if (!sai)
976 return -ENOMEM;
977
978 sai->pdev = pdev;
979 sai->soc_data = of_device_get_match_data(&pdev->dev);
980
981 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
982
983 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
984 base = devm_ioremap_resource(&pdev->dev, res);
985 if (IS_ERR(base))
986 return PTR_ERR(base);
987
988 if (sai->soc_data->reg_offset == 8) {
989 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
990 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV;
991 fsl_sai_regmap_config.num_reg_defaults =
992 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
993 }
994
995 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
996 "bus", base, &fsl_sai_regmap_config);
997
998 /* Compatible with old DTB cases */
999 if (IS_ERR(sai->regmap))
1000 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
1001 "sai", base, &fsl_sai_regmap_config);
1002 if (IS_ERR(sai->regmap)) {
1003 dev_err(&pdev->dev, "regmap init failed\n");
1004 return PTR_ERR(sai->regmap);
1005 }
1006
1007 /* No error out for old DTB cases but only mark the clock NULL */
1008 sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
1009 if (IS_ERR(sai->bus_clk)) {
1010 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
1011 PTR_ERR(sai->bus_clk));
1012 sai->bus_clk = NULL;
1013 }
1014
1015 sai->mclk_clk[0] = sai->bus_clk;
1016 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
1017 sprintf(tmp, "mclk%d", i);
1018 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
1019 if (IS_ERR(sai->mclk_clk[i])) {
1020 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
1021 i + 1, PTR_ERR(sai->mclk_clk[i]));
1022 sai->mclk_clk[i] = NULL;
1023 }
1024 }
1025
1026 irq = platform_get_irq(pdev, 0);
1027 if (irq < 0)
1028 return irq;
1029
1030 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
1031 if (ret) {
1032 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
1033 return ret;
1034 }
1035
1036 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template,
1037 sizeof(fsl_sai_dai_template));
1038
1039 /* Sync Tx with Rx as default by following old DT binding */
1040 sai->synchronous[RX] = true;
1041 sai->synchronous[TX] = false;
1042 sai->cpu_dai_drv.symmetric_rates = 1;
1043 sai->cpu_dai_drv.symmetric_channels = 1;
1044 sai->cpu_dai_drv.symmetric_samplebits = 1;
1045
1046 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
1047 of_find_property(np, "fsl,sai-asynchronous", NULL)) {
1048 /* error out if both synchronous and asynchronous are present */
1049 dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
1050 return -EINVAL;
1051 }
1052
1053 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
1054 /* Sync Rx with Tx */
1055 sai->synchronous[RX] = false;
1056 sai->synchronous[TX] = true;
1057 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
1058 /* Discard all settings for asynchronous mode */
1059 sai->synchronous[RX] = false;
1060 sai->synchronous[TX] = false;
1061 sai->cpu_dai_drv.symmetric_rates = 0;
1062 sai->cpu_dai_drv.symmetric_channels = 0;
1063 sai->cpu_dai_drv.symmetric_samplebits = 0;
1064 }
1065
1066 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
1067 of_device_is_compatible(np, "fsl,imx6ul-sai")) {
1068 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
1069 if (IS_ERR(gpr)) {
1070 dev_err(&pdev->dev, "cannot find iomuxc registers\n");
1071 return PTR_ERR(gpr);
1072 }
1073
1074 index = of_alias_get_id(np, "sai");
1075 if (index < 0)
1076 return index;
1077
1078 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
1079 MCLK_DIR(index));
1080 }
1081
1082 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0;
1083 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0;
1084 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
1085 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
1086
1087 platform_set_drvdata(pdev, sai);
1088
1089 pm_runtime_enable(&pdev->dev);
1090
1091 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
1092 &sai->cpu_dai_drv, 1);
1093 if (ret)
1094 goto err_pm_disable;
1095
1096 if (sai->soc_data->use_imx_pcm) {
1097 ret = imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
1098 if (ret)
1099 goto err_pm_disable;
1100 } else {
1101 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1102 if (ret)
1103 goto err_pm_disable;
1104 }
1105
1106 return ret;
1107
1108 err_pm_disable:
1109 pm_runtime_disable(&pdev->dev);
1110
1111 return ret;
1112 }
1113
fsl_sai_remove(struct platform_device * pdev)1114 static int fsl_sai_remove(struct platform_device *pdev)
1115 {
1116 pm_runtime_disable(&pdev->dev);
1117
1118 return 0;
1119 }
1120
1121 static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
1122 .use_imx_pcm = false,
1123 .use_edma = false,
1124 .fifo_depth = 32,
1125 .reg_offset = 0,
1126 };
1127
1128 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
1129 .use_imx_pcm = true,
1130 .use_edma = false,
1131 .fifo_depth = 32,
1132 .reg_offset = 0,
1133 };
1134
1135 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
1136 .use_imx_pcm = true,
1137 .use_edma = false,
1138 .fifo_depth = 16,
1139 .reg_offset = 8,
1140 };
1141
1142 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
1143 .use_imx_pcm = true,
1144 .use_edma = false,
1145 .fifo_depth = 128,
1146 .reg_offset = 8,
1147 };
1148
1149 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
1150 .use_imx_pcm = true,
1151 .use_edma = true,
1152 .fifo_depth = 64,
1153 .reg_offset = 0,
1154 };
1155
1156 static const struct of_device_id fsl_sai_ids[] = {
1157 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1158 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1159 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1160 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1161 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1162 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1163 { /* sentinel */ }
1164 };
1165 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
1166
1167 #ifdef CONFIG_PM
fsl_sai_runtime_suspend(struct device * dev)1168 static int fsl_sai_runtime_suspend(struct device *dev)
1169 {
1170 struct fsl_sai *sai = dev_get_drvdata(dev);
1171
1172 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1173 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1174
1175 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1176 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1177
1178 clk_disable_unprepare(sai->bus_clk);
1179
1180 regcache_cache_only(sai->regmap, true);
1181 regcache_mark_dirty(sai->regmap);
1182
1183 return 0;
1184 }
1185
fsl_sai_runtime_resume(struct device * dev)1186 static int fsl_sai_runtime_resume(struct device *dev)
1187 {
1188 struct fsl_sai *sai = dev_get_drvdata(dev);
1189 unsigned int ofs = sai->soc_data->reg_offset;
1190 int ret;
1191
1192 ret = clk_prepare_enable(sai->bus_clk);
1193 if (ret) {
1194 dev_err(dev, "failed to enable bus clock: %d\n", ret);
1195 return ret;
1196 }
1197
1198 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
1199 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
1200 if (ret)
1201 goto disable_bus_clk;
1202 }
1203
1204 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
1205 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
1206 if (ret)
1207 goto disable_tx_clk;
1208 }
1209
1210 regcache_cache_only(sai->regmap, false);
1211 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
1212 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
1213 usleep_range(1000, 2000);
1214 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
1215 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
1216
1217 ret = regcache_sync(sai->regmap);
1218 if (ret)
1219 goto disable_rx_clk;
1220
1221 return 0;
1222
1223 disable_rx_clk:
1224 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1225 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1226 disable_tx_clk:
1227 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1228 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1229 disable_bus_clk:
1230 clk_disable_unprepare(sai->bus_clk);
1231
1232 return ret;
1233 }
1234 #endif /* CONFIG_PM */
1235
1236 static const struct dev_pm_ops fsl_sai_pm_ops = {
1237 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend,
1238 fsl_sai_runtime_resume, NULL)
1239 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1240 pm_runtime_force_resume)
1241 };
1242
1243 static struct platform_driver fsl_sai_driver = {
1244 .probe = fsl_sai_probe,
1245 .remove = fsl_sai_remove,
1246 .driver = {
1247 .name = "fsl-sai",
1248 .pm = &fsl_sai_pm_ops,
1249 .of_match_table = fsl_sai_ids,
1250 },
1251 };
1252 module_platform_driver(fsl_sai_driver);
1253
1254 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
1255 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
1256 MODULE_ALIAS("platform:fsl-sai");
1257 MODULE_LICENSE("GPL");
1258