1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Intel SST Haswell/Broadwell IPC Support
4 *
5 * Copyright (C) 2013, Intel Corporation. All rights reserved.
6 */
7
8 #include <linux/types.h>
9 #include <linux/kernel.h>
10 #include <linux/list.h>
11 #include <linux/device.h>
12 #include <linux/wait.h>
13 #include <linux/spinlock.h>
14 #include <linux/workqueue.h>
15 #include <linux/export.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
18 #include <linux/sched.h>
19 #include <linux/platform_device.h>
20 #include <linux/firmware.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/debugfs.h>
23 #include <linux/pm_runtime.h>
24 #include <sound/asound.h>
25
26 #include "sst-haswell-ipc.h"
27 #include "../common/sst-dsp.h"
28 #include "../common/sst-dsp-priv.h"
29 #include "../common/sst-ipc.h"
30
31 /* Global Message - Generic */
32 #define IPC_GLB_TYPE_SHIFT 24
33 #define IPC_GLB_TYPE_MASK (0x1f << IPC_GLB_TYPE_SHIFT)
34 #define IPC_GLB_TYPE(x) (x << IPC_GLB_TYPE_SHIFT)
35
36 /* Global Message - Reply */
37 #define IPC_GLB_REPLY_SHIFT 0
38 #define IPC_GLB_REPLY_MASK (0x1f << IPC_GLB_REPLY_SHIFT)
39 #define IPC_GLB_REPLY_TYPE(x) (x << IPC_GLB_REPLY_TYPE_SHIFT)
40
41 /* Stream Message - Generic */
42 #define IPC_STR_TYPE_SHIFT 20
43 #define IPC_STR_TYPE_MASK (0xf << IPC_STR_TYPE_SHIFT)
44 #define IPC_STR_TYPE(x) (x << IPC_STR_TYPE_SHIFT)
45 #define IPC_STR_ID_SHIFT 16
46 #define IPC_STR_ID_MASK (0xf << IPC_STR_ID_SHIFT)
47 #define IPC_STR_ID(x) (x << IPC_STR_ID_SHIFT)
48
49 /* Stream Message - Reply */
50 #define IPC_STR_REPLY_SHIFT 0
51 #define IPC_STR_REPLY_MASK (0x1f << IPC_STR_REPLY_SHIFT)
52
53 /* Stream Stage Message - Generic */
54 #define IPC_STG_TYPE_SHIFT 12
55 #define IPC_STG_TYPE_MASK (0xf << IPC_STG_TYPE_SHIFT)
56 #define IPC_STG_TYPE(x) (x << IPC_STG_TYPE_SHIFT)
57 #define IPC_STG_ID_SHIFT 10
58 #define IPC_STG_ID_MASK (0x3 << IPC_STG_ID_SHIFT)
59 #define IPC_STG_ID(x) (x << IPC_STG_ID_SHIFT)
60
61 /* Stream Stage Message - Reply */
62 #define IPC_STG_REPLY_SHIFT 0
63 #define IPC_STG_REPLY_MASK (0x1f << IPC_STG_REPLY_SHIFT)
64
65 /* Debug Log Message - Generic */
66 #define IPC_LOG_OP_SHIFT 20
67 #define IPC_LOG_OP_MASK (0xf << IPC_LOG_OP_SHIFT)
68 #define IPC_LOG_OP_TYPE(x) (x << IPC_LOG_OP_SHIFT)
69 #define IPC_LOG_ID_SHIFT 16
70 #define IPC_LOG_ID_MASK (0xf << IPC_LOG_ID_SHIFT)
71 #define IPC_LOG_ID(x) (x << IPC_LOG_ID_SHIFT)
72
73 /* Module Message */
74 #define IPC_MODULE_OPERATION_SHIFT 20
75 #define IPC_MODULE_OPERATION_MASK (0xf << IPC_MODULE_OPERATION_SHIFT)
76 #define IPC_MODULE_OPERATION(x) (x << IPC_MODULE_OPERATION_SHIFT)
77
78 #define IPC_MODULE_ID_SHIFT 16
79 #define IPC_MODULE_ID_MASK (0xf << IPC_MODULE_ID_SHIFT)
80 #define IPC_MODULE_ID(x) (x << IPC_MODULE_ID_SHIFT)
81
82 /* IPC message timeout (msecs) */
83 #define IPC_TIMEOUT_MSECS 300
84 #define IPC_BOOT_MSECS 200
85 #define IPC_MSG_WAIT 0
86 #define IPC_MSG_NOWAIT 1
87
88 /* Firmware Ready Message */
89 #define IPC_FW_READY (0x1 << 29)
90 #define IPC_STATUS_MASK (0x3 << 30)
91
92 #define IPC_EMPTY_LIST_SIZE 8
93 #define IPC_MAX_STREAMS 4
94
95 /* Mailbox */
96 #define IPC_MAX_MAILBOX_BYTES 256
97
98 #define INVALID_STREAM_HW_ID 0xffffffff
99
100 /* Global Message - Types and Replies */
101 enum ipc_glb_type {
102 IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
103 IPC_GLB_PERFORMANCE_MONITOR = 1, /* Performance monitoring actions */
104 IPC_GLB_ALLOCATE_STREAM = 3, /* Request to allocate new stream */
105 IPC_GLB_FREE_STREAM = 4, /* Request to free stream */
106 IPC_GLB_GET_FW_CAPABILITIES = 5, /* Retrieves firmware capabilities */
107 IPC_GLB_STREAM_MESSAGE = 6, /* Message directed to stream or its stages */
108 /* Request to store firmware context during D0->D3 transition */
109 IPC_GLB_REQUEST_DUMP = 7,
110 /* Request to restore firmware context during D3->D0 transition */
111 IPC_GLB_RESTORE_CONTEXT = 8,
112 IPC_GLB_GET_DEVICE_FORMATS = 9, /* Set device format */
113 IPC_GLB_SET_DEVICE_FORMATS = 10, /* Get device format */
114 IPC_GLB_SHORT_REPLY = 11,
115 IPC_GLB_ENTER_DX_STATE = 12,
116 IPC_GLB_GET_MIXER_STREAM_INFO = 13, /* Request mixer stream params */
117 IPC_GLB_DEBUG_LOG_MESSAGE = 14, /* Message to or from the debug logger. */
118 IPC_GLB_MODULE_OPERATION = 15, /* Message to loadable fw module */
119 IPC_GLB_REQUEST_TRANSFER = 16, /* < Request Transfer for host */
120 IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17, /* Maximum message number */
121 };
122
123 enum ipc_glb_reply {
124 IPC_GLB_REPLY_SUCCESS = 0, /* The operation was successful. */
125 IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1, /* Invalid parameter was passed. */
126 IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
127 IPC_GLB_REPLY_OUT_OF_RESOURCES = 3, /* No resources to satisfy the request. */
128 IPC_GLB_REPLY_BUSY = 4, /* The system or resource is busy. */
129 IPC_GLB_REPLY_PENDING = 5, /* The action was scheduled for processing. */
130 IPC_GLB_REPLY_FAILURE = 6, /* Critical error happened. */
131 IPC_GLB_REPLY_INVALID_REQUEST = 7, /* Request can not be completed. */
132 IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8, /* Processing stage was uninitialized. */
133 IPC_GLB_REPLY_NOT_FOUND = 9, /* Required resource can not be found. */
134 IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10, /* Source was not started. */
135 };
136
137 enum ipc_module_operation {
138 IPC_MODULE_NOTIFICATION = 0,
139 IPC_MODULE_ENABLE = 1,
140 IPC_MODULE_DISABLE = 2,
141 IPC_MODULE_GET_PARAMETER = 3,
142 IPC_MODULE_SET_PARAMETER = 4,
143 IPC_MODULE_GET_INFO = 5,
144 IPC_MODULE_MAX_MESSAGE
145 };
146
147 /* Stream Message - Types */
148 enum ipc_str_operation {
149 IPC_STR_RESET = 0,
150 IPC_STR_PAUSE = 1,
151 IPC_STR_RESUME = 2,
152 IPC_STR_STAGE_MESSAGE = 3,
153 IPC_STR_NOTIFICATION = 4,
154 IPC_STR_MAX_MESSAGE
155 };
156
157 /* Stream Stage Message Types */
158 enum ipc_stg_operation {
159 IPC_STG_GET_VOLUME = 0,
160 IPC_STG_SET_VOLUME,
161 IPC_STG_SET_WRITE_POSITION,
162 IPC_STG_SET_FX_ENABLE,
163 IPC_STG_SET_FX_DISABLE,
164 IPC_STG_SET_FX_GET_PARAM,
165 IPC_STG_SET_FX_SET_PARAM,
166 IPC_STG_SET_FX_GET_INFO,
167 IPC_STG_MUTE_LOOPBACK,
168 IPC_STG_MAX_MESSAGE
169 };
170
171 /* Stream Stage Message Types For Notification*/
172 enum ipc_stg_operation_notify {
173 IPC_POSITION_CHANGED = 0,
174 IPC_STG_GLITCH,
175 IPC_STG_MAX_NOTIFY
176 };
177
178 enum ipc_glitch_type {
179 IPC_GLITCH_UNDERRUN = 1,
180 IPC_GLITCH_DECODER_ERROR,
181 IPC_GLITCH_DOUBLED_WRITE_POS,
182 IPC_GLITCH_MAX
183 };
184
185 /* Debug Control */
186 enum ipc_debug_operation {
187 IPC_DEBUG_ENABLE_LOG = 0,
188 IPC_DEBUG_DISABLE_LOG = 1,
189 IPC_DEBUG_REQUEST_LOG_DUMP = 2,
190 IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
191 IPC_DEBUG_MAX_DEBUG_LOG
192 };
193
194 /* Firmware Ready */
195 struct sst_hsw_ipc_fw_ready {
196 u32 inbox_offset;
197 u32 outbox_offset;
198 u32 inbox_size;
199 u32 outbox_size;
200 u32 fw_info_size;
201 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
202 } __attribute__((packed));
203
204 struct sst_hsw_stream;
205 struct sst_hsw;
206
207 /* Stream infomation */
208 struct sst_hsw_stream {
209 /* configuration */
210 struct sst_hsw_ipc_stream_alloc_req request;
211 struct sst_hsw_ipc_stream_alloc_reply reply;
212 struct sst_hsw_ipc_stream_free_req free_req;
213
214 /* Mixer info */
215 u32 mute_volume[SST_HSW_NO_CHANNELS];
216 u32 mute[SST_HSW_NO_CHANNELS];
217
218 /* runtime info */
219 struct sst_hsw *hsw;
220 int host_id;
221 bool commited;
222 bool running;
223
224 /* Notification work */
225 struct work_struct notify_work;
226 u32 header;
227
228 /* Position info from DSP */
229 struct sst_hsw_ipc_stream_set_position wpos;
230 struct sst_hsw_ipc_stream_get_position rpos;
231 struct sst_hsw_ipc_stream_glitch_position glitch;
232
233 /* Volume info */
234 struct sst_hsw_ipc_volume_req vol_req;
235
236 /* driver callback */
237 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
238 void *pdata;
239
240 /* record the fw read position when playback */
241 snd_pcm_uframes_t old_position;
242 bool play_silence;
243 struct list_head node;
244 };
245
246 /* FW log ring information */
247 struct sst_hsw_log_stream {
248 dma_addr_t dma_addr;
249 unsigned char *dma_area;
250 unsigned char *ring_descr;
251 int pages;
252 int size;
253
254 /* Notification work */
255 struct work_struct notify_work;
256 wait_queue_head_t readers_wait_q;
257 struct mutex rw_mutex;
258
259 u32 last_pos;
260 u32 curr_pos;
261 u32 reader_pos;
262
263 /* fw log config */
264 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
265
266 struct sst_hsw *hsw;
267 };
268
269 /* SST Haswell IPC data */
270 struct sst_hsw {
271 struct device *dev;
272 struct sst_dsp *dsp;
273 struct platform_device *pdev_pcm;
274
275 /* FW config */
276 struct sst_hsw_ipc_fw_ready fw_ready;
277 struct sst_hsw_ipc_fw_version version;
278 bool fw_done;
279 struct sst_fw *sst_fw;
280
281 /* stream */
282 struct list_head stream_list;
283
284 /* global mixer */
285 struct sst_hsw_ipc_stream_info_reply mixer_info;
286 enum sst_hsw_volume_curve curve_type;
287 u32 curve_duration;
288 u32 mute[SST_HSW_NO_CHANNELS];
289 u32 mute_volume[SST_HSW_NO_CHANNELS];
290
291 /* DX */
292 struct sst_hsw_ipc_dx_reply dx;
293 void *dx_context;
294 dma_addr_t dx_context_paddr;
295 enum sst_hsw_device_id dx_dev;
296 enum sst_hsw_device_mclk dx_mclk;
297 enum sst_hsw_device_mode dx_mode;
298 u32 dx_clock_divider;
299
300 /* boot */
301 wait_queue_head_t boot_wait;
302 bool boot_complete;
303 bool shutdown;
304
305 /* IPC messaging */
306 struct sst_generic_ipc ipc;
307
308 /* FW log stream */
309 struct sst_hsw_log_stream log_stream;
310
311 /* flags bit field to track module state when resume from RTD3,
312 * each bit represent state (enabled/disabled) of single module */
313 u32 enabled_modules_rtd3;
314
315 /* buffer to store parameter lines */
316 u32 param_idx_w; /* write index */
317 u32 param_idx_r; /* read index */
318 u8 param_buf[WAVES_PARAM_LINES][WAVES_PARAM_COUNT];
319 };
320
321 #define CREATE_TRACE_POINTS
322 #include <trace/events/hswadsp.h>
323
msg_get_global_type(u32 msg)324 static inline u32 msg_get_global_type(u32 msg)
325 {
326 return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
327 }
328
msg_get_global_reply(u32 msg)329 static inline u32 msg_get_global_reply(u32 msg)
330 {
331 return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
332 }
333
msg_get_stream_type(u32 msg)334 static inline u32 msg_get_stream_type(u32 msg)
335 {
336 return (msg & IPC_STR_TYPE_MASK) >> IPC_STR_TYPE_SHIFT;
337 }
338
msg_get_stream_id(u32 msg)339 static inline u32 msg_get_stream_id(u32 msg)
340 {
341 return (msg & IPC_STR_ID_MASK) >> IPC_STR_ID_SHIFT;
342 }
343
msg_get_notify_reason(u32 msg)344 static inline u32 msg_get_notify_reason(u32 msg)
345 {
346 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
347 }
348
msg_get_module_operation(u32 msg)349 static inline u32 msg_get_module_operation(u32 msg)
350 {
351 return (msg & IPC_MODULE_OPERATION_MASK) >> IPC_MODULE_OPERATION_SHIFT;
352 }
353
msg_get_module_id(u32 msg)354 static inline u32 msg_get_module_id(u32 msg)
355 {
356 return (msg & IPC_MODULE_ID_MASK) >> IPC_MODULE_ID_SHIFT;
357 }
358
create_channel_map(enum sst_hsw_channel_config config)359 u32 create_channel_map(enum sst_hsw_channel_config config)
360 {
361 switch (config) {
362 case SST_HSW_CHANNEL_CONFIG_MONO:
363 return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
364 case SST_HSW_CHANNEL_CONFIG_STEREO:
365 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
366 | (SST_HSW_CHANNEL_RIGHT << 4));
367 case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
368 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
369 | (SST_HSW_CHANNEL_RIGHT << 4)
370 | (SST_HSW_CHANNEL_LFE << 8 ));
371 case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
372 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
373 | (SST_HSW_CHANNEL_CENTER << 4)
374 | (SST_HSW_CHANNEL_RIGHT << 8));
375 case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
376 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
377 | (SST_HSW_CHANNEL_CENTER << 4)
378 | (SST_HSW_CHANNEL_RIGHT << 8)
379 | (SST_HSW_CHANNEL_LFE << 12));
380 case SST_HSW_CHANNEL_CONFIG_QUATRO:
381 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
382 | (SST_HSW_CHANNEL_RIGHT << 4)
383 | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
384 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
385 case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
386 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
387 | (SST_HSW_CHANNEL_CENTER << 4)
388 | (SST_HSW_CHANNEL_RIGHT << 8)
389 | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
390 case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
391 return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
392 | (SST_HSW_CHANNEL_CENTER << 4)
393 | (SST_HSW_CHANNEL_RIGHT << 8)
394 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
395 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
396 case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
397 return (0xFF000000 | SST_HSW_CHANNEL_CENTER
398 | (SST_HSW_CHANNEL_LEFT << 4)
399 | (SST_HSW_CHANNEL_RIGHT << 8)
400 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
401 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
402 | (SST_HSW_CHANNEL_LFE << 20));
403 case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
404 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
405 | (SST_HSW_CHANNEL_LEFT << 4));
406 default:
407 return 0xFFFFFFFF;
408 }
409 }
410
get_stream_by_id(struct sst_hsw * hsw,int stream_id)411 static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
412 int stream_id)
413 {
414 struct sst_hsw_stream *stream;
415
416 list_for_each_entry(stream, &hsw->stream_list, node) {
417 if (stream->reply.stream_hw_id == stream_id)
418 return stream;
419 }
420
421 return NULL;
422 }
423
hsw_fw_ready(struct sst_hsw * hsw,u32 header)424 static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
425 {
426 struct sst_hsw_ipc_fw_ready fw_ready;
427 u32 offset;
428 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
429 char *tmp[5], *pinfo;
430 int i = 0;
431
432 offset = (header & 0x1FFFFFFF) << 3;
433
434 dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
435 header, offset);
436
437 /* copy data from the DSP FW ready offset */
438 sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
439
440 sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
441 fw_ready.inbox_size, fw_ready.outbox_offset,
442 fw_ready.outbox_size);
443
444 hsw->boot_complete = true;
445 wake_up(&hsw->boot_wait);
446
447 dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
448 fw_ready.inbox_offset, fw_ready.inbox_size);
449 dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
450 fw_ready.outbox_offset, fw_ready.outbox_size);
451 if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
452 fw_ready.fw_info[fw_ready.fw_info_size] = 0;
453 dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
454
455 /* log the FW version info got from the mailbox here. */
456 memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
457 pinfo = &fw_info[0];
458 for (i = 0; i < ARRAY_SIZE(tmp); i++)
459 tmp[i] = strsep(&pinfo, " ");
460 dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
461 "version: %s.%s, build %s, source commit id: %s\n",
462 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
463 }
464 }
465
hsw_notification_work(struct work_struct * work)466 static void hsw_notification_work(struct work_struct *work)
467 {
468 struct sst_hsw_stream *stream = container_of(work,
469 struct sst_hsw_stream, notify_work);
470 struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
471 struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
472 struct sst_hsw *hsw = stream->hsw;
473 u32 reason;
474
475 reason = msg_get_notify_reason(stream->header);
476
477 switch (reason) {
478 case IPC_STG_GLITCH:
479 trace_ipc_notification("DSP stream under/overrun",
480 stream->reply.stream_hw_id);
481 sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
482
483 dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
484 glitch->glitch_type, glitch->present_pos,
485 glitch->write_pos);
486 break;
487
488 case IPC_POSITION_CHANGED:
489 trace_ipc_notification("DSP stream position changed for",
490 stream->reply.stream_hw_id);
491 sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
492
493 if (stream->notify_position)
494 stream->notify_position(stream, stream->pdata);
495
496 break;
497 default:
498 dev_err(hsw->dev, "error: unknown notification 0x%x\n",
499 stream->header);
500 break;
501 }
502
503 /* tell DSP that notification has been handled */
504 sst_dsp_shim_update_bits(hsw->dsp, SST_IPCD,
505 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
506
507 /* unmask busy interrupt */
508 sst_dsp_shim_update_bits(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
509 }
510
hsw_stream_update(struct sst_hsw * hsw,struct ipc_message * msg)511 static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
512 {
513 struct sst_hsw_stream *stream;
514 u32 header = msg->tx.header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
515 u32 stream_id = msg_get_stream_id(header);
516 u32 stream_msg = msg_get_stream_type(header);
517
518 stream = get_stream_by_id(hsw, stream_id);
519 if (stream == NULL)
520 return;
521
522 switch (stream_msg) {
523 case IPC_STR_STAGE_MESSAGE:
524 case IPC_STR_NOTIFICATION:
525 break;
526 case IPC_STR_RESET:
527 trace_ipc_notification("stream reset", stream->reply.stream_hw_id);
528 break;
529 case IPC_STR_PAUSE:
530 stream->running = false;
531 trace_ipc_notification("stream paused",
532 stream->reply.stream_hw_id);
533 break;
534 case IPC_STR_RESUME:
535 stream->running = true;
536 trace_ipc_notification("stream running",
537 stream->reply.stream_hw_id);
538 break;
539 }
540 }
541
hsw_process_reply(struct sst_hsw * hsw,u32 header)542 static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
543 {
544 struct ipc_message *msg;
545 u32 reply = msg_get_global_reply(header);
546
547 trace_ipc_reply("processing -->", header);
548
549 msg = sst_ipc_reply_find_msg(&hsw->ipc, header);
550 if (msg == NULL) {
551 trace_ipc_error("error: can't find message header", header);
552 return -EIO;
553 }
554
555 msg->rx.header = header;
556 /* first process the header */
557 switch (reply) {
558 case IPC_GLB_REPLY_PENDING:
559 trace_ipc_pending_reply("received", header);
560 msg->pending = true;
561 hsw->ipc.pending = true;
562 return 1;
563 case IPC_GLB_REPLY_SUCCESS:
564 if (msg->pending) {
565 trace_ipc_pending_reply("completed", header);
566 sst_dsp_inbox_read(hsw->dsp, msg->rx.data,
567 msg->rx.size);
568 hsw->ipc.pending = false;
569 } else {
570 /* copy data from the DSP */
571 sst_dsp_outbox_read(hsw->dsp, msg->rx.data,
572 msg->rx.size);
573 }
574 break;
575 /* these will be rare - but useful for debug */
576 case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
577 trace_ipc_error("error: unknown message type", header);
578 msg->errno = -EBADMSG;
579 break;
580 case IPC_GLB_REPLY_OUT_OF_RESOURCES:
581 trace_ipc_error("error: out of resources", header);
582 msg->errno = -ENOMEM;
583 break;
584 case IPC_GLB_REPLY_BUSY:
585 trace_ipc_error("error: reply busy", header);
586 msg->errno = -EBUSY;
587 break;
588 case IPC_GLB_REPLY_FAILURE:
589 trace_ipc_error("error: reply failure", header);
590 msg->errno = -EINVAL;
591 break;
592 case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
593 trace_ipc_error("error: stage uninitialized", header);
594 msg->errno = -EINVAL;
595 break;
596 case IPC_GLB_REPLY_NOT_FOUND:
597 trace_ipc_error("error: reply not found", header);
598 msg->errno = -EINVAL;
599 break;
600 case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
601 trace_ipc_error("error: source not started", header);
602 msg->errno = -EINVAL;
603 break;
604 case IPC_GLB_REPLY_INVALID_REQUEST:
605 trace_ipc_error("error: invalid request", header);
606 msg->errno = -EINVAL;
607 break;
608 case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
609 trace_ipc_error("error: invalid parameter", header);
610 msg->errno = -EINVAL;
611 break;
612 default:
613 trace_ipc_error("error: unknown reply", header);
614 msg->errno = -EINVAL;
615 break;
616 }
617
618 /* update any stream states */
619 if (msg_get_global_type(header) == IPC_GLB_STREAM_MESSAGE)
620 hsw_stream_update(hsw, msg);
621
622 /* wake up and return the error if we have waiters on this message ? */
623 list_del(&msg->list);
624 sst_ipc_tx_msg_reply_complete(&hsw->ipc, msg);
625
626 return 1;
627 }
628
hsw_module_message(struct sst_hsw * hsw,u32 header)629 static int hsw_module_message(struct sst_hsw *hsw, u32 header)
630 {
631 u32 operation, module_id;
632 int handled = 0;
633
634 operation = msg_get_module_operation(header);
635 module_id = msg_get_module_id(header);
636 dev_dbg(hsw->dev, "received module message header: 0x%8.8x\n",
637 header);
638 dev_dbg(hsw->dev, "operation: 0x%8.8x module_id: 0x%8.8x\n",
639 operation, module_id);
640
641 switch (operation) {
642 case IPC_MODULE_NOTIFICATION:
643 dev_dbg(hsw->dev, "module notification received");
644 handled = 1;
645 break;
646 default:
647 handled = hsw_process_reply(hsw, header);
648 break;
649 }
650
651 return handled;
652 }
653
hsw_stream_message(struct sst_hsw * hsw,u32 header)654 static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
655 {
656 u32 stream_msg, stream_id;
657 struct sst_hsw_stream *stream;
658 int handled = 0;
659
660 stream_msg = msg_get_stream_type(header);
661 stream_id = msg_get_stream_id(header);
662
663 stream = get_stream_by_id(hsw, stream_id);
664 if (stream == NULL)
665 return handled;
666
667 stream->header = header;
668
669 switch (stream_msg) {
670 case IPC_STR_STAGE_MESSAGE:
671 dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
672 header);
673 break;
674 case IPC_STR_NOTIFICATION:
675 schedule_work(&stream->notify_work);
676 break;
677 default:
678 /* handle pending message complete request */
679 handled = hsw_process_reply(hsw, header);
680 break;
681 }
682
683 return handled;
684 }
685
hsw_log_message(struct sst_hsw * hsw,u32 header)686 static int hsw_log_message(struct sst_hsw *hsw, u32 header)
687 {
688 u32 operation = (header & IPC_LOG_OP_MASK) >> IPC_LOG_OP_SHIFT;
689 struct sst_hsw_log_stream *stream = &hsw->log_stream;
690 int ret = 1;
691
692 if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
693 dev_err(hsw->dev,
694 "error: log msg not implemented 0x%8.8x\n", header);
695 return 0;
696 }
697
698 mutex_lock(&stream->rw_mutex);
699 stream->last_pos = stream->curr_pos;
700 sst_dsp_inbox_read(
701 hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
702 mutex_unlock(&stream->rw_mutex);
703
704 schedule_work(&stream->notify_work);
705
706 return ret;
707 }
708
hsw_process_notification(struct sst_hsw * hsw)709 static int hsw_process_notification(struct sst_hsw *hsw)
710 {
711 struct sst_dsp *sst = hsw->dsp;
712 u32 type, header;
713 int handled = 1;
714
715 header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
716 type = msg_get_global_type(header);
717
718 trace_ipc_request("processing -->", header);
719
720 /* FW Ready is a special case */
721 if (!hsw->boot_complete && header & IPC_FW_READY) {
722 hsw_fw_ready(hsw, header);
723 return handled;
724 }
725
726 switch (type) {
727 case IPC_GLB_GET_FW_VERSION:
728 case IPC_GLB_ALLOCATE_STREAM:
729 case IPC_GLB_FREE_STREAM:
730 case IPC_GLB_GET_FW_CAPABILITIES:
731 case IPC_GLB_REQUEST_DUMP:
732 case IPC_GLB_GET_DEVICE_FORMATS:
733 case IPC_GLB_SET_DEVICE_FORMATS:
734 case IPC_GLB_ENTER_DX_STATE:
735 case IPC_GLB_GET_MIXER_STREAM_INFO:
736 case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
737 case IPC_GLB_RESTORE_CONTEXT:
738 case IPC_GLB_SHORT_REPLY:
739 dev_err(hsw->dev, "error: message type %d header 0x%x\n",
740 type, header);
741 break;
742 case IPC_GLB_STREAM_MESSAGE:
743 handled = hsw_stream_message(hsw, header);
744 break;
745 case IPC_GLB_DEBUG_LOG_MESSAGE:
746 handled = hsw_log_message(hsw, header);
747 break;
748 case IPC_GLB_MODULE_OPERATION:
749 handled = hsw_module_message(hsw, header);
750 break;
751 default:
752 dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
753 type, header);
754 break;
755 }
756
757 return handled;
758 }
759
hsw_irq_thread(int irq,void * context)760 static irqreturn_t hsw_irq_thread(int irq, void *context)
761 {
762 struct sst_dsp *sst = (struct sst_dsp *) context;
763 struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
764 struct sst_generic_ipc *ipc = &hsw->ipc;
765 u32 ipcx, ipcd;
766 unsigned long flags;
767
768 spin_lock_irqsave(&sst->spinlock, flags);
769
770 ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
771 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
772
773 /* reply message from DSP */
774 if (ipcx & SST_IPCX_DONE) {
775
776 /* Handle Immediate reply from DSP Core */
777 hsw_process_reply(hsw, ipcx);
778
779 /* clear DONE bit - tell DSP we have completed */
780 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
781 SST_IPCX_DONE, 0);
782
783 /* unmask Done interrupt */
784 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
785 SST_IMRX_DONE, 0);
786 }
787
788 /* new message from DSP */
789 if (ipcd & SST_IPCD_BUSY) {
790
791 /* Handle Notification and Delayed reply from DSP Core */
792 hsw_process_notification(hsw);
793
794 /* clear BUSY bit and set DONE bit - accept new messages */
795 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
796 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
797
798 /* unmask busy interrupt */
799 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
800 SST_IMRX_BUSY, 0);
801 }
802
803 spin_unlock_irqrestore(&sst->spinlock, flags);
804
805 /* continue to send any remaining messages... */
806 schedule_work(&ipc->kwork);
807
808 return IRQ_HANDLED;
809 }
810
sst_hsw_fw_get_version(struct sst_hsw * hsw,struct sst_hsw_ipc_fw_version * version)811 int sst_hsw_fw_get_version(struct sst_hsw *hsw,
812 struct sst_hsw_ipc_fw_version *version)
813 {
814 struct sst_ipc_message request = {0}, reply = {0};
815 int ret;
816
817 request.header = IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION);
818 reply.data = version;
819 reply.size = sizeof(*version);
820 ret = sst_ipc_tx_message_wait(&hsw->ipc, request, &reply);
821 if (ret < 0)
822 dev_err(hsw->dev, "error: get version failed\n");
823
824 return ret;
825 }
826
827 /* Mixer Controls */
sst_hsw_stream_get_volume(struct sst_hsw * hsw,struct sst_hsw_stream * stream,u32 stage_id,u32 channel,u32 * volume)828 int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
829 u32 stage_id, u32 channel, u32 *volume)
830 {
831 if (channel > 1)
832 return -EINVAL;
833
834 sst_dsp_read(hsw->dsp, volume,
835 stream->reply.volume_register_address[channel],
836 sizeof(*volume));
837
838 return 0;
839 }
840
841 /* stream volume */
sst_hsw_stream_set_volume(struct sst_hsw * hsw,struct sst_hsw_stream * stream,u32 stage_id,u32 channel,u32 volume)842 int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
843 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
844 {
845 struct sst_hsw_ipc_volume_req *req;
846 struct sst_ipc_message request;
847 int ret;
848
849 trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
850
851 if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
852 return -EINVAL;
853
854 request.header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
855 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
856 request.header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
857 request.header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
858 request.header |= (stage_id << IPC_STG_ID_SHIFT);
859
860 req = &stream->vol_req;
861 req->target_volume = volume;
862
863 /* set both at same time ? */
864 if (channel == SST_HSW_CHANNELS_ALL) {
865 if (hsw->mute[0] && hsw->mute[1]) {
866 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
867 return 0;
868 } else if (hsw->mute[0])
869 req->channel = 1;
870 else if (hsw->mute[1])
871 req->channel = 0;
872 else
873 req->channel = SST_HSW_CHANNELS_ALL;
874 } else {
875 /* set only 1 channel */
876 if (hsw->mute[channel]) {
877 hsw->mute_volume[channel] = volume;
878 return 0;
879 }
880 req->channel = channel;
881 }
882
883 request.data = req;
884 request.size = sizeof(*req);
885 ret = sst_ipc_tx_message_wait(&hsw->ipc, request, NULL);
886 if (ret < 0) {
887 dev_err(hsw->dev, "error: set stream volume failed\n");
888 return ret;
889 }
890
891 return 0;
892 }
893
sst_hsw_mixer_get_volume(struct sst_hsw * hsw,u32 stage_id,u32 channel,u32 * volume)894 int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
895 u32 *volume)
896 {
897 if (channel > 1)
898 return -EINVAL;
899
900 sst_dsp_read(hsw->dsp, volume,
901 hsw->mixer_info.volume_register_address[channel],
902 sizeof(*volume));
903
904 return 0;
905 }
906
907 /* global mixer volume */
sst_hsw_mixer_set_volume(struct sst_hsw * hsw,u32 stage_id,u32 channel,u32 volume)908 int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
909 u32 volume)
910 {
911 struct sst_hsw_ipc_volume_req req;
912 struct sst_ipc_message request;
913 int ret;
914
915 trace_ipc_request("set mixer volume", volume);
916
917 if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
918 return -EINVAL;
919
920 /* set both at same time ? */
921 if (channel == SST_HSW_CHANNELS_ALL) {
922 if (hsw->mute[0] && hsw->mute[1]) {
923 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
924 return 0;
925 } else if (hsw->mute[0])
926 req.channel = 1;
927 else if (hsw->mute[1])
928 req.channel = 0;
929 else
930 req.channel = SST_HSW_CHANNELS_ALL;
931 } else {
932 /* set only 1 channel */
933 if (hsw->mute[channel]) {
934 hsw->mute_volume[channel] = volume;
935 return 0;
936 }
937 req.channel = channel;
938 }
939
940 request.header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
941 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
942 request.header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
943 request.header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
944 request.header |= (stage_id << IPC_STG_ID_SHIFT);
945
946 req.curve_duration = hsw->curve_duration;
947 req.curve_type = hsw->curve_type;
948 req.target_volume = volume;
949
950 request.data = &req;
951 request.size = sizeof(req);
952 ret = sst_ipc_tx_message_wait(&hsw->ipc, request, NULL);
953 if (ret < 0) {
954 dev_err(hsw->dev, "error: set mixer volume failed\n");
955 return ret;
956 }
957
958 return 0;
959 }
960
961 /* Stream API */
sst_hsw_stream_new(struct sst_hsw * hsw,int id,u32 (* notify_position)(struct sst_hsw_stream * stream,void * data),void * data)962 struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
963 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
964 void *data)
965 {
966 struct sst_hsw_stream *stream;
967 struct sst_dsp *sst = hsw->dsp;
968 unsigned long flags;
969
970 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
971 if (stream == NULL)
972 return NULL;
973
974 spin_lock_irqsave(&sst->spinlock, flags);
975 stream->reply.stream_hw_id = INVALID_STREAM_HW_ID;
976 list_add(&stream->node, &hsw->stream_list);
977 stream->notify_position = notify_position;
978 stream->pdata = data;
979 stream->hsw = hsw;
980 stream->host_id = id;
981
982 /* work to process notification messages */
983 INIT_WORK(&stream->notify_work, hsw_notification_work);
984 spin_unlock_irqrestore(&sst->spinlock, flags);
985
986 return stream;
987 }
988
sst_hsw_stream_free(struct sst_hsw * hsw,struct sst_hsw_stream * stream)989 int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
990 {
991 struct sst_ipc_message request;
992 int ret = 0;
993 struct sst_dsp *sst = hsw->dsp;
994 unsigned long flags;
995
996 if (!stream) {
997 dev_warn(hsw->dev, "warning: stream is NULL, no stream to free, ignore it.\n");
998 return 0;
999 }
1000
1001 /* dont free DSP streams that are not commited */
1002 if (!stream->commited)
1003 goto out;
1004
1005 trace_ipc_request("stream free", stream->host_id);
1006
1007 stream->free_req.stream_id = stream->reply.stream_hw_id;
1008 request.header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
1009 request.data = &stream->free_req;
1010 request.size = sizeof(stream->free_req);
1011
1012 ret = sst_ipc_tx_message_wait(&hsw->ipc, request, NULL);
1013 if (ret < 0) {
1014 dev_err(hsw->dev, "error: free stream %d failed\n",
1015 stream->free_req.stream_id);
1016 return -EAGAIN;
1017 }
1018
1019 trace_hsw_stream_free_req(stream, &stream->free_req);
1020
1021 out:
1022 cancel_work_sync(&stream->notify_work);
1023 spin_lock_irqsave(&sst->spinlock, flags);
1024 list_del(&stream->node);
1025 kfree(stream);
1026 spin_unlock_irqrestore(&sst->spinlock, flags);
1027
1028 return ret;
1029 }
1030
sst_hsw_stream_set_bits(struct sst_hsw * hsw,struct sst_hsw_stream * stream,enum sst_hsw_bitdepth bits)1031 int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
1032 struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
1033 {
1034 if (stream->commited) {
1035 dev_err(hsw->dev, "error: stream committed for set bits\n");
1036 return -EINVAL;
1037 }
1038
1039 stream->request.format.bitdepth = bits;
1040 return 0;
1041 }
1042
sst_hsw_stream_set_channels(struct sst_hsw * hsw,struct sst_hsw_stream * stream,int channels)1043 int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
1044 struct sst_hsw_stream *stream, int channels)
1045 {
1046 if (stream->commited) {
1047 dev_err(hsw->dev, "error: stream committed for set channels\n");
1048 return -EINVAL;
1049 }
1050
1051 stream->request.format.ch_num = channels;
1052 return 0;
1053 }
1054
sst_hsw_stream_set_rate(struct sst_hsw * hsw,struct sst_hsw_stream * stream,int rate)1055 int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
1056 struct sst_hsw_stream *stream, int rate)
1057 {
1058 if (stream->commited) {
1059 dev_err(hsw->dev, "error: stream committed for set rate\n");
1060 return -EINVAL;
1061 }
1062
1063 stream->request.format.frequency = rate;
1064 return 0;
1065 }
1066
sst_hsw_stream_set_map_config(struct sst_hsw * hsw,struct sst_hsw_stream * stream,u32 map,enum sst_hsw_channel_config config)1067 int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
1068 struct sst_hsw_stream *stream, u32 map,
1069 enum sst_hsw_channel_config config)
1070 {
1071 if (stream->commited) {
1072 dev_err(hsw->dev, "error: stream committed for set map\n");
1073 return -EINVAL;
1074 }
1075
1076 stream->request.format.map = map;
1077 stream->request.format.config = config;
1078 return 0;
1079 }
1080
sst_hsw_stream_set_style(struct sst_hsw * hsw,struct sst_hsw_stream * stream,enum sst_hsw_interleaving style)1081 int sst_hsw_stream_set_style(struct sst_hsw *hsw,
1082 struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
1083 {
1084 if (stream->commited) {
1085 dev_err(hsw->dev, "error: stream committed for set style\n");
1086 return -EINVAL;
1087 }
1088
1089 stream->request.format.style = style;
1090 return 0;
1091 }
1092
sst_hsw_stream_set_valid(struct sst_hsw * hsw,struct sst_hsw_stream * stream,u32 bits)1093 int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
1094 struct sst_hsw_stream *stream, u32 bits)
1095 {
1096 if (stream->commited) {
1097 dev_err(hsw->dev, "error: stream committed for set valid bits\n");
1098 return -EINVAL;
1099 }
1100
1101 stream->request.format.valid_bit = bits;
1102 return 0;
1103 }
1104
1105 /* Stream Configuration */
sst_hsw_stream_format(struct sst_hsw * hsw,struct sst_hsw_stream * stream,enum sst_hsw_stream_path_id path_id,enum sst_hsw_stream_type stream_type,enum sst_hsw_stream_format format_id)1106 int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1107 enum sst_hsw_stream_path_id path_id,
1108 enum sst_hsw_stream_type stream_type,
1109 enum sst_hsw_stream_format format_id)
1110 {
1111 if (stream->commited) {
1112 dev_err(hsw->dev, "error: stream committed for set format\n");
1113 return -EINVAL;
1114 }
1115
1116 stream->request.path_id = path_id;
1117 stream->request.stream_type = stream_type;
1118 stream->request.format_id = format_id;
1119
1120 trace_hsw_stream_alloc_request(stream, &stream->request);
1121
1122 return 0;
1123 }
1124
sst_hsw_stream_buffer(struct sst_hsw * hsw,struct sst_hsw_stream * stream,u32 ring_pt_address,u32 num_pages,u32 ring_size,u32 ring_offset,u32 ring_first_pfn)1125 int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1126 u32 ring_pt_address, u32 num_pages,
1127 u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
1128 {
1129 if (stream->commited) {
1130 dev_err(hsw->dev, "error: stream committed for buffer\n");
1131 return -EINVAL;
1132 }
1133
1134 stream->request.ringinfo.ring_pt_address = ring_pt_address;
1135 stream->request.ringinfo.num_pages = num_pages;
1136 stream->request.ringinfo.ring_size = ring_size;
1137 stream->request.ringinfo.ring_offset = ring_offset;
1138 stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
1139
1140 trace_hsw_stream_buffer(stream);
1141
1142 return 0;
1143 }
1144
sst_hsw_stream_set_module_info(struct sst_hsw * hsw,struct sst_hsw_stream * stream,struct sst_module_runtime * runtime)1145 int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
1146 struct sst_hsw_stream *stream, struct sst_module_runtime *runtime)
1147 {
1148 struct sst_hsw_module_map *map = &stream->request.map;
1149 struct sst_dsp *dsp = sst_hsw_get_dsp(hsw);
1150 struct sst_module *module = runtime->module;
1151
1152 if (stream->commited) {
1153 dev_err(hsw->dev, "error: stream committed for set module\n");
1154 return -EINVAL;
1155 }
1156
1157 /* only support initial module atm */
1158 map->module_entries_count = 1;
1159 map->module_entries[0].module_id = module->id;
1160 map->module_entries[0].entry_point = module->entry;
1161
1162 stream->request.persistent_mem.offset =
1163 sst_dsp_get_offset(dsp, runtime->persistent_offset, SST_MEM_DRAM);
1164 stream->request.persistent_mem.size = module->persistent_size;
1165
1166 stream->request.scratch_mem.offset =
1167 sst_dsp_get_offset(dsp, dsp->scratch_offset, SST_MEM_DRAM);
1168 stream->request.scratch_mem.size = dsp->scratch_size;
1169
1170 dev_dbg(hsw->dev, "module %d runtime %d using:\n", module->id,
1171 runtime->id);
1172 dev_dbg(hsw->dev, " persistent offset 0x%x bytes 0x%x\n",
1173 stream->request.persistent_mem.offset,
1174 stream->request.persistent_mem.size);
1175 dev_dbg(hsw->dev, " scratch offset 0x%x bytes 0x%x\n",
1176 stream->request.scratch_mem.offset,
1177 stream->request.scratch_mem.size);
1178
1179 return 0;
1180 }
1181
sst_hsw_stream_commit(struct sst_hsw * hsw,struct sst_hsw_stream * stream)1182 int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1183 {
1184 struct sst_ipc_message request, reply = {0};
1185 int ret;
1186
1187 if (!stream) {
1188 dev_warn(hsw->dev, "warning: stream is NULL, no stream to commit, ignore it.\n");
1189 return 0;
1190 }
1191
1192 if (stream->commited) {
1193 dev_warn(hsw->dev, "warning: stream is already committed, ignore it.\n");
1194 return 0;
1195 }
1196
1197 trace_ipc_request("stream alloc", stream->host_id);
1198
1199 request.header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
1200 request.data = &stream->request;
1201 request.size = sizeof(stream->request);
1202 reply.data = &stream->reply;
1203 reply.size = sizeof(stream->reply);
1204
1205 ret = sst_ipc_tx_message_wait(&hsw->ipc, request, &reply);
1206 if (ret < 0) {
1207 dev_err(hsw->dev, "error: stream commit failed\n");
1208 return ret;
1209 }
1210
1211 stream->commited = true;
1212 trace_hsw_stream_alloc_reply(stream);
1213
1214 return 0;
1215 }
1216
sst_hsw_stream_get_old_position(struct sst_hsw * hsw,struct sst_hsw_stream * stream)1217 snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw,
1218 struct sst_hsw_stream *stream)
1219 {
1220 return stream->old_position;
1221 }
1222
sst_hsw_stream_set_old_position(struct sst_hsw * hsw,struct sst_hsw_stream * stream,snd_pcm_uframes_t val)1223 void sst_hsw_stream_set_old_position(struct sst_hsw *hsw,
1224 struct sst_hsw_stream *stream, snd_pcm_uframes_t val)
1225 {
1226 stream->old_position = val;
1227 }
1228
sst_hsw_stream_get_silence_start(struct sst_hsw * hsw,struct sst_hsw_stream * stream)1229 bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw,
1230 struct sst_hsw_stream *stream)
1231 {
1232 return stream->play_silence;
1233 }
1234
sst_hsw_stream_set_silence_start(struct sst_hsw * hsw,struct sst_hsw_stream * stream,bool val)1235 void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw,
1236 struct sst_hsw_stream *stream, bool val)
1237 {
1238 stream->play_silence = val;
1239 }
1240
1241 /* Stream Information - these calls could be inline but we want the IPC
1242 ABI to be opaque to client PCM drivers to cope with any future ABI changes */
sst_hsw_mixer_get_info(struct sst_hsw * hsw)1243 int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
1244 {
1245 struct sst_ipc_message request = {0}, reply = {0};
1246 int ret;
1247
1248 request.header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
1249 reply.data = &hsw->mixer_info;
1250 reply.size = sizeof(hsw->mixer_info);
1251
1252 trace_ipc_request("get global mixer info", 0);
1253
1254 ret = sst_ipc_tx_message_wait(&hsw->ipc, request, &reply);
1255 if (ret < 0) {
1256 dev_err(hsw->dev, "error: get stream info failed\n");
1257 return ret;
1258 }
1259
1260 trace_hsw_mixer_info_reply(&hsw->mixer_info);
1261
1262 return 0;
1263 }
1264
1265 /* Send stream command */
sst_hsw_stream_operations(struct sst_hsw * hsw,int type,int stream_id,int wait)1266 static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
1267 int stream_id, int wait)
1268 {
1269 struct sst_ipc_message request = {0};
1270
1271 request.header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE);
1272 request.header |= IPC_STR_TYPE(type) | (stream_id << IPC_STR_ID_SHIFT);
1273
1274 if (wait)
1275 return sst_ipc_tx_message_wait(&hsw->ipc, request, NULL);
1276 else
1277 return sst_ipc_tx_message_nowait(&hsw->ipc, request);
1278 }
1279
1280 /* Stream ALSA trigger operations */
sst_hsw_stream_pause(struct sst_hsw * hsw,struct sst_hsw_stream * stream,int wait)1281 int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1282 int wait)
1283 {
1284 int ret;
1285
1286 if (!stream) {
1287 dev_warn(hsw->dev, "warning: stream is NULL, no stream to pause, ignore it.\n");
1288 return 0;
1289 }
1290
1291 trace_ipc_request("stream pause", stream->reply.stream_hw_id);
1292
1293 ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
1294 stream->reply.stream_hw_id, wait);
1295 if (ret < 0)
1296 dev_err(hsw->dev, "error: failed to pause stream %d\n",
1297 stream->reply.stream_hw_id);
1298
1299 return ret;
1300 }
1301
sst_hsw_stream_resume(struct sst_hsw * hsw,struct sst_hsw_stream * stream,int wait)1302 int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1303 int wait)
1304 {
1305 int ret;
1306
1307 if (!stream) {
1308 dev_warn(hsw->dev, "warning: stream is NULL, no stream to resume, ignore it.\n");
1309 return 0;
1310 }
1311
1312 trace_ipc_request("stream resume", stream->reply.stream_hw_id);
1313
1314 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
1315 stream->reply.stream_hw_id, wait);
1316 if (ret < 0)
1317 dev_err(hsw->dev, "error: failed to resume stream %d\n",
1318 stream->reply.stream_hw_id);
1319
1320 return ret;
1321 }
1322
sst_hsw_stream_reset(struct sst_hsw * hsw,struct sst_hsw_stream * stream)1323 int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1324 {
1325 int ret, tries = 10;
1326
1327 if (!stream) {
1328 dev_warn(hsw->dev, "warning: stream is NULL, no stream to reset, ignore it.\n");
1329 return 0;
1330 }
1331
1332 /* dont reset streams that are not commited */
1333 if (!stream->commited)
1334 return 0;
1335
1336 /* wait for pause to complete before we reset the stream */
1337 while (stream->running && --tries)
1338 msleep(1);
1339 if (!tries) {
1340 dev_err(hsw->dev, "error: reset stream %d still running\n",
1341 stream->reply.stream_hw_id);
1342 return -EINVAL;
1343 }
1344
1345 trace_ipc_request("stream reset", stream->reply.stream_hw_id);
1346
1347 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
1348 stream->reply.stream_hw_id, 1);
1349 if (ret < 0)
1350 dev_err(hsw->dev, "error: failed to reset stream %d\n",
1351 stream->reply.stream_hw_id);
1352 return ret;
1353 }
1354
1355 /* Stream pointer positions */
sst_hsw_get_dsp_position(struct sst_hsw * hsw,struct sst_hsw_stream * stream)1356 u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
1357 struct sst_hsw_stream *stream)
1358 {
1359 u32 rpos;
1360
1361 sst_dsp_read(hsw->dsp, &rpos,
1362 stream->reply.read_position_register_address, sizeof(rpos));
1363
1364 return rpos;
1365 }
1366
1367 /* Stream presentation (monotonic) positions */
sst_hsw_get_dsp_presentation_position(struct sst_hsw * hsw,struct sst_hsw_stream * stream)1368 u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
1369 struct sst_hsw_stream *stream)
1370 {
1371 u64 ppos;
1372
1373 sst_dsp_read(hsw->dsp, &ppos,
1374 stream->reply.presentation_position_register_address,
1375 sizeof(ppos));
1376
1377 return ppos;
1378 }
1379
1380 /* physical BE config */
sst_hsw_device_set_config(struct sst_hsw * hsw,enum sst_hsw_device_id dev,enum sst_hsw_device_mclk mclk,enum sst_hsw_device_mode mode,u32 clock_divider)1381 int sst_hsw_device_set_config(struct sst_hsw *hsw,
1382 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
1383 enum sst_hsw_device_mode mode, u32 clock_divider)
1384 {
1385 struct sst_ipc_message request;
1386 struct sst_hsw_ipc_device_config_req config;
1387 int ret;
1388
1389 trace_ipc_request("set device config", dev);
1390
1391 hsw->dx_dev = config.ssp_interface = dev;
1392 hsw->dx_mclk = config.clock_frequency = mclk;
1393 hsw->dx_mode = config.mode = mode;
1394 hsw->dx_clock_divider = config.clock_divider = clock_divider;
1395 if (mode == SST_HSW_DEVICE_TDM_CLOCK_MASTER)
1396 config.channels = 4;
1397 else
1398 config.channels = 2;
1399
1400 trace_hsw_device_config_req(&config);
1401
1402 request.header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
1403 request.data = &config;
1404 request.size = sizeof(config);
1405
1406 ret = sst_ipc_tx_message_wait(&hsw->ipc, request, NULL);
1407 if (ret < 0)
1408 dev_err(hsw->dev, "error: set device formats failed\n");
1409
1410 return ret;
1411 }
1412 EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
1413
1414 /* DX Config */
sst_hsw_dx_set_state(struct sst_hsw * hsw,enum sst_hsw_dx_state state,struct sst_hsw_ipc_dx_reply * dx)1415 int sst_hsw_dx_set_state(struct sst_hsw *hsw,
1416 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
1417 {
1418 struct sst_ipc_message request, reply = {0};
1419 u32 state_;
1420 int ret, item;
1421
1422 state_ = state;
1423 request.header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
1424 request.data = &state_;
1425 request.size = sizeof(state_);
1426 reply.data = dx;
1427 reply.size = sizeof(*dx);
1428
1429 trace_ipc_request("PM enter Dx state", state);
1430
1431 ret = sst_ipc_tx_message_wait(&hsw->ipc, request, &reply);
1432 if (ret < 0) {
1433 dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
1434 return ret;
1435 }
1436
1437 for (item = 0; item < dx->entries_no; item++) {
1438 dev_dbg(hsw->dev,
1439 "Item[%d] offset[%x] - size[%x] - source[%x]\n",
1440 item, dx->mem_info[item].offset,
1441 dx->mem_info[item].size,
1442 dx->mem_info[item].source);
1443 }
1444 dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
1445 dx->entries_no, state);
1446
1447 return ret;
1448 }
1449
sst_hsw_runtime_module_create(struct sst_hsw * hsw,int mod_id,int offset)1450 struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
1451 int mod_id, int offset)
1452 {
1453 struct sst_dsp *dsp = hsw->dsp;
1454 struct sst_module *module;
1455 struct sst_module_runtime *runtime;
1456 int err;
1457
1458 module = sst_module_get_from_id(dsp, mod_id);
1459 if (module == NULL) {
1460 dev_err(dsp->dev, "error: failed to get module %d for pcm\n",
1461 mod_id);
1462 return NULL;
1463 }
1464
1465 runtime = sst_module_runtime_new(module, mod_id, NULL);
1466 if (runtime == NULL) {
1467 dev_err(dsp->dev, "error: failed to create module %d runtime\n",
1468 mod_id);
1469 return NULL;
1470 }
1471
1472 err = sst_module_runtime_alloc_blocks(runtime, offset);
1473 if (err < 0) {
1474 dev_err(dsp->dev, "error: failed to alloc blocks for module %d runtime\n",
1475 mod_id);
1476 sst_module_runtime_free(runtime);
1477 return NULL;
1478 }
1479
1480 dev_dbg(dsp->dev, "runtime id %d created for module %d\n", runtime->id,
1481 mod_id);
1482 return runtime;
1483 }
1484
sst_hsw_runtime_module_free(struct sst_module_runtime * runtime)1485 void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime)
1486 {
1487 sst_module_runtime_free_blocks(runtime);
1488 sst_module_runtime_free(runtime);
1489 }
1490
1491 #ifdef CONFIG_PM
sst_hsw_dx_state_dump(struct sst_hsw * hsw)1492 static int sst_hsw_dx_state_dump(struct sst_hsw *hsw)
1493 {
1494 struct sst_dsp *sst = hsw->dsp;
1495 u32 item, offset, size;
1496 int ret = 0;
1497
1498 trace_ipc_request("PM state dump. Items #", SST_HSW_MAX_DX_REGIONS);
1499
1500 if (hsw->dx.entries_no > SST_HSW_MAX_DX_REGIONS) {
1501 dev_err(hsw->dev,
1502 "error: number of FW context regions greater than %d\n",
1503 SST_HSW_MAX_DX_REGIONS);
1504 memset(&hsw->dx, 0, sizeof(hsw->dx));
1505 return -EINVAL;
1506 }
1507
1508 ret = sst_dsp_dma_get_channel(sst, 0);
1509 if (ret < 0) {
1510 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1511 return ret;
1512 }
1513
1514 /* set on-demond mode on engine 0 channel 3 */
1515 sst_dsp_shim_update_bits(sst, SST_HMDC,
1516 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
1517 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
1518
1519 for (item = 0; item < hsw->dx.entries_no; item++) {
1520 if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1521 && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1522 && hsw->dx.mem_info[item].offset <
1523 DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1524
1525 offset = hsw->dx.mem_info[item].offset
1526 - DSP_DRAM_ADDR_OFFSET;
1527 size = (hsw->dx.mem_info[item].size + 3) & (~3);
1528
1529 ret = sst_dsp_dma_copyfrom(sst, hsw->dx_context_paddr + offset,
1530 sst->addr.lpe_base + offset, size);
1531 if (ret < 0) {
1532 dev_err(hsw->dev,
1533 "error: FW context dump failed\n");
1534 memset(&hsw->dx, 0, sizeof(hsw->dx));
1535 goto out;
1536 }
1537 }
1538 }
1539
1540 out:
1541 sst_dsp_dma_put_channel(sst);
1542 return ret;
1543 }
1544
sst_hsw_dx_state_restore(struct sst_hsw * hsw)1545 static int sst_hsw_dx_state_restore(struct sst_hsw *hsw)
1546 {
1547 struct sst_dsp *sst = hsw->dsp;
1548 u32 item, offset, size;
1549 int ret;
1550
1551 for (item = 0; item < hsw->dx.entries_no; item++) {
1552 if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1553 && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1554 && hsw->dx.mem_info[item].offset <
1555 DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1556
1557 offset = hsw->dx.mem_info[item].offset
1558 - DSP_DRAM_ADDR_OFFSET;
1559 size = (hsw->dx.mem_info[item].size + 3) & (~3);
1560
1561 ret = sst_dsp_dma_copyto(sst, sst->addr.lpe_base + offset,
1562 hsw->dx_context_paddr + offset, size);
1563 if (ret < 0) {
1564 dev_err(hsw->dev,
1565 "error: FW context restore failed\n");
1566 return ret;
1567 }
1568 }
1569 }
1570
1571 return 0;
1572 }
1573
sst_hsw_dsp_load(struct sst_hsw * hsw)1574 int sst_hsw_dsp_load(struct sst_hsw *hsw)
1575 {
1576 struct sst_dsp *dsp = hsw->dsp;
1577 struct sst_fw *sst_fw, *t;
1578 int ret;
1579
1580 dev_dbg(hsw->dev, "loading audio DSP....");
1581
1582 ret = sst_dsp_wake(dsp);
1583 if (ret < 0) {
1584 dev_err(hsw->dev, "error: failed to wake audio DSP\n");
1585 return -ENODEV;
1586 }
1587
1588 ret = sst_dsp_dma_get_channel(dsp, 0);
1589 if (ret < 0) {
1590 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1591 return ret;
1592 }
1593
1594 list_for_each_entry_safe_reverse(sst_fw, t, &dsp->fw_list, list) {
1595 ret = sst_fw_reload(sst_fw);
1596 if (ret < 0) {
1597 dev_err(hsw->dev, "error: SST FW reload failed\n");
1598 sst_dsp_dma_put_channel(dsp);
1599 return -ENOMEM;
1600 }
1601 }
1602 ret = sst_block_alloc_scratch(hsw->dsp);
1603 if (ret < 0)
1604 return -EINVAL;
1605
1606 sst_dsp_dma_put_channel(dsp);
1607 return 0;
1608 }
1609
sst_hsw_dsp_restore(struct sst_hsw * hsw)1610 static int sst_hsw_dsp_restore(struct sst_hsw *hsw)
1611 {
1612 struct sst_dsp *dsp = hsw->dsp;
1613 int ret;
1614
1615 dev_dbg(hsw->dev, "restoring audio DSP....");
1616
1617 ret = sst_dsp_dma_get_channel(dsp, 0);
1618 if (ret < 0) {
1619 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1620 return ret;
1621 }
1622
1623 ret = sst_hsw_dx_state_restore(hsw);
1624 if (ret < 0) {
1625 dev_err(hsw->dev, "error: SST FW context restore failed\n");
1626 sst_dsp_dma_put_channel(dsp);
1627 return -ENOMEM;
1628 }
1629 sst_dsp_dma_put_channel(dsp);
1630
1631 /* wait for DSP boot completion */
1632 sst_dsp_boot(dsp);
1633
1634 return ret;
1635 }
1636
sst_hsw_dsp_runtime_suspend(struct sst_hsw * hsw)1637 int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw)
1638 {
1639 int ret;
1640
1641 dev_dbg(hsw->dev, "audio dsp runtime suspend\n");
1642
1643 ret = sst_hsw_dx_set_state(hsw, SST_HSW_DX_STATE_D3, &hsw->dx);
1644 if (ret < 0)
1645 return ret;
1646
1647 sst_dsp_stall(hsw->dsp);
1648
1649 ret = sst_hsw_dx_state_dump(hsw);
1650 if (ret < 0)
1651 return ret;
1652
1653 sst_ipc_drop_all(&hsw->ipc);
1654
1655 return 0;
1656 }
1657
sst_hsw_dsp_runtime_sleep(struct sst_hsw * hsw)1658 int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw)
1659 {
1660 struct sst_fw *sst_fw, *t;
1661 struct sst_dsp *dsp = hsw->dsp;
1662
1663 list_for_each_entry_safe(sst_fw, t, &dsp->fw_list, list) {
1664 sst_fw_unload(sst_fw);
1665 }
1666 sst_block_free_scratch(dsp);
1667
1668 hsw->boot_complete = false;
1669
1670 sst_dsp_sleep(dsp);
1671
1672 return 0;
1673 }
1674
sst_hsw_dsp_runtime_resume(struct sst_hsw * hsw)1675 int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw)
1676 {
1677 struct device *dev = hsw->dev;
1678 int ret;
1679
1680 dev_dbg(dev, "audio dsp runtime resume\n");
1681
1682 if (hsw->boot_complete)
1683 return 1; /* tell caller no action is required */
1684
1685 ret = sst_hsw_dsp_restore(hsw);
1686 if (ret < 0)
1687 dev_err(dev, "error: audio DSP boot failure\n");
1688
1689 sst_hsw_init_module_state(hsw);
1690
1691 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
1692 msecs_to_jiffies(IPC_BOOT_MSECS));
1693 if (ret == 0) {
1694 dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
1695 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
1696 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
1697 return -EIO;
1698 }
1699
1700 /* Set ADSP SSP port settings - sadly the FW does not store SSP port
1701 settings as part of the PM context. */
1702 ret = sst_hsw_device_set_config(hsw, hsw->dx_dev, hsw->dx_mclk,
1703 hsw->dx_mode, hsw->dx_clock_divider);
1704 if (ret < 0)
1705 dev_err(dev, "error: SSP re-initialization failed\n");
1706
1707 return ret;
1708 }
1709 #endif
1710
sst_hsw_get_dsp(struct sst_hsw * hsw)1711 struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
1712 {
1713 return hsw->dsp;
1714 }
1715
sst_hsw_init_module_state(struct sst_hsw * hsw)1716 void sst_hsw_init_module_state(struct sst_hsw *hsw)
1717 {
1718 struct sst_module *module;
1719 enum sst_hsw_module_id id;
1720
1721 /* the base fw contains several modules */
1722 for (id = SST_HSW_MODULE_BASE_FW; id < SST_HSW_MAX_MODULE_ID; id++) {
1723 module = sst_module_get_from_id(hsw->dsp, id);
1724 if (module) {
1725 /* module waves is active only after being enabled */
1726 if (id == SST_HSW_MODULE_WAVES)
1727 module->state = SST_MODULE_STATE_INITIALIZED;
1728 else
1729 module->state = SST_MODULE_STATE_ACTIVE;
1730 }
1731 }
1732 }
1733
sst_hsw_is_module_loaded(struct sst_hsw * hsw,u32 module_id)1734 bool sst_hsw_is_module_loaded(struct sst_hsw *hsw, u32 module_id)
1735 {
1736 struct sst_module *module;
1737
1738 module = sst_module_get_from_id(hsw->dsp, module_id);
1739 if (module == NULL || module->state == SST_MODULE_STATE_UNLOADED)
1740 return false;
1741 else
1742 return true;
1743 }
1744
sst_hsw_is_module_active(struct sst_hsw * hsw,u32 module_id)1745 bool sst_hsw_is_module_active(struct sst_hsw *hsw, u32 module_id)
1746 {
1747 struct sst_module *module;
1748
1749 module = sst_module_get_from_id(hsw->dsp, module_id);
1750 if (module != NULL && module->state == SST_MODULE_STATE_ACTIVE)
1751 return true;
1752 else
1753 return false;
1754 }
1755
sst_hsw_set_module_enabled_rtd3(struct sst_hsw * hsw,u32 module_id)1756 void sst_hsw_set_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1757 {
1758 hsw->enabled_modules_rtd3 |= (1 << module_id);
1759 }
1760
sst_hsw_set_module_disabled_rtd3(struct sst_hsw * hsw,u32 module_id)1761 void sst_hsw_set_module_disabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1762 {
1763 hsw->enabled_modules_rtd3 &= ~(1 << module_id);
1764 }
1765
sst_hsw_is_module_enabled_rtd3(struct sst_hsw * hsw,u32 module_id)1766 bool sst_hsw_is_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1767 {
1768 return hsw->enabled_modules_rtd3 & (1 << module_id);
1769 }
1770
sst_hsw_reset_param_buf(struct sst_hsw * hsw)1771 void sst_hsw_reset_param_buf(struct sst_hsw *hsw)
1772 {
1773 hsw->param_idx_w = 0;
1774 hsw->param_idx_r = 0;
1775 memset((void *)hsw->param_buf, 0, sizeof(hsw->param_buf));
1776 }
1777
sst_hsw_store_param_line(struct sst_hsw * hsw,u8 * buf)1778 int sst_hsw_store_param_line(struct sst_hsw *hsw, u8 *buf)
1779 {
1780 /* save line to the first available position of param buffer */
1781 if (hsw->param_idx_w > WAVES_PARAM_LINES - 1) {
1782 dev_warn(hsw->dev, "warning: param buffer overflow!\n");
1783 return -EPERM;
1784 }
1785 memcpy(hsw->param_buf[hsw->param_idx_w], buf, WAVES_PARAM_COUNT);
1786 hsw->param_idx_w++;
1787 return 0;
1788 }
1789
sst_hsw_load_param_line(struct sst_hsw * hsw,u8 * buf)1790 int sst_hsw_load_param_line(struct sst_hsw *hsw, u8 *buf)
1791 {
1792 u8 id = 0;
1793
1794 /* read the first matching line from param buffer */
1795 while (hsw->param_idx_r < WAVES_PARAM_LINES) {
1796 id = hsw->param_buf[hsw->param_idx_r][0];
1797 hsw->param_idx_r++;
1798 if (buf[0] == id) {
1799 memcpy(buf, hsw->param_buf[hsw->param_idx_r],
1800 WAVES_PARAM_COUNT);
1801 break;
1802 }
1803 }
1804 if (hsw->param_idx_r > WAVES_PARAM_LINES - 1) {
1805 dev_dbg(hsw->dev, "end of buffer, roll to the beginning\n");
1806 hsw->param_idx_r = 0;
1807 return 0;
1808 }
1809 return 0;
1810 }
1811
sst_hsw_launch_param_buf(struct sst_hsw * hsw)1812 int sst_hsw_launch_param_buf(struct sst_hsw *hsw)
1813 {
1814 int ret, idx;
1815
1816 if (!sst_hsw_is_module_active(hsw, SST_HSW_MODULE_WAVES)) {
1817 dev_dbg(hsw->dev, "module waves is not active\n");
1818 return 0;
1819 }
1820
1821 /* put all param lines to DSP through ipc */
1822 for (idx = 0; idx < hsw->param_idx_w; idx++) {
1823 ret = sst_hsw_module_set_param(hsw,
1824 SST_HSW_MODULE_WAVES, 0, hsw->param_buf[idx][0],
1825 WAVES_PARAM_COUNT, hsw->param_buf[idx]);
1826 if (ret < 0)
1827 return ret;
1828 }
1829 return 0;
1830 }
1831
sst_hsw_module_load(struct sst_hsw * hsw,u32 module_id,u32 instance_id,char * name)1832 int sst_hsw_module_load(struct sst_hsw *hsw,
1833 u32 module_id, u32 instance_id, char *name)
1834 {
1835 int ret = 0;
1836 const struct firmware *fw = NULL;
1837 struct sst_fw *hsw_sst_fw;
1838 struct sst_module *module;
1839 struct device *dev = hsw->dev;
1840 struct sst_dsp *dsp = hsw->dsp;
1841
1842 dev_dbg(dev, "sst_hsw_module_load id=%d, name='%s'", module_id, name);
1843
1844 module = sst_module_get_from_id(dsp, module_id);
1845 if (module == NULL) {
1846 /* loading for the first time */
1847 if (module_id == SST_HSW_MODULE_BASE_FW) {
1848 /* for base module: use fw requested in acpi probe */
1849 fw = dsp->pdata->fw;
1850 if (!fw) {
1851 dev_err(dev, "request Base fw failed\n");
1852 return -ENODEV;
1853 }
1854 } else {
1855 /* try and load any other optional modules if they are
1856 * available. Use dev_info instead of dev_err in case
1857 * request firmware failed */
1858 ret = request_firmware(&fw, name, dev);
1859 if (ret) {
1860 dev_info(dev, "fw image %s not available(%d)\n",
1861 name, ret);
1862 return ret;
1863 }
1864 }
1865 hsw_sst_fw = sst_fw_new(dsp, fw, hsw);
1866 if (hsw_sst_fw == NULL) {
1867 dev_err(dev, "error: failed to load firmware\n");
1868 ret = -ENOMEM;
1869 goto out;
1870 }
1871 module = sst_module_get_from_id(dsp, module_id);
1872 if (module == NULL) {
1873 dev_err(dev, "error: no module %d in firmware %s\n",
1874 module_id, name);
1875 }
1876 } else
1877 dev_info(dev, "module %d (%s) already loaded\n",
1878 module_id, name);
1879 out:
1880 /* release fw, but base fw should be released by acpi driver */
1881 if (fw && module_id != SST_HSW_MODULE_BASE_FW)
1882 release_firmware(fw);
1883
1884 return ret;
1885 }
1886
sst_hsw_module_enable(struct sst_hsw * hsw,u32 module_id,u32 instance_id)1887 int sst_hsw_module_enable(struct sst_hsw *hsw,
1888 u32 module_id, u32 instance_id)
1889 {
1890 int ret;
1891 struct sst_ipc_message request;
1892 struct sst_hsw_ipc_module_config config;
1893 struct sst_module *module;
1894 struct sst_module_runtime *runtime;
1895 struct device *dev = hsw->dev;
1896 struct sst_dsp *dsp = hsw->dsp;
1897
1898 if (!sst_hsw_is_module_loaded(hsw, module_id)) {
1899 dev_dbg(dev, "module %d not loaded\n", module_id);
1900 return 0;
1901 }
1902
1903 if (sst_hsw_is_module_active(hsw, module_id)) {
1904 dev_info(dev, "module %d already enabled\n", module_id);
1905 return 0;
1906 }
1907
1908 module = sst_module_get_from_id(dsp, module_id);
1909 if (module == NULL) {
1910 dev_err(dev, "module %d not valid\n", module_id);
1911 return -ENXIO;
1912 }
1913
1914 runtime = sst_module_runtime_get_from_id(module, module_id);
1915 if (runtime == NULL) {
1916 dev_err(dev, "runtime %d not valid", module_id);
1917 return -ENXIO;
1918 }
1919
1920 request.header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1921 IPC_MODULE_OPERATION(IPC_MODULE_ENABLE) |
1922 IPC_MODULE_ID(module_id);
1923 dev_dbg(dev, "module enable header: %x\n", (u32)request.header);
1924
1925 config.map.module_entries_count = 1;
1926 config.map.module_entries[0].module_id = module->id;
1927 config.map.module_entries[0].entry_point = module->entry;
1928
1929 config.persistent_mem.offset =
1930 sst_dsp_get_offset(dsp,
1931 runtime->persistent_offset, SST_MEM_DRAM);
1932 config.persistent_mem.size = module->persistent_size;
1933
1934 config.scratch_mem.offset =
1935 sst_dsp_get_offset(dsp,
1936 dsp->scratch_offset, SST_MEM_DRAM);
1937 config.scratch_mem.size = module->scratch_size;
1938 dev_dbg(dev, "mod %d enable p:%d @ %x, s:%d @ %x, ep: %x",
1939 config.map.module_entries[0].module_id,
1940 config.persistent_mem.size,
1941 config.persistent_mem.offset,
1942 config.scratch_mem.size, config.scratch_mem.offset,
1943 config.map.module_entries[0].entry_point);
1944
1945 request.data = &config;
1946 request.size = sizeof(config);
1947 ret = sst_ipc_tx_message_wait(&hsw->ipc, request, NULL);
1948 if (ret < 0)
1949 dev_err(dev, "ipc: module enable failed - %d\n", ret);
1950 else
1951 module->state = SST_MODULE_STATE_ACTIVE;
1952
1953 return ret;
1954 }
1955
sst_hsw_module_disable(struct sst_hsw * hsw,u32 module_id,u32 instance_id)1956 int sst_hsw_module_disable(struct sst_hsw *hsw,
1957 u32 module_id, u32 instance_id)
1958 {
1959 int ret;
1960 struct sst_ipc_message request = {0};
1961 struct sst_module *module;
1962 struct device *dev = hsw->dev;
1963 struct sst_dsp *dsp = hsw->dsp;
1964
1965 if (!sst_hsw_is_module_loaded(hsw, module_id)) {
1966 dev_dbg(dev, "module %d not loaded\n", module_id);
1967 return 0;
1968 }
1969
1970 if (!sst_hsw_is_module_active(hsw, module_id)) {
1971 dev_info(dev, "module %d already disabled\n", module_id);
1972 return 0;
1973 }
1974
1975 module = sst_module_get_from_id(dsp, module_id);
1976 if (module == NULL) {
1977 dev_err(dev, "module %d not valid\n", module_id);
1978 return -ENXIO;
1979 }
1980
1981 request.header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1982 IPC_MODULE_OPERATION(IPC_MODULE_DISABLE) |
1983 IPC_MODULE_ID(module_id);
1984
1985 ret = sst_ipc_tx_message_wait(&hsw->ipc, request, NULL);
1986 if (ret < 0)
1987 dev_err(dev, "module disable failed - %d\n", ret);
1988 else
1989 module->state = SST_MODULE_STATE_INITIALIZED;
1990
1991 return ret;
1992 }
1993
sst_hsw_module_set_param(struct sst_hsw * hsw,u32 module_id,u32 instance_id,u32 parameter_id,u32 param_size,char * param)1994 int sst_hsw_module_set_param(struct sst_hsw *hsw,
1995 u32 module_id, u32 instance_id, u32 parameter_id,
1996 u32 param_size, char *param)
1997 {
1998 int ret;
1999 struct sst_ipc_message request = {0};
2000 u32 payload_size = 0;
2001 struct sst_hsw_transfer_parameter *parameter;
2002 struct device *dev = hsw->dev;
2003
2004 request.header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
2005 IPC_MODULE_OPERATION(IPC_MODULE_SET_PARAMETER) |
2006 IPC_MODULE_ID(module_id);
2007 dev_dbg(dev, "sst_hsw_module_set_param header=%x\n",
2008 (u32)request.header);
2009
2010 payload_size = param_size +
2011 sizeof(struct sst_hsw_transfer_parameter) -
2012 sizeof(struct sst_hsw_transfer_list);
2013 dev_dbg(dev, "parameter size : %d\n", param_size);
2014 dev_dbg(dev, "payload size : %d\n", payload_size);
2015
2016 if (payload_size <= SST_HSW_IPC_MAX_SHORT_PARAMETER_SIZE) {
2017 /* short parameter, mailbox can contain data */
2018 dev_dbg(dev, "transfer parameter size : %zu\n",
2019 request.size);
2020
2021 request.size = ALIGN(payload_size, 4);
2022 dev_dbg(dev, "transfer parameter aligned size : %zu\n",
2023 request.size);
2024
2025 parameter = kzalloc(request.size, GFP_KERNEL);
2026 if (parameter == NULL)
2027 return -ENOMEM;
2028
2029 memcpy(parameter->data, param, param_size);
2030 } else {
2031 dev_warn(dev, "transfer parameter size too large!");
2032 return 0;
2033 }
2034
2035 parameter->parameter_id = parameter_id;
2036 parameter->data_size = param_size;
2037 request.data = parameter;
2038
2039 ret = sst_ipc_tx_message_wait(&hsw->ipc, request, NULL);
2040 if (ret < 0)
2041 dev_err(dev, "ipc: module set parameter failed - %d\n", ret);
2042
2043 kfree(parameter);
2044
2045 return ret;
2046 }
2047
2048 static struct sst_dsp_device hsw_dev = {
2049 .thread = hsw_irq_thread,
2050 .ops = &haswell_ops,
2051 };
2052
hsw_tx_msg(struct sst_generic_ipc * ipc,struct ipc_message * msg)2053 static void hsw_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
2054 {
2055 /* send the message */
2056 sst_dsp_outbox_write(ipc->dsp, msg->tx.data, msg->tx.size);
2057 sst_dsp_ipc_msg_tx(ipc->dsp, msg->tx.header);
2058 }
2059
hsw_shim_dbg(struct sst_generic_ipc * ipc,const char * text)2060 static void hsw_shim_dbg(struct sst_generic_ipc *ipc, const char *text)
2061 {
2062 struct sst_dsp *sst = ipc->dsp;
2063 u32 isr, ipcd, imrx, ipcx;
2064
2065 ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
2066 isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
2067 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
2068 imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
2069
2070 dev_err(ipc->dev,
2071 "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
2072 text, ipcx, isr, ipcd, imrx);
2073 }
2074
hsw_tx_data_copy(struct ipc_message * msg,char * tx_data,size_t tx_size)2075 static void hsw_tx_data_copy(struct ipc_message *msg, char *tx_data,
2076 size_t tx_size)
2077 {
2078 memcpy(msg->tx.data, tx_data, tx_size);
2079 }
2080
hsw_reply_msg_match(u64 header,u64 * mask)2081 static u64 hsw_reply_msg_match(u64 header, u64 *mask)
2082 {
2083 /* clear reply bits & status bits */
2084 header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
2085 *mask = (u64)-1;
2086
2087 return header;
2088 }
2089
hsw_is_dsp_busy(struct sst_dsp * dsp)2090 static bool hsw_is_dsp_busy(struct sst_dsp *dsp)
2091 {
2092 u64 ipcx;
2093
2094 ipcx = sst_dsp_shim_read_unlocked(dsp, SST_IPCX);
2095 return (ipcx & (SST_IPCX_BUSY | SST_IPCX_DONE));
2096 }
2097
sst_hsw_dsp_init(struct device * dev,struct sst_pdata * pdata)2098 int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
2099 {
2100 struct sst_hsw_ipc_fw_version version;
2101 struct sst_hsw *hsw;
2102 struct sst_generic_ipc *ipc;
2103 int ret;
2104
2105 dev_dbg(dev, "initialising Audio DSP IPC\n");
2106
2107 hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
2108 if (hsw == NULL)
2109 return -ENOMEM;
2110
2111 hsw->dev = dev;
2112
2113 ipc = &hsw->ipc;
2114 ipc->dev = dev;
2115 ipc->ops.tx_msg = hsw_tx_msg;
2116 ipc->ops.shim_dbg = hsw_shim_dbg;
2117 ipc->ops.tx_data_copy = hsw_tx_data_copy;
2118 ipc->ops.reply_msg_match = hsw_reply_msg_match;
2119 ipc->ops.is_dsp_busy = hsw_is_dsp_busy;
2120
2121 ipc->tx_data_max_size = IPC_MAX_MAILBOX_BYTES;
2122 ipc->rx_data_max_size = IPC_MAX_MAILBOX_BYTES;
2123
2124 ret = sst_ipc_init(ipc);
2125 if (ret != 0)
2126 goto ipc_init_err;
2127
2128 INIT_LIST_HEAD(&hsw->stream_list);
2129 init_waitqueue_head(&hsw->boot_wait);
2130 hsw_dev.thread_context = hsw;
2131
2132 /* init SST shim */
2133 hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
2134 if (hsw->dsp == NULL) {
2135 ret = -ENODEV;
2136 goto dsp_new_err;
2137 }
2138
2139 ipc->dsp = hsw->dsp;
2140
2141 /* allocate DMA buffer for context storage */
2142 hsw->dx_context = dma_alloc_coherent(hsw->dsp->dma_dev,
2143 SST_HSW_DX_CONTEXT_SIZE, &hsw->dx_context_paddr, GFP_KERNEL);
2144 if (hsw->dx_context == NULL) {
2145 ret = -ENOMEM;
2146 goto dma_err;
2147 }
2148
2149 /* keep the DSP in reset state for base FW loading */
2150 sst_dsp_reset(hsw->dsp);
2151
2152 /* load base module and other modules in base firmware image */
2153 ret = sst_hsw_module_load(hsw, SST_HSW_MODULE_BASE_FW, 0, "Base");
2154 if (ret < 0)
2155 goto fw_err;
2156
2157 /* try to load module waves */
2158 sst_hsw_module_load(hsw, SST_HSW_MODULE_WAVES, 0, "intel/IntcPP01.bin");
2159
2160 /* allocate scratch mem regions */
2161 ret = sst_block_alloc_scratch(hsw->dsp);
2162 if (ret < 0)
2163 goto boot_err;
2164
2165 /* init param buffer */
2166 sst_hsw_reset_param_buf(hsw);
2167
2168 /* wait for DSP boot completion */
2169 sst_dsp_boot(hsw->dsp);
2170 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
2171 msecs_to_jiffies(IPC_BOOT_MSECS));
2172 if (ret == 0) {
2173 ret = -EIO;
2174 dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
2175 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
2176 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
2177 goto boot_err;
2178 }
2179
2180 /* init module state after boot */
2181 sst_hsw_init_module_state(hsw);
2182
2183 /* get the FW version */
2184 sst_hsw_fw_get_version(hsw, &version);
2185
2186 /* get the globalmixer */
2187 ret = sst_hsw_mixer_get_info(hsw);
2188 if (ret < 0) {
2189 dev_err(hsw->dev, "error: failed to get stream info\n");
2190 goto boot_err;
2191 }
2192
2193 pdata->dsp = hsw;
2194 return 0;
2195
2196 boot_err:
2197 sst_dsp_reset(hsw->dsp);
2198 sst_fw_free_all(hsw->dsp);
2199 fw_err:
2200 dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2201 hsw->dx_context, hsw->dx_context_paddr);
2202 dma_err:
2203 sst_dsp_free(hsw->dsp);
2204 dsp_new_err:
2205 sst_ipc_fini(ipc);
2206 ipc_init_err:
2207 return ret;
2208 }
2209 EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
2210
sst_hsw_dsp_free(struct device * dev,struct sst_pdata * pdata)2211 void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
2212 {
2213 struct sst_hsw *hsw = pdata->dsp;
2214
2215 sst_dsp_reset(hsw->dsp);
2216 sst_fw_free_all(hsw->dsp);
2217 dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2218 hsw->dx_context, hsw->dx_context_paddr);
2219 sst_dsp_free(hsw->dsp);
2220 sst_ipc_fini(&hsw->ipc);
2221 }
2222 EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);
2223