1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * cnl-sst.c - DSP library functions for CNL platform
4 *
5 * Copyright (C) 2016-17, Intel Corporation.
6 *
7 * Author: Guneshwor Singh <guneshwor.o.singh@intel.com>
8 *
9 * Modified from:
10 * HDA DSP library functions for SKL platform
11 * Copyright (C) 2014-15, Intel Corporation.
12 *
13 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
14 *
15 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
16 */
17
18 #include <linux/module.h>
19 #include <linux/delay.h>
20 #include <linux/firmware.h>
21 #include <linux/device.h>
22
23 #include "../common/sst-dsp.h"
24 #include "../common/sst-dsp-priv.h"
25 #include "../common/sst-ipc.h"
26 #include "cnl-sst-dsp.h"
27 #include "skl.h"
28
29 #define CNL_FW_ROM_INIT 0x1
30 #define CNL_FW_INIT 0x5
31 #define CNL_IPC_PURGE 0x01004000
32 #define CNL_INIT_TIMEOUT 300
33 #define CNL_BASEFW_TIMEOUT 3000
34
35 #define CNL_ADSP_SRAM0_BASE 0x80000
36
37 /* Firmware status window */
38 #define CNL_ADSP_FW_STATUS CNL_ADSP_SRAM0_BASE
39 #define CNL_ADSP_ERROR_CODE (CNL_ADSP_FW_STATUS + 0x4)
40
41 #define CNL_INSTANCE_ID 0
42 #define CNL_BASE_FW_MODULE_ID 0
43 #define CNL_ADSP_FW_HDR_OFFSET 0x2000
44 #define CNL_ROM_CTRL_DMA_ID 0x9
45
cnl_prepare_fw(struct sst_dsp * ctx,const void * fwdata,u32 fwsize)46 static int cnl_prepare_fw(struct sst_dsp *ctx, const void *fwdata, u32 fwsize)
47 {
48
49 int ret, stream_tag;
50
51 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
52 if (stream_tag <= 0) {
53 dev_err(ctx->dev, "dma prepare failed: 0%#x\n", stream_tag);
54 return stream_tag;
55 }
56
57 ctx->dsp_ops.stream_tag = stream_tag;
58 memcpy(ctx->dmab.area, fwdata, fwsize);
59
60 ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK);
61 if (ret < 0) {
62 dev_err(ctx->dev, "dsp core0 power up failed\n");
63 ret = -EIO;
64 goto base_fw_load_failed;
65 }
66
67 /* purge FW request */
68 sst_dsp_shim_write(ctx, CNL_ADSP_REG_HIPCIDR,
69 CNL_ADSP_REG_HIPCIDR_BUSY | (CNL_IPC_PURGE |
70 ((stream_tag - 1) << CNL_ROM_CTRL_DMA_ID)));
71
72 ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
73 if (ret < 0) {
74 dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
75 ret = -EIO;
76 goto base_fw_load_failed;
77 }
78
79 ret = sst_dsp_register_poll(ctx, CNL_ADSP_REG_HIPCIDA,
80 CNL_ADSP_REG_HIPCIDA_DONE,
81 CNL_ADSP_REG_HIPCIDA_DONE,
82 BXT_INIT_TIMEOUT, "HIPCIDA Done");
83 if (ret < 0) {
84 dev_err(ctx->dev, "timeout for purge request: %d\n", ret);
85 goto base_fw_load_failed;
86 }
87
88 /* enable interrupt */
89 cnl_ipc_int_enable(ctx);
90 cnl_ipc_op_int_enable(ctx);
91
92 ret = sst_dsp_register_poll(ctx, CNL_ADSP_FW_STATUS, CNL_FW_STS_MASK,
93 CNL_FW_ROM_INIT, CNL_INIT_TIMEOUT,
94 "rom load");
95 if (ret < 0) {
96 dev_err(ctx->dev, "rom init timeout, ret: %d\n", ret);
97 goto base_fw_load_failed;
98 }
99
100 return 0;
101
102 base_fw_load_failed:
103 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
104 cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
105
106 return ret;
107 }
108
sst_transfer_fw_host_dma(struct sst_dsp * ctx)109 static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
110 {
111 int ret;
112
113 ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
114 ret = sst_dsp_register_poll(ctx, CNL_ADSP_FW_STATUS, CNL_FW_STS_MASK,
115 CNL_FW_INIT, CNL_BASEFW_TIMEOUT,
116 "firmware boot");
117
118 ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
119 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
120
121 return ret;
122 }
123
cnl_load_base_firmware(struct sst_dsp * ctx)124 static int cnl_load_base_firmware(struct sst_dsp *ctx)
125 {
126 struct firmware stripped_fw;
127 struct skl_dev *cnl = ctx->thread_context;
128 int ret, i;
129
130 if (!ctx->fw) {
131 ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
132 if (ret < 0) {
133 dev_err(ctx->dev, "request firmware failed: %d\n", ret);
134 goto cnl_load_base_firmware_failed;
135 }
136 }
137
138 /* parse uuids if first boot */
139 if (cnl->is_first_boot) {
140 ret = snd_skl_parse_uuids(ctx, ctx->fw,
141 CNL_ADSP_FW_HDR_OFFSET, 0);
142 if (ret < 0)
143 goto cnl_load_base_firmware_failed;
144 }
145
146 stripped_fw.data = ctx->fw->data;
147 stripped_fw.size = ctx->fw->size;
148 skl_dsp_strip_extended_manifest(&stripped_fw);
149
150 for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) {
151 ret = cnl_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
152 if (!ret)
153 break;
154 dev_dbg(ctx->dev, "prepare firmware failed: %d\n", ret);
155 }
156
157 if (ret < 0)
158 goto cnl_load_base_firmware_failed;
159
160 ret = sst_transfer_fw_host_dma(ctx);
161 if (ret < 0) {
162 dev_err(ctx->dev, "transfer firmware failed: %d\n", ret);
163 cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
164 goto cnl_load_base_firmware_failed;
165 }
166
167 ret = wait_event_timeout(cnl->boot_wait, cnl->boot_complete,
168 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
169 if (ret == 0) {
170 dev_err(ctx->dev, "FW ready timed-out\n");
171 cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
172 ret = -EIO;
173 goto cnl_load_base_firmware_failed;
174 }
175
176 cnl->fw_loaded = true;
177
178 return 0;
179
180 cnl_load_base_firmware_failed:
181 dev_err(ctx->dev, "firmware load failed: %d\n", ret);
182 release_firmware(ctx->fw);
183 ctx->fw = NULL;
184
185 return ret;
186 }
187
cnl_set_dsp_D0(struct sst_dsp * ctx,unsigned int core_id)188 static int cnl_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
189 {
190 struct skl_dev *cnl = ctx->thread_context;
191 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
192 struct skl_ipc_dxstate_info dx;
193 int ret;
194
195 if (!cnl->fw_loaded) {
196 cnl->boot_complete = false;
197 ret = cnl_load_base_firmware(ctx);
198 if (ret < 0) {
199 dev_err(ctx->dev, "fw reload failed: %d\n", ret);
200 return ret;
201 }
202
203 cnl->cores.state[core_id] = SKL_DSP_RUNNING;
204 return ret;
205 }
206
207 ret = cnl_dsp_enable_core(ctx, core_mask);
208 if (ret < 0) {
209 dev_err(ctx->dev, "enable dsp core %d failed: %d\n",
210 core_id, ret);
211 goto err;
212 }
213
214 if (core_id == SKL_DSP_CORE0_ID) {
215 /* enable interrupt */
216 cnl_ipc_int_enable(ctx);
217 cnl_ipc_op_int_enable(ctx);
218 cnl->boot_complete = false;
219
220 ret = wait_event_timeout(cnl->boot_wait, cnl->boot_complete,
221 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
222 if (ret == 0) {
223 dev_err(ctx->dev,
224 "dsp boot timeout, status=%#x error=%#x\n",
225 sst_dsp_shim_read(ctx, CNL_ADSP_FW_STATUS),
226 sst_dsp_shim_read(ctx, CNL_ADSP_ERROR_CODE));
227 ret = -ETIMEDOUT;
228 goto err;
229 }
230 } else {
231 dx.core_mask = core_mask;
232 dx.dx_mask = core_mask;
233
234 ret = skl_ipc_set_dx(&cnl->ipc, CNL_INSTANCE_ID,
235 CNL_BASE_FW_MODULE_ID, &dx);
236 if (ret < 0) {
237 dev_err(ctx->dev, "set_dx failed, core: %d ret: %d\n",
238 core_id, ret);
239 goto err;
240 }
241 }
242 cnl->cores.state[core_id] = SKL_DSP_RUNNING;
243
244 return 0;
245 err:
246 cnl_dsp_disable_core(ctx, core_mask);
247
248 return ret;
249 }
250
cnl_set_dsp_D3(struct sst_dsp * ctx,unsigned int core_id)251 static int cnl_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
252 {
253 struct skl_dev *cnl = ctx->thread_context;
254 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
255 struct skl_ipc_dxstate_info dx;
256 int ret;
257
258 dx.core_mask = core_mask;
259 dx.dx_mask = SKL_IPC_D3_MASK;
260
261 ret = skl_ipc_set_dx(&cnl->ipc, CNL_INSTANCE_ID,
262 CNL_BASE_FW_MODULE_ID, &dx);
263 if (ret < 0) {
264 dev_err(ctx->dev,
265 "dsp core %d to d3 failed; continue reset\n",
266 core_id);
267 cnl->fw_loaded = false;
268 }
269
270 /* disable interrupts if core 0 */
271 if (core_id == SKL_DSP_CORE0_ID) {
272 skl_ipc_op_int_disable(ctx);
273 skl_ipc_int_disable(ctx);
274 }
275
276 ret = cnl_dsp_disable_core(ctx, core_mask);
277 if (ret < 0) {
278 dev_err(ctx->dev, "disable dsp core %d failed: %d\n",
279 core_id, ret);
280 return ret;
281 }
282
283 cnl->cores.state[core_id] = SKL_DSP_RESET;
284
285 return ret;
286 }
287
cnl_get_errno(struct sst_dsp * ctx)288 static unsigned int cnl_get_errno(struct sst_dsp *ctx)
289 {
290 return sst_dsp_shim_read(ctx, CNL_ADSP_ERROR_CODE);
291 }
292
293 static const struct skl_dsp_fw_ops cnl_fw_ops = {
294 .set_state_D0 = cnl_set_dsp_D0,
295 .set_state_D3 = cnl_set_dsp_D3,
296 .load_fw = cnl_load_base_firmware,
297 .get_fw_errcode = cnl_get_errno,
298 };
299
300 static struct sst_ops cnl_ops = {
301 .irq_handler = cnl_dsp_sst_interrupt,
302 .write = sst_shim32_write,
303 .read = sst_shim32_read,
304 .ram_read = sst_memcpy_fromio_32,
305 .ram_write = sst_memcpy_toio_32,
306 .free = cnl_dsp_free,
307 };
308
309 #define CNL_IPC_GLB_NOTIFY_RSP_SHIFT 29
310 #define CNL_IPC_GLB_NOTIFY_RSP_MASK 0x1
311 #define CNL_IPC_GLB_NOTIFY_RSP_TYPE(x) (((x) >> CNL_IPC_GLB_NOTIFY_RSP_SHIFT) \
312 & CNL_IPC_GLB_NOTIFY_RSP_MASK)
313
cnl_dsp_irq_thread_handler(int irq,void * context)314 static irqreturn_t cnl_dsp_irq_thread_handler(int irq, void *context)
315 {
316 struct sst_dsp *dsp = context;
317 struct skl_dev *cnl = sst_dsp_get_thread_context(dsp);
318 struct sst_generic_ipc *ipc = &cnl->ipc;
319 struct skl_ipc_header header = {0};
320 u32 hipcida, hipctdr, hipctdd;
321 int ipc_irq = 0;
322
323 /* here we handle ipc interrupts only */
324 if (!(dsp->intr_status & CNL_ADSPIS_IPC))
325 return IRQ_NONE;
326
327 hipcida = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCIDA);
328 hipctdr = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCTDR);
329 hipctdd = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCTDD);
330
331 /* reply message from dsp */
332 if (hipcida & CNL_ADSP_REG_HIPCIDA_DONE) {
333 sst_dsp_shim_update_bits(dsp, CNL_ADSP_REG_HIPCCTL,
334 CNL_ADSP_REG_HIPCCTL_DONE, 0);
335
336 /* clear done bit - tell dsp operation is complete */
337 sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCIDA,
338 CNL_ADSP_REG_HIPCIDA_DONE, CNL_ADSP_REG_HIPCIDA_DONE);
339
340 ipc_irq = 1;
341
342 /* unmask done interrupt */
343 sst_dsp_shim_update_bits(dsp, CNL_ADSP_REG_HIPCCTL,
344 CNL_ADSP_REG_HIPCCTL_DONE, CNL_ADSP_REG_HIPCCTL_DONE);
345 }
346
347 /* new message from dsp */
348 if (hipctdr & CNL_ADSP_REG_HIPCTDR_BUSY) {
349 header.primary = hipctdr;
350 header.extension = hipctdd;
351 dev_dbg(dsp->dev, "IPC irq: Firmware respond primary:%x",
352 header.primary);
353 dev_dbg(dsp->dev, "IPC irq: Firmware respond extension:%x",
354 header.extension);
355
356 if (CNL_IPC_GLB_NOTIFY_RSP_TYPE(header.primary)) {
357 /* Handle Immediate reply from DSP Core */
358 skl_ipc_process_reply(ipc, header);
359 } else {
360 dev_dbg(dsp->dev, "IPC irq: Notification from firmware\n");
361 skl_ipc_process_notification(ipc, header);
362 }
363 /* clear busy interrupt */
364 sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCTDR,
365 CNL_ADSP_REG_HIPCTDR_BUSY, CNL_ADSP_REG_HIPCTDR_BUSY);
366
367 /* set done bit to ack dsp */
368 sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCTDA,
369 CNL_ADSP_REG_HIPCTDA_DONE, CNL_ADSP_REG_HIPCTDA_DONE);
370 ipc_irq = 1;
371 }
372
373 if (ipc_irq == 0)
374 return IRQ_NONE;
375
376 cnl_ipc_int_enable(dsp);
377
378 /* continue to send any remaining messages */
379 schedule_work(&ipc->kwork);
380
381 return IRQ_HANDLED;
382 }
383
384 static struct sst_dsp_device cnl_dev = {
385 .thread = cnl_dsp_irq_thread_handler,
386 .ops = &cnl_ops,
387 };
388
cnl_ipc_tx_msg(struct sst_generic_ipc * ipc,struct ipc_message * msg)389 static void cnl_ipc_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
390 {
391 struct skl_ipc_header *header = (struct skl_ipc_header *)(&msg->tx.header);
392
393 if (msg->tx.size)
394 sst_dsp_outbox_write(ipc->dsp, msg->tx.data, msg->tx.size);
395 sst_dsp_shim_write_unlocked(ipc->dsp, CNL_ADSP_REG_HIPCIDD,
396 header->extension);
397 sst_dsp_shim_write_unlocked(ipc->dsp, CNL_ADSP_REG_HIPCIDR,
398 header->primary | CNL_ADSP_REG_HIPCIDR_BUSY);
399 }
400
cnl_ipc_is_dsp_busy(struct sst_dsp * dsp)401 static bool cnl_ipc_is_dsp_busy(struct sst_dsp *dsp)
402 {
403 u32 hipcidr;
404
405 hipcidr = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCIDR);
406
407 return (hipcidr & CNL_ADSP_REG_HIPCIDR_BUSY);
408 }
409
cnl_ipc_init(struct device * dev,struct skl_dev * cnl)410 static int cnl_ipc_init(struct device *dev, struct skl_dev *cnl)
411 {
412 struct sst_generic_ipc *ipc;
413 int err;
414
415 ipc = &cnl->ipc;
416 ipc->dsp = cnl->dsp;
417 ipc->dev = dev;
418
419 ipc->tx_data_max_size = CNL_ADSP_W1_SZ;
420 ipc->rx_data_max_size = CNL_ADSP_W0_UP_SZ;
421
422 err = sst_ipc_init(ipc);
423 if (err)
424 return err;
425
426 /*
427 * overriding tx_msg and is_dsp_busy since
428 * ipc registers are different for cnl
429 */
430 ipc->ops.tx_msg = cnl_ipc_tx_msg;
431 ipc->ops.tx_data_copy = skl_ipc_tx_data_copy;
432 ipc->ops.is_dsp_busy = cnl_ipc_is_dsp_busy;
433
434 return 0;
435 }
436
cnl_sst_dsp_init(struct device * dev,void __iomem * mmio_base,int irq,const char * fw_name,struct skl_dsp_loader_ops dsp_ops,struct skl_dev ** dsp)437 int cnl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
438 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
439 struct skl_dev **dsp)
440 {
441 struct skl_dev *cnl;
442 struct sst_dsp *sst;
443 int ret;
444
445 ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &cnl_dev);
446 if (ret < 0) {
447 dev_err(dev, "%s: no device\n", __func__);
448 return ret;
449 }
450
451 cnl = *dsp;
452 sst = cnl->dsp;
453 sst->fw_ops = cnl_fw_ops;
454 sst->addr.lpe = mmio_base;
455 sst->addr.shim = mmio_base;
456 sst->addr.sram0_base = CNL_ADSP_SRAM0_BASE;
457 sst->addr.sram1_base = CNL_ADSP_SRAM1_BASE;
458 sst->addr.w0_stat_sz = CNL_ADSP_W0_STAT_SZ;
459 sst->addr.w0_up_sz = CNL_ADSP_W0_UP_SZ;
460
461 sst_dsp_mailbox_init(sst, (CNL_ADSP_SRAM0_BASE + CNL_ADSP_W0_STAT_SZ),
462 CNL_ADSP_W0_UP_SZ, CNL_ADSP_SRAM1_BASE,
463 CNL_ADSP_W1_SZ);
464
465 ret = cnl_ipc_init(dev, cnl);
466 if (ret) {
467 skl_dsp_free(sst);
468 return ret;
469 }
470
471 cnl->boot_complete = false;
472 init_waitqueue_head(&cnl->boot_wait);
473
474 return skl_dsp_acquire_irq(sst);
475 }
476 EXPORT_SYMBOL_GPL(cnl_sst_dsp_init);
477
cnl_sst_init_fw(struct device * dev,struct skl_dev * skl)478 int cnl_sst_init_fw(struct device *dev, struct skl_dev *skl)
479 {
480 int ret;
481 struct sst_dsp *sst = skl->dsp;
482
483 ret = skl->dsp->fw_ops.load_fw(sst);
484 if (ret < 0) {
485 dev_err(dev, "load base fw failed: %d", ret);
486 return ret;
487 }
488
489 skl_dsp_init_core_state(sst);
490
491 skl->is_first_boot = false;
492
493 return 0;
494 }
495 EXPORT_SYMBOL_GPL(cnl_sst_init_fw);
496
cnl_sst_dsp_cleanup(struct device * dev,struct skl_dev * skl)497 void cnl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl)
498 {
499 if (skl->dsp->fw)
500 release_firmware(skl->dsp->fw);
501
502 skl_freeup_uuid_list(skl);
503 cnl_ipc_free(&skl->ipc);
504
505 skl->dsp->ops->free(skl->dsp);
506 }
507 EXPORT_SYMBOL_GPL(cnl_sst_dsp_cleanup);
508
509 MODULE_LICENSE("GPL v2");
510 MODULE_DESCRIPTION("Intel Cannonlake IPC driver");
511