1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
4 *
5 * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
6 */
7
8 #include <linux/clk.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <sound/pcm.h>
15 #include <sound/pcm_params.h>
16 #include <linux/regmap.h>
17 #include <sound/soc.h>
18 #include <sound/soc-dai.h>
19 #include "lpass-lpaif-reg.h"
20 #include "lpass.h"
21
lpass_cpu_daiops_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)22 static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
23 unsigned int freq, int dir)
24 {
25 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
26 int ret;
27
28 ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
29 if (ret)
30 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n",
31 freq, ret);
32
33 return ret;
34 }
35
lpass_cpu_daiops_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)36 static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
37 struct snd_soc_dai *dai)
38 {
39 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
40 int ret;
41
42 ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]);
43 if (ret) {
44 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
45 return ret;
46 }
47
48 ret = clk_prepare_enable(drvdata->mi2s_bit_clk[dai->driver->id]);
49 if (ret) {
50 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
51 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
52 return ret;
53 }
54
55 return 0;
56 }
57
lpass_cpu_daiops_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)58 static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
59 struct snd_soc_dai *dai)
60 {
61 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
62
63 clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
64
65 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
66 }
67
lpass_cpu_daiops_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)68 static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
69 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
70 {
71 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
72 snd_pcm_format_t format = params_format(params);
73 unsigned int channels = params_channels(params);
74 unsigned int rate = params_rate(params);
75 unsigned int regval;
76 int bitwidth, ret;
77
78 bitwidth = snd_pcm_format_width(format);
79 if (bitwidth < 0) {
80 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth);
81 return bitwidth;
82 }
83
84 regval = LPAIF_I2SCTL_LOOPBACK_DISABLE |
85 LPAIF_I2SCTL_WSSRC_INTERNAL;
86
87 switch (bitwidth) {
88 case 16:
89 regval |= LPAIF_I2SCTL_BITWIDTH_16;
90 break;
91 case 24:
92 regval |= LPAIF_I2SCTL_BITWIDTH_24;
93 break;
94 case 32:
95 regval |= LPAIF_I2SCTL_BITWIDTH_32;
96 break;
97 default:
98 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth);
99 return -EINVAL;
100 }
101
102 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
103 switch (channels) {
104 case 1:
105 regval |= LPAIF_I2SCTL_SPKMODE_SD0;
106 regval |= LPAIF_I2SCTL_SPKMONO_MONO;
107 break;
108 case 2:
109 regval |= LPAIF_I2SCTL_SPKMODE_SD0;
110 regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
111 break;
112 case 4:
113 regval |= LPAIF_I2SCTL_SPKMODE_QUAD01;
114 regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
115 break;
116 case 6:
117 regval |= LPAIF_I2SCTL_SPKMODE_6CH;
118 regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
119 break;
120 case 8:
121 regval |= LPAIF_I2SCTL_SPKMODE_8CH;
122 regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
123 break;
124 default:
125 dev_err(dai->dev, "invalid channels given: %u\n",
126 channels);
127 return -EINVAL;
128 }
129 } else {
130 switch (channels) {
131 case 1:
132 regval |= LPAIF_I2SCTL_MICMODE_SD0;
133 regval |= LPAIF_I2SCTL_MICMONO_MONO;
134 break;
135 case 2:
136 regval |= LPAIF_I2SCTL_MICMODE_SD0;
137 regval |= LPAIF_I2SCTL_MICMONO_STEREO;
138 break;
139 case 4:
140 regval |= LPAIF_I2SCTL_MICMODE_QUAD01;
141 regval |= LPAIF_I2SCTL_MICMONO_STEREO;
142 break;
143 case 6:
144 regval |= LPAIF_I2SCTL_MICMODE_6CH;
145 regval |= LPAIF_I2SCTL_MICMONO_STEREO;
146 break;
147 case 8:
148 regval |= LPAIF_I2SCTL_MICMODE_8CH;
149 regval |= LPAIF_I2SCTL_MICMONO_STEREO;
150 break;
151 default:
152 dev_err(dai->dev, "invalid channels given: %u\n",
153 channels);
154 return -EINVAL;
155 }
156 }
157
158 ret = regmap_write(drvdata->lpaif_map,
159 LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id),
160 regval);
161 if (ret) {
162 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
163 return ret;
164 }
165
166 ret = clk_set_rate(drvdata->mi2s_bit_clk[dai->driver->id],
167 rate * bitwidth * 2);
168 if (ret) {
169 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n",
170 rate * bitwidth * 2, ret);
171 return ret;
172 }
173
174 return 0;
175 }
176
lpass_cpu_daiops_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)177 static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream,
178 struct snd_soc_dai *dai)
179 {
180 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
181 int ret;
182 unsigned int val, mask;
183
184 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
185 val = LPAIF_I2SCTL_SPKEN_ENABLE;
186 mask = LPAIF_I2SCTL_SPKEN_MASK;
187 } else {
188 val = LPAIF_I2SCTL_MICEN_ENABLE;
189 mask = LPAIF_I2SCTL_MICEN_MASK;
190 }
191
192 ret = regmap_update_bits(drvdata->lpaif_map,
193 LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id),
194 mask, val);
195 if (ret)
196 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
197
198 return ret;
199 }
200
lpass_cpu_daiops_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)201 static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
202 int cmd, struct snd_soc_dai *dai)
203 {
204 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
205 int ret = -EINVAL;
206 unsigned int val, mask;
207
208 switch (cmd) {
209 case SNDRV_PCM_TRIGGER_START:
210 case SNDRV_PCM_TRIGGER_RESUME:
211 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
212 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
213 val = LPAIF_I2SCTL_SPKEN_ENABLE;
214 mask = LPAIF_I2SCTL_SPKEN_MASK;
215 } else {
216 val = LPAIF_I2SCTL_MICEN_ENABLE;
217 mask = LPAIF_I2SCTL_MICEN_MASK;
218 }
219
220 ret = regmap_update_bits(drvdata->lpaif_map,
221 LPAIF_I2SCTL_REG(drvdata->variant,
222 dai->driver->id),
223 mask, val);
224 if (ret)
225 dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
226 ret);
227 break;
228 case SNDRV_PCM_TRIGGER_STOP:
229 case SNDRV_PCM_TRIGGER_SUSPEND:
230 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
231 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
232 val = LPAIF_I2SCTL_SPKEN_DISABLE;
233 mask = LPAIF_I2SCTL_SPKEN_MASK;
234 } else {
235 val = LPAIF_I2SCTL_MICEN_DISABLE;
236 mask = LPAIF_I2SCTL_MICEN_MASK;
237 }
238
239 ret = regmap_update_bits(drvdata->lpaif_map,
240 LPAIF_I2SCTL_REG(drvdata->variant,
241 dai->driver->id),
242 mask, val);
243 if (ret)
244 dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
245 ret);
246 break;
247 }
248
249 return ret;
250 }
251
252 const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
253 .set_sysclk = lpass_cpu_daiops_set_sysclk,
254 .startup = lpass_cpu_daiops_startup,
255 .shutdown = lpass_cpu_daiops_shutdown,
256 .hw_params = lpass_cpu_daiops_hw_params,
257 .prepare = lpass_cpu_daiops_prepare,
258 .trigger = lpass_cpu_daiops_trigger,
259 };
260 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);
261
asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai * dai)262 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai)
263 {
264 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
265 int ret;
266
267 /* ensure audio hardware is disabled */
268 ret = regmap_write(drvdata->lpaif_map,
269 LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
270 if (ret)
271 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
272
273 return ret;
274 }
275 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe);
276
277 static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
278 .name = "lpass-cpu",
279 };
280
lpass_cpu_regmap_writeable(struct device * dev,unsigned int reg)281 static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
282 {
283 struct lpass_data *drvdata = dev_get_drvdata(dev);
284 struct lpass_variant *v = drvdata->variant;
285 int i;
286
287 for (i = 0; i < v->i2s_ports; ++i)
288 if (reg == LPAIF_I2SCTL_REG(v, i))
289 return true;
290
291 for (i = 0; i < v->irq_ports; ++i) {
292 if (reg == LPAIF_IRQEN_REG(v, i))
293 return true;
294 if (reg == LPAIF_IRQCLEAR_REG(v, i))
295 return true;
296 }
297
298 for (i = 0; i < v->rdma_channels; ++i) {
299 if (reg == LPAIF_RDMACTL_REG(v, i))
300 return true;
301 if (reg == LPAIF_RDMABASE_REG(v, i))
302 return true;
303 if (reg == LPAIF_RDMABUFF_REG(v, i))
304 return true;
305 if (reg == LPAIF_RDMAPER_REG(v, i))
306 return true;
307 }
308
309 for (i = 0; i < v->wrdma_channels; ++i) {
310 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
311 return true;
312 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
313 return true;
314 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
315 return true;
316 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
317 return true;
318 }
319
320 return false;
321 }
322
lpass_cpu_regmap_readable(struct device * dev,unsigned int reg)323 static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
324 {
325 struct lpass_data *drvdata = dev_get_drvdata(dev);
326 struct lpass_variant *v = drvdata->variant;
327 int i;
328
329 for (i = 0; i < v->i2s_ports; ++i)
330 if (reg == LPAIF_I2SCTL_REG(v, i))
331 return true;
332
333 for (i = 0; i < v->irq_ports; ++i) {
334 if (reg == LPAIF_IRQEN_REG(v, i))
335 return true;
336 if (reg == LPAIF_IRQSTAT_REG(v, i))
337 return true;
338 }
339
340 for (i = 0; i < v->rdma_channels; ++i) {
341 if (reg == LPAIF_RDMACTL_REG(v, i))
342 return true;
343 if (reg == LPAIF_RDMABASE_REG(v, i))
344 return true;
345 if (reg == LPAIF_RDMABUFF_REG(v, i))
346 return true;
347 if (reg == LPAIF_RDMACURR_REG(v, i))
348 return true;
349 if (reg == LPAIF_RDMAPER_REG(v, i))
350 return true;
351 }
352
353 for (i = 0; i < v->wrdma_channels; ++i) {
354 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
355 return true;
356 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
357 return true;
358 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
359 return true;
360 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
361 return true;
362 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
363 return true;
364 }
365
366 return false;
367 }
368
lpass_cpu_regmap_volatile(struct device * dev,unsigned int reg)369 static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
370 {
371 struct lpass_data *drvdata = dev_get_drvdata(dev);
372 struct lpass_variant *v = drvdata->variant;
373 int i;
374
375 for (i = 0; i < v->irq_ports; ++i)
376 if (reg == LPAIF_IRQSTAT_REG(v, i))
377 return true;
378
379 for (i = 0; i < v->rdma_channels; ++i)
380 if (reg == LPAIF_RDMACURR_REG(v, i))
381 return true;
382
383 for (i = 0; i < v->wrdma_channels; ++i)
384 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
385 return true;
386
387 return false;
388 }
389
390 static struct regmap_config lpass_cpu_regmap_config = {
391 .reg_bits = 32,
392 .reg_stride = 4,
393 .val_bits = 32,
394 .writeable_reg = lpass_cpu_regmap_writeable,
395 .readable_reg = lpass_cpu_regmap_readable,
396 .volatile_reg = lpass_cpu_regmap_volatile,
397 .cache_type = REGCACHE_FLAT,
398 };
399
asoc_qcom_lpass_cpu_platform_probe(struct platform_device * pdev)400 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
401 {
402 struct lpass_data *drvdata;
403 struct device_node *dsp_of_node;
404 struct resource *res;
405 struct lpass_variant *variant;
406 struct device *dev = &pdev->dev;
407 const struct of_device_id *match;
408 int ret, i, dai_id;
409
410 dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
411 if (dsp_of_node) {
412 dev_err(&pdev->dev, "DSP exists and holds audio resources\n");
413 return -EBUSY;
414 }
415
416 drvdata = devm_kzalloc(&pdev->dev, sizeof(struct lpass_data),
417 GFP_KERNEL);
418 if (!drvdata)
419 return -ENOMEM;
420 platform_set_drvdata(pdev, drvdata);
421
422 match = of_match_device(dev->driver->of_match_table, dev);
423 if (!match || !match->data)
424 return -EINVAL;
425
426 drvdata->variant = (struct lpass_variant *)match->data;
427 variant = drvdata->variant;
428
429 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif");
430
431 drvdata->lpaif = devm_ioremap_resource(&pdev->dev, res);
432 if (IS_ERR((void const __force *)drvdata->lpaif)) {
433 dev_err(&pdev->dev, "error mapping reg resource: %ld\n",
434 PTR_ERR((void const __force *)drvdata->lpaif));
435 return PTR_ERR((void const __force *)drvdata->lpaif);
436 }
437
438 lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
439 variant->wrdma_channels +
440 variant->wrdma_channel_start);
441
442 drvdata->lpaif_map = devm_regmap_init_mmio(&pdev->dev, drvdata->lpaif,
443 &lpass_cpu_regmap_config);
444 if (IS_ERR(drvdata->lpaif_map)) {
445 dev_err(&pdev->dev, "error initializing regmap: %ld\n",
446 PTR_ERR(drvdata->lpaif_map));
447 return PTR_ERR(drvdata->lpaif_map);
448 }
449
450 if (variant->init)
451 variant->init(pdev);
452
453 for (i = 0; i < variant->num_dai; i++) {
454 dai_id = variant->dai_driver[i].id;
455 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(&pdev->dev,
456 variant->dai_osr_clk_names[i]);
457 if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) {
458 dev_warn(&pdev->dev,
459 "%s() error getting optional %s: %ld\n",
460 __func__,
461 variant->dai_osr_clk_names[i],
462 PTR_ERR(drvdata->mi2s_osr_clk[dai_id]));
463
464 drvdata->mi2s_osr_clk[dai_id] = NULL;
465 }
466
467 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(&pdev->dev,
468 variant->dai_bit_clk_names[i]);
469 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
470 dev_err(&pdev->dev,
471 "error getting %s: %ld\n",
472 variant->dai_bit_clk_names[i],
473 PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
474 return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
475 }
476 }
477
478 drvdata->ahbix_clk = devm_clk_get(&pdev->dev, "ahbix-clk");
479 if (IS_ERR(drvdata->ahbix_clk)) {
480 dev_err(&pdev->dev, "error getting ahbix-clk: %ld\n",
481 PTR_ERR(drvdata->ahbix_clk));
482 return PTR_ERR(drvdata->ahbix_clk);
483 }
484
485 ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY);
486 if (ret) {
487 dev_err(&pdev->dev, "error setting rate on ahbix_clk: %d\n",
488 ret);
489 return ret;
490 }
491 dev_dbg(&pdev->dev, "set ahbix_clk rate to %lu\n",
492 clk_get_rate(drvdata->ahbix_clk));
493
494 ret = clk_prepare_enable(drvdata->ahbix_clk);
495 if (ret) {
496 dev_err(&pdev->dev, "error enabling ahbix_clk: %d\n", ret);
497 return ret;
498 }
499
500 ret = devm_snd_soc_register_component(&pdev->dev,
501 &lpass_cpu_comp_driver,
502 variant->dai_driver,
503 variant->num_dai);
504 if (ret) {
505 dev_err(&pdev->dev, "error registering cpu driver: %d\n", ret);
506 goto err_clk;
507 }
508
509 ret = asoc_qcom_lpass_platform_register(pdev);
510 if (ret) {
511 dev_err(&pdev->dev, "error registering platform driver: %d\n",
512 ret);
513 goto err_clk;
514 }
515
516 return 0;
517
518 err_clk:
519 clk_disable_unprepare(drvdata->ahbix_clk);
520 return ret;
521 }
522 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);
523
asoc_qcom_lpass_cpu_platform_remove(struct platform_device * pdev)524 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
525 {
526 struct lpass_data *drvdata = platform_get_drvdata(pdev);
527
528 if (drvdata->variant->exit)
529 drvdata->variant->exit(pdev);
530
531 clk_disable_unprepare(drvdata->ahbix_clk);
532
533 return 0;
534 }
535 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);
536
537 MODULE_DESCRIPTION("QTi LPASS CPU Driver");
538 MODULE_LICENSE("GPL v2");
539