1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
7 //
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
12 //
13
14 /*
15 * Hardware interface for generic Intel audio DSP HDA IP
16 */
17
18 #include <sound/hdaudio_ext.h>
19 #include <sound/hda_register.h>
20
21 #include <linux/module.h>
22 #include <sound/intel-nhlt.h>
23 #include <sound/sof.h>
24 #include <sound/sof/xtensa.h>
25 #include "../ops.h"
26 #include "hda.h"
27
28 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
29 #include <sound/soc-acpi-intel-match.h>
30 #endif
31
32 /* platform specific devices */
33 #include "shim.h"
34
35 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
36 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
37
38 #define EXCEPT_MAX_HDR_SIZE 0x400
39
40 /*
41 * Debug
42 */
43
44 struct hda_dsp_msg_code {
45 u32 code;
46 const char *msg;
47 };
48
49 static bool hda_use_msi = IS_ENABLED(CONFIG_PCI);
50 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
51 module_param_named(use_msi, hda_use_msi, bool, 0444);
52 MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode");
53 #endif
54
55 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
56 static int hda_dmic_num = -1;
57 module_param_named(dmic_num, hda_dmic_num, int, 0444);
58 MODULE_PARM_DESC(dmic_num, "SOF HDA DMIC number");
59 #endif
60
61 static const struct hda_dsp_msg_code hda_dsp_rom_msg[] = {
62 {HDA_DSP_ROM_FW_MANIFEST_LOADED, "status: manifest loaded"},
63 {HDA_DSP_ROM_FW_FW_LOADED, "status: fw loaded"},
64 {HDA_DSP_ROM_FW_ENTERED, "status: fw entered"},
65 {HDA_DSP_ROM_CSE_ERROR, "error: cse error"},
66 {HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"},
67 {HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"},
68 {HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"},
69 {HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"},
70 {HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"},
71 {HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"},
72 {HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"},
73 {HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"},
74 {HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"},
75 {HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"},
76 {HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"},
77 {HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"},
78 {HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"},
79 {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
80 {HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"},
81 };
82
hda_dsp_get_status_skl(struct snd_sof_dev * sdev)83 static void hda_dsp_get_status_skl(struct snd_sof_dev *sdev)
84 {
85 u32 status;
86 int i;
87
88 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
89 HDA_ADSP_FW_STATUS_SKL);
90
91 for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
92 if (status == hda_dsp_rom_msg[i].code) {
93 dev_err(sdev->dev, "%s - code %8.8x\n",
94 hda_dsp_rom_msg[i].msg, status);
95 return;
96 }
97 }
98
99 /* not for us, must be generic sof message */
100 dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
101 }
102
hda_dsp_get_status(struct snd_sof_dev * sdev)103 static void hda_dsp_get_status(struct snd_sof_dev *sdev)
104 {
105 u32 status;
106 int i;
107
108 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
109 HDA_DSP_SRAM_REG_ROM_STATUS);
110
111 for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
112 if (status == hda_dsp_rom_msg[i].code) {
113 dev_err(sdev->dev, "%s - code %8.8x\n",
114 hda_dsp_rom_msg[i].msg, status);
115 return;
116 }
117 }
118
119 /* not for us, must be generic sof message */
120 dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
121 }
122
hda_dsp_get_registers(struct snd_sof_dev * sdev,struct sof_ipc_dsp_oops_xtensa * xoops,struct sof_ipc_panic_info * panic_info,u32 * stack,size_t stack_words)123 static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
124 struct sof_ipc_dsp_oops_xtensa *xoops,
125 struct sof_ipc_panic_info *panic_info,
126 u32 *stack, size_t stack_words)
127 {
128 u32 offset = sdev->dsp_oops_offset;
129
130 /* first read registers */
131 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
132
133 /* note: variable AR register array is not read */
134
135 /* then get panic info */
136 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
137 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
138 xoops->arch_hdr.totalsize);
139 return;
140 }
141 offset += xoops->arch_hdr.totalsize;
142 sof_block_read(sdev, sdev->mmio_bar, offset,
143 panic_info, sizeof(*panic_info));
144
145 /* then get the stack */
146 offset += sizeof(*panic_info);
147 sof_block_read(sdev, sdev->mmio_bar, offset, stack,
148 stack_words * sizeof(u32));
149 }
150
hda_dsp_dump_skl(struct snd_sof_dev * sdev,u32 flags)151 void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags)
152 {
153 struct sof_ipc_dsp_oops_xtensa xoops;
154 struct sof_ipc_panic_info panic_info;
155 u32 stack[HDA_DSP_STACK_DUMP_SIZE];
156 u32 status, panic;
157
158 /* try APL specific status message types first */
159 hda_dsp_get_status_skl(sdev);
160
161 /* now try generic SOF status messages */
162 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
163 HDA_ADSP_ERROR_CODE_SKL);
164
165 /*TODO: Check: there is no define in spec, but it is used in the code*/
166 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
167 HDA_ADSP_ERROR_CODE_SKL + 0x4);
168
169 if (sdev->fw_state == SOF_FW_BOOT_COMPLETE) {
170 hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
171 HDA_DSP_STACK_DUMP_SIZE);
172 snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
173 stack, HDA_DSP_STACK_DUMP_SIZE);
174 } else {
175 dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
176 status, panic);
177 hda_dsp_get_status_skl(sdev);
178 }
179 }
180
hda_dsp_dump(struct snd_sof_dev * sdev,u32 flags)181 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
182 {
183 struct sof_ipc_dsp_oops_xtensa xoops;
184 struct sof_ipc_panic_info panic_info;
185 u32 stack[HDA_DSP_STACK_DUMP_SIZE];
186 u32 status, panic;
187
188 /* try APL specific status message types first */
189 hda_dsp_get_status(sdev);
190
191 /* now try generic SOF status messages */
192 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
193 HDA_DSP_SRAM_REG_FW_STATUS);
194 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP);
195
196 if (sdev->fw_state == SOF_FW_BOOT_COMPLETE) {
197 hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
198 HDA_DSP_STACK_DUMP_SIZE);
199 snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
200 stack, HDA_DSP_STACK_DUMP_SIZE);
201 } else {
202 dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
203 status, panic);
204 hda_dsp_get_status(sdev);
205 }
206 }
207
hda_ipc_irq_dump(struct snd_sof_dev * sdev)208 void hda_ipc_irq_dump(struct snd_sof_dev *sdev)
209 {
210 struct hdac_bus *bus = sof_to_bus(sdev);
211 u32 adspis;
212 u32 intsts;
213 u32 intctl;
214 u32 ppsts;
215 u8 rirbsts;
216
217 /* read key IRQ stats and config registers */
218 adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
219 intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
220 intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL);
221 ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS);
222 rirbsts = snd_hdac_chip_readb(bus, RIRBSTS);
223
224 dev_err(sdev->dev,
225 "error: hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n",
226 intsts, intctl, rirbsts);
227 dev_err(sdev->dev,
228 "error: dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n",
229 ppsts, adspis);
230 }
231
hda_ipc_dump(struct snd_sof_dev * sdev)232 void hda_ipc_dump(struct snd_sof_dev *sdev)
233 {
234 u32 hipcie;
235 u32 hipct;
236 u32 hipcctl;
237
238 hda_ipc_irq_dump(sdev);
239
240 /* read IPC status */
241 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
242 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
243 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
244
245 /* dump the IPC regs */
246 /* TODO: parse the raw msg */
247 dev_err(sdev->dev,
248 "error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
249 hipcie, hipct, hipcctl);
250 }
251
hda_init(struct snd_sof_dev * sdev)252 static int hda_init(struct snd_sof_dev *sdev)
253 {
254 struct hda_bus *hbus;
255 struct hdac_bus *bus;
256 struct pci_dev *pci = to_pci_dev(sdev->dev);
257 int ret;
258
259 hbus = sof_to_hbus(sdev);
260 bus = sof_to_bus(sdev);
261
262 /* HDA bus init */
263 sof_hda_bus_init(bus, &pci->dev);
264
265 /* Workaround for a communication error on CFL (bko#199007) and CNL */
266 if (IS_CFL(pci) || IS_CNL(pci))
267 bus->polling_mode = 1;
268
269 bus->use_posbuf = 1;
270 bus->bdl_pos_adj = 0;
271 bus->sync_write = 1;
272
273 mutex_init(&hbus->prepare_mutex);
274 hbus->pci = pci;
275 hbus->mixer_assigned = -1;
276 hbus->modelname = "sofbus";
277
278 /* initialise hdac bus */
279 bus->addr = pci_resource_start(pci, 0);
280 #if IS_ENABLED(CONFIG_PCI)
281 bus->remap_addr = pci_ioremap_bar(pci, 0);
282 #endif
283 if (!bus->remap_addr) {
284 dev_err(bus->dev, "error: ioremap error\n");
285 return -ENXIO;
286 }
287
288 /* HDA base */
289 sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr;
290
291 /* get controller capabilities */
292 ret = hda_dsp_ctrl_get_caps(sdev);
293 if (ret < 0)
294 dev_err(sdev->dev, "error: get caps error\n");
295
296 return ret;
297 }
298
299 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
300
check_nhlt_dmic(struct snd_sof_dev * sdev)301 static int check_nhlt_dmic(struct snd_sof_dev *sdev)
302 {
303 struct nhlt_acpi_table *nhlt;
304 int dmic_num;
305
306 nhlt = intel_nhlt_init(sdev->dev);
307 if (nhlt) {
308 dmic_num = intel_nhlt_get_dmic_geo(sdev->dev, nhlt);
309 intel_nhlt_free(nhlt);
310 if (dmic_num == 2 || dmic_num == 4)
311 return dmic_num;
312 }
313
314 return 0;
315 }
316
fixup_tplg_name(struct snd_sof_dev * sdev,const char * sof_tplg_filename,const char * idisp_str,const char * dmic_str)317 static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
318 const char *sof_tplg_filename,
319 const char *idisp_str,
320 const char *dmic_str)
321 {
322 const char *tplg_filename = NULL;
323 char *filename;
324 char *split_ext;
325
326 filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL);
327 if (!filename)
328 return NULL;
329
330 /* this assumes a .tplg extension */
331 split_ext = strsep(&filename, ".");
332 if (split_ext) {
333 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
334 "%s%s%s.tplg",
335 split_ext, idisp_str, dmic_str);
336 if (!tplg_filename)
337 return NULL;
338 }
339 return tplg_filename;
340 }
341
342 #endif
343
hda_init_caps(struct snd_sof_dev * sdev)344 static int hda_init_caps(struct snd_sof_dev *sdev)
345 {
346 struct hdac_bus *bus = sof_to_bus(sdev);
347 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
348 struct hdac_ext_link *hlink;
349 struct snd_soc_acpi_mach_params *mach_params;
350 struct snd_soc_acpi_mach *hda_mach;
351 struct snd_sof_pdata *pdata = sdev->pdata;
352 struct snd_soc_acpi_mach *mach;
353 const char *tplg_filename;
354 const char *idisp_str;
355 const char *dmic_str;
356 int dmic_num;
357 int codec_num = 0;
358 int i;
359 #endif
360 int ret = 0;
361
362 device_disable_async_suspend(bus->dev);
363
364 /* check if dsp is there */
365 if (bus->ppcap)
366 dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n");
367
368 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
369 /* init i915 and HDMI codecs */
370 ret = hda_codec_i915_init(sdev);
371 if (ret < 0) {
372 dev_err(sdev->dev, "error: init i915 and HDMI codec failed\n");
373 return ret;
374 }
375 #endif
376
377 /* Init HDA controller after i915 init */
378 ret = hda_dsp_ctrl_init_chip(sdev, true);
379 if (ret < 0) {
380 dev_err(bus->dev, "error: init chip failed with ret: %d\n",
381 ret);
382 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
383 hda_codec_i915_exit(sdev);
384 #endif
385 return ret;
386 }
387
388 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
389 if (bus->mlcap)
390 snd_hdac_ext_bus_get_ml_capabilities(bus);
391
392 /* codec detection */
393 if (!bus->codec_mask) {
394 dev_info(bus->dev, "no hda codecs found!\n");
395 } else {
396 dev_info(bus->dev, "hda codecs found, mask %lx\n",
397 bus->codec_mask);
398
399 for (i = 0; i < HDA_MAX_CODECS; i++) {
400 if (bus->codec_mask & (1 << i))
401 codec_num++;
402 }
403
404 /*
405 * If no machine driver is found, then:
406 *
407 * hda machine driver is used if :
408 * 1. there is one HDMI codec and one external HDAudio codec
409 * 2. only HDMI codec
410 */
411 if (!pdata->machine && codec_num <= 2 &&
412 HDA_IDISP_CODEC(bus->codec_mask)) {
413 hda_mach = snd_soc_acpi_intel_hda_machines;
414 pdata->machine = hda_mach;
415
416 /* topology: use the info from hda_machines */
417 pdata->tplg_filename =
418 hda_mach->sof_tplg_filename;
419
420 /* firmware: pick the first in machine list */
421 mach = pdata->desc->machines;
422 pdata->fw_filename = mach->sof_fw_filename;
423
424 dev_info(bus->dev, "using HDA machine driver %s now\n",
425 hda_mach->drv_name);
426
427 if (codec_num == 1)
428 idisp_str = "-idisp";
429 else
430 idisp_str = "";
431
432 /* first check NHLT for DMICs */
433 dmic_num = check_nhlt_dmic(sdev);
434
435 /* allow for module parameter override */
436 if (hda_dmic_num != -1)
437 dmic_num = hda_dmic_num;
438
439 switch (dmic_num) {
440 case 2:
441 dmic_str = "-2ch";
442 break;
443 case 4:
444 dmic_str = "-4ch";
445 break;
446 default:
447 dmic_num = 0;
448 dmic_str = "";
449 break;
450 }
451
452 tplg_filename = pdata->tplg_filename;
453 tplg_filename = fixup_tplg_name(sdev, tplg_filename,
454 idisp_str, dmic_str);
455 if (!tplg_filename) {
456 hda_codec_i915_exit(sdev);
457 return ret;
458 }
459 pdata->tplg_filename = tplg_filename;
460 }
461 }
462
463 /* used by hda machine driver to create dai links */
464 if (pdata->machine) {
465 mach_params = (struct snd_soc_acpi_mach_params *)
466 &pdata->machine->mach_params;
467 mach_params->codec_mask = bus->codec_mask;
468 mach_params->platform = dev_name(sdev->dev);
469 }
470
471 /* create codec instances */
472 hda_codec_probe_bus(sdev);
473
474 hda_codec_i915_put(sdev);
475
476 /*
477 * we are done probing so decrement link counts
478 */
479 list_for_each_entry(hlink, &bus->hlink_list, list)
480 snd_hdac_ext_bus_link_put(bus, hlink);
481 #endif
482 return 0;
483 }
484
485 static const struct sof_intel_dsp_desc
get_chip_info(struct snd_sof_pdata * pdata)486 *get_chip_info(struct snd_sof_pdata *pdata)
487 {
488 const struct sof_dev_desc *desc = pdata->desc;
489 const struct sof_intel_dsp_desc *chip_info;
490
491 chip_info = desc->chip_info;
492
493 return chip_info;
494 }
495
hda_dsp_probe(struct snd_sof_dev * sdev)496 int hda_dsp_probe(struct snd_sof_dev *sdev)
497 {
498 struct pci_dev *pci = to_pci_dev(sdev->dev);
499 struct sof_intel_hda_dev *hdev;
500 struct hdac_bus *bus;
501 const struct sof_intel_dsp_desc *chip;
502 int ret = 0;
503
504 /*
505 * detect DSP by checking class/subclass/prog-id information
506 * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required
507 * class=04 subclass 01 prog-if 00: DSP is present
508 * (and may be required e.g. for DMIC or SSP support)
509 * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works
510 */
511 if (pci->class == 0x040300) {
512 dev_err(sdev->dev, "error: the DSP is not enabled on this platform, aborting probe\n");
513 return -ENODEV;
514 } else if (pci->class != 0x040100 && pci->class != 0x040380) {
515 dev_err(sdev->dev, "error: unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", pci->class);
516 return -ENODEV;
517 }
518 dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", pci->class);
519
520 chip = get_chip_info(sdev->pdata);
521 if (!chip) {
522 dev_err(sdev->dev, "error: no such device supported, chip id:%x\n",
523 pci->device);
524 ret = -EIO;
525 goto err;
526 }
527
528 hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL);
529 if (!hdev)
530 return -ENOMEM;
531 sdev->pdata->hw_pdata = hdev;
532 hdev->desc = chip;
533
534 hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
535 PLATFORM_DEVID_NONE,
536 NULL, 0);
537 if (IS_ERR(hdev->dmic_dev)) {
538 dev_err(sdev->dev, "error: failed to create DMIC device\n");
539 return PTR_ERR(hdev->dmic_dev);
540 }
541
542 /*
543 * use position update IPC if either it is forced
544 * or we don't have other choice
545 */
546 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION)
547 hdev->no_ipc_position = 0;
548 #else
549 hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0;
550 #endif
551
552 /* set up HDA base */
553 bus = sof_to_bus(sdev);
554 ret = hda_init(sdev);
555 if (ret < 0)
556 goto hdac_bus_unmap;
557
558 /* DSP base */
559 #if IS_ENABLED(CONFIG_PCI)
560 sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR);
561 #endif
562 if (!sdev->bar[HDA_DSP_BAR]) {
563 dev_err(sdev->dev, "error: ioremap error\n");
564 ret = -ENXIO;
565 goto hdac_bus_unmap;
566 }
567
568 sdev->mmio_bar = HDA_DSP_BAR;
569 sdev->mailbox_bar = HDA_DSP_BAR;
570
571 /* allow 64bit DMA address if supported by H/W */
572 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(64))) {
573 dev_dbg(sdev->dev, "DMA mask is 64 bit\n");
574 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(64));
575 } else {
576 dev_dbg(sdev->dev, "DMA mask is 32 bit\n");
577 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
578 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
579 }
580
581 /* init streams */
582 ret = hda_dsp_stream_init(sdev);
583 if (ret < 0) {
584 dev_err(sdev->dev, "error: failed to init streams\n");
585 /*
586 * not all errors are due to memory issues, but trying
587 * to free everything does not harm
588 */
589 goto free_streams;
590 }
591
592 /*
593 * register our IRQ
594 * let's try to enable msi firstly
595 * if it fails, use legacy interrupt mode
596 * TODO: support msi multiple vectors
597 */
598 if (hda_use_msi && pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) > 0) {
599 dev_info(sdev->dev, "use msi interrupt mode\n");
600 hdev->irq = pci_irq_vector(pci, 0);
601 /* ipc irq number is the same of hda irq */
602 sdev->ipc_irq = hdev->irq;
603 /* initialised to "false" by kzalloc() */
604 sdev->msi_enabled = true;
605 }
606
607 if (!sdev->msi_enabled) {
608 dev_info(sdev->dev, "use legacy interrupt mode\n");
609 /*
610 * in IO-APIC mode, hda->irq and ipc_irq are using the same
611 * irq number of pci->irq
612 */
613 hdev->irq = pci->irq;
614 sdev->ipc_irq = pci->irq;
615 }
616
617 dev_dbg(sdev->dev, "using HDA IRQ %d\n", hdev->irq);
618 ret = request_threaded_irq(hdev->irq, hda_dsp_stream_interrupt,
619 hda_dsp_stream_threaded_handler,
620 IRQF_SHARED, "AudioHDA", bus);
621 if (ret < 0) {
622 dev_err(sdev->dev, "error: failed to register HDA IRQ %d\n",
623 hdev->irq);
624 goto free_irq_vector;
625 }
626
627 dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq);
628 ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_ipc_irq_handler,
629 sof_ops(sdev)->irq_thread, IRQF_SHARED,
630 "AudioDSP", sdev);
631 if (ret < 0) {
632 dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n",
633 sdev->ipc_irq);
634 goto free_hda_irq;
635 }
636
637 pci_set_master(pci);
638 synchronize_irq(pci->irq);
639
640 /*
641 * clear TCSEL to clear playback on some HD Audio
642 * codecs. PCI TCSEL is defined in the Intel manuals.
643 */
644 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
645
646 /* init HDA capabilities */
647 ret = hda_init_caps(sdev);
648 if (ret < 0)
649 goto free_ipc_irq;
650
651 /* enable ppcap interrupt */
652 hda_dsp_ctrl_ppcap_enable(sdev, true);
653 hda_dsp_ctrl_ppcap_int_enable(sdev, true);
654
655 /* initialize waitq for code loading */
656 init_waitqueue_head(&sdev->waitq);
657
658 /* set default mailbox offset for FW ready message */
659 sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET;
660
661 return 0;
662
663 free_ipc_irq:
664 free_irq(sdev->ipc_irq, sdev);
665 free_hda_irq:
666 free_irq(hdev->irq, bus);
667 free_irq_vector:
668 if (sdev->msi_enabled)
669 pci_free_irq_vectors(pci);
670 free_streams:
671 hda_dsp_stream_free(sdev);
672 /* dsp_unmap: not currently used */
673 iounmap(sdev->bar[HDA_DSP_BAR]);
674 hdac_bus_unmap:
675 platform_device_unregister(hdev->dmic_dev);
676 iounmap(bus->remap_addr);
677 err:
678 return ret;
679 }
680
hda_dsp_remove(struct snd_sof_dev * sdev)681 int hda_dsp_remove(struct snd_sof_dev *sdev)
682 {
683 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
684 struct hdac_bus *bus = sof_to_bus(sdev);
685 struct pci_dev *pci = to_pci_dev(sdev->dev);
686 const struct sof_intel_dsp_desc *chip = hda->desc;
687
688 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
689 /* codec removal, invoke bus_device_remove */
690 snd_hdac_ext_bus_device_remove(bus);
691 #endif
692
693 if (!IS_ERR_OR_NULL(hda->dmic_dev))
694 platform_device_unregister(hda->dmic_dev);
695
696 /* disable DSP IRQ */
697 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
698 SOF_HDA_PPCTL_PIE, 0);
699
700 /* disable CIE and GIE interrupts */
701 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
702 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0);
703
704 /* disable cores */
705 if (chip)
706 hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
707
708 /* disable DSP */
709 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
710 SOF_HDA_PPCTL_GPROCEN, 0);
711
712 free_irq(sdev->ipc_irq, sdev);
713 free_irq(hda->irq, bus);
714 if (sdev->msi_enabled)
715 pci_free_irq_vectors(pci);
716
717 hda_dsp_stream_free(sdev);
718 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
719 snd_hdac_link_free_all(bus);
720 #endif
721
722 iounmap(sdev->bar[HDA_DSP_BAR]);
723 iounmap(bus->remap_addr);
724
725 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
726 snd_hdac_ext_bus_exit(bus);
727 #endif
728 hda_codec_i915_exit(sdev);
729
730 return 0;
731 }
732
733 MODULE_LICENSE("Dual BSD/GPL");
734