Lines Matching full:when

43       SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
44       PHY is suspended. suspend clocks a small part of the USB3 core when
85       When set, disable isoc START TRANSFER command failure SW work-around
91       True when SW should disable data scrambling. Only really useful for FPGA
96     description: True when DWC3 was configured with LPM Erratum enabled
113       When set, the core will always request for P1/P2/P3 transition sequence.
118       When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
123     description: When set core will delay PHY power change from P0 to P1/P2/P3.
127     description: When set core will filter LFPS reception.
132       when set core will disable a 400us delay to start Polling LFPS after
137     description: When set core will set Tx de-emphasis value
147     description: When set core will disable USB3 suspend phy
151     description: When set core will disable USB2 suspend phy
156       When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
170       When set core will disable receiver detection in PHY P3 power state.
175       When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
181       When set core will change PHY power from P0 to P1/P2/P3 without delay.
185     description: When set, disable u2mac linestate check during HS transmit
190       When set, all SuperSpeed bus instances in park mode are disabled.
195       When set, disable metastability workaround. CAUTION! Use only if you are
201       When set, change the way URBs are handled by the driver. Needed to
207       True when DWC3 asserts output signal utmi_l1_suspend_n, false when
217       High-Speed PHY interface selection between UTMI+ and ULPI when the
225       length adjustment when the fladj_30mhz_sdbnd signal is invalid or
275       can account for when higher endpoint bursting is used. (bMaxBurst > 6) The