1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/snps,dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Synopsys DesignWare USB3 Controller 8 9maintainers: 10 - Felipe Balbi <balbi@kernel.org> 11 12description: 13 This is usually a subnode to DWC3 glue to which it is connected, but can also 14 be presented as a standalone DT node with an optional vendor-specific 15 compatible string. 16 17allOf: 18 - $ref: usb-drd.yaml# 19 - if: 20 properties: 21 dr_mode: 22 const: peripheral 23 24 required: 25 - dr_mode 26 then: 27 $ref: usb.yaml# 28 else: 29 $ref: usb-xhci.yaml# 30 31properties: 32 compatible: 33 contains: 34 const: snps,dwc3 35 36 interrupts: 37 minItems: 1 38 maxItems: 3 39 40 clocks: 41 description: 42 In general the core supports three types of clocks. bus_early is a 43 SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI 44 PHY is suspended. suspend clocks a small part of the USB3 core when 45 SS PHY in P3. But particular cases may differ from that having less 46 or more clock sources with another names. 47 48 clock-names: 49 contains: 50 anyOf: 51 - enum: [bus_early, ref, suspend] 52 - true 53 54 usb-phy: 55 minItems: 1 56 items: 57 - description: USB2/HS PHY 58 - description: USB3/SS PHY 59 60 phys: 61 minItems: 1 62 items: 63 - description: USB2/HS PHY 64 - description: USB3/SS PHY 65 66 phy-names: 67 minItems: 1 68 items: 69 - const: usb2-phy 70 - const: usb3-phy 71 72 resets: 73 minItems: 1 74 75 snps,usb2-lpm-disable: 76 description: Indicate if we don't want to enable USB2 HW LPM 77 type: boolean 78 79 snps,usb3_lpm_capable: 80 description: Determines if platform is USB3 LPM capable 81 type: boolean 82 83 snps,dis-start-transfer-quirk: 84 description: 85 When set, disable isoc START TRANSFER command failure SW work-around 86 for DWC_usb31 version 1.70a-ea06 and prior. 87 type: boolean 88 89 snps,disable_scramble_quirk: 90 description: 91 True when SW should disable data scrambling. Only really useful for FPGA 92 builds. 93 type: boolean 94 95 snps,has-lpm-erratum: 96 description: True when DWC3 was configured with LPM Erratum enabled 97 type: boolean 98 99 snps,lpm-nyet-threshold: 100 description: LPM NYET threshold 101 $ref: /schemas/types.yaml#/definitions/uint8 102 103 snps,u2exit_lfps_quirk: 104 description: Set if we want to enable u2exit lfps quirk 105 type: boolean 106 107 snps,u2ss_inp3_quirk: 108 description: Set if we enable P3 OK for U2/SS Inactive quirk 109 type: boolean 110 111 snps,req_p1p2p3_quirk: 112 description: 113 When set, the core will always request for P1/P2/P3 transition sequence. 114 type: boolean 115 116 snps,del_p1p2p3_quirk: 117 description: 118 When set core will delay P1/P2/P3 until a certain amount of 8B10B errors 119 occur. 120 type: boolean 121 122 snps,del_phy_power_chg_quirk: 123 description: When set core will delay PHY power change from P0 to P1/P2/P3. 124 type: boolean 125 126 snps,lfps_filter_quirk: 127 description: When set core will filter LFPS reception. 128 type: boolean 129 130 snps,rx_detect_poll_quirk: 131 description: 132 when set core will disable a 400us delay to start Polling LFPS after 133 RX.Detect. 134 type: boolean 135 136 snps,tx_de_emphasis_quirk: 137 description: When set core will set Tx de-emphasis value 138 type: boolean 139 140 snps,tx_de_emphasis: 141 description: 142 The value driven to the PHY is controlled by the LTSSM during USB3 143 Compliance mode. 144 $ref: /schemas/types.yaml#/definitions/uint8 145 146 snps,dis_u3_susphy_quirk: 147 description: When set core will disable USB3 suspend phy 148 type: boolean 149 150 snps,dis_u2_susphy_quirk: 151 description: When set core will disable USB2 suspend phy 152 type: boolean 153 154 snps,dis_enblslpm_quirk: 155 description: 156 When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal 157 to the PHY. 158 type: boolean 159 160 snps,dis-u1-entry-quirk: 161 description: Set if link entering into U1 needs to be disabled 162 type: boolean 163 164 snps,dis-u2-entry-quirk: 165 description: Set if link entering into U2 needs to be disabled 166 type: boolean 167 168 snps,dis_rxdet_inp3_quirk: 169 description: 170 When set core will disable receiver detection in PHY P3 power state. 171 type: boolean 172 173 snps,dis-u2-freeclk-exists-quirk: 174 description: 175 When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2 176 PHY doesn't provide a free-running PHY clock. 177 type: boolean 178 179 snps,dis-del-phy-power-chg-quirk: 180 description: 181 When set core will change PHY power from P0 to P1/P2/P3 without delay. 182 type: boolean 183 184 snps,dis-tx-ipgap-linecheck-quirk: 185 description: When set, disable u2mac linestate check during HS transmit 186 type: boolean 187 188 snps,parkmode-disable-ss-quirk: 189 description: 190 When set, all SuperSpeed bus instances in park mode are disabled. 191 type: boolean 192 193 snps,dis_metastability_quirk: 194 description: 195 When set, disable metastability workaround. CAUTION! Use only if you are 196 absolutely sure of it. 197 type: boolean 198 199 snps,dis-split-quirk: 200 description: 201 When set, change the way URBs are handled by the driver. Needed to 202 avoid -EPROTO errors with usbhid on some devices (Hikey 970). 203 type: boolean 204 205 snps,is-utmi-l1-suspend: 206 description: 207 True when DWC3 asserts output signal utmi_l1_suspend_n, false when 208 asserts utmi_sleep_n. 209 type: boolean 210 211 snps,hird-threshold: 212 description: HIRD threshold 213 $ref: /schemas/types.yaml#/definitions/uint8 214 215 snps,hsphy_interface: 216 description: 217 High-Speed PHY interface selection between UTMI+ and ULPI when the 218 DWC_USB3_HSPHY_INTERFACE has value 3. 219 $ref: /schemas/types.yaml#/definitions/uint8 220 enum: [utmi, ulpi] 221 222 snps,quirk-frame-length-adjustment: 223 description: 224 Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame 225 length adjustment when the fladj_30mhz_sdbnd signal is invalid or 226 incorrect. 227 $ref: /schemas/types.yaml#/definitions/uint32 228 229 snps,rx-thr-num-pkt-prd: 230 description: 231 Periodic ESS RX packet threshold count (host mode only). Set this and 232 snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31 233 programming guide section 1.2.4) to enable periodic ESS RX threshold. 234 $ref: /schemas/types.yaml#/definitions/uint8 235 minimum: 1 236 maximum: 16 237 238 snps,rx-max-burst-prd: 239 description: 240 Max periodic ESS RX burst size (host mode only). Set this and 241 snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31 242 programming guide section 1.2.4) to enable periodic ESS RX threshold. 243 $ref: /schemas/types.yaml#/definitions/uint8 244 minimum: 1 245 maximum: 16 246 247 snps,tx-thr-num-pkt-prd: 248 description: 249 Periodic ESS TX packet threshold count (host mode only). Set this and 250 snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31 251 programming guide section 1.2.3) to enable periodic ESS TX threshold. 252 $ref: /schemas/types.yaml#/definitions/uint8 253 minimum: 1 254 maximum: 16 255 256 snps,tx-max-burst-prd: 257 description: 258 Max periodic ESS TX burst size (host mode only). Set this and 259 snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31 260 programming guide section 1.2.3) to enable periodic ESS TX threshold. 261 $ref: /schemas/types.yaml#/definitions/uint8 262 minimum: 1 263 maximum: 16 264 265 tx-fifo-resize: 266 description: Determines if the TX fifos can be dynamically resized depending 267 on the number of IN endpoints used and if bursting is supported. This 268 may help improve bandwidth on platforms with higher system latencies, as 269 increased fifo space allows for the controller to prefetch data into its 270 internal memory. 271 type: boolean 272 273 tx-fifo-max-num: 274 description: Specifies the max number of packets the txfifo resizing logic 275 can account for when higher endpoint bursting is used. (bMaxBurst > 6) The 276 higher the number, the more fifo space the txfifo resizing logic will 277 allocate for that endpoint. 278 $ref: /schemas/types.yaml#/definitions/uint8 279 minimum: 3 280 281 snps,incr-burst-type-adjustment: 282 description: 283 Value for INCR burst type of GSBUSCFG0 register, undefined length INCR 284 burst type enable and INCRx type. A single value means INCRX burst mode 285 enabled. If more than one value specified, undefined length INCR burst 286 type will be enabled with burst lengths utilized up to the maximum 287 of the values passed in this property. 288 $ref: /schemas/types.yaml#/definitions/uint32-array 289 minItems: 1 290 maxItems: 8 291 uniqueItems: true 292 items: 293 enum: [1, 4, 8, 16, 32, 64, 128, 256] 294 295unevaluatedProperties: false 296 297required: 298 - compatible 299 - reg 300 - interrupts 301 302examples: 303 - | 304 usb@4a030000 { 305 compatible = "snps,dwc3"; 306 reg = <0x4a030000 0xcfff>; 307 interrupts = <0 92 4>; 308 usb-phy = <&usb2_phy>, <&usb3_phy>; 309 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 310 }; 311 - | 312 usb@4a000000 { 313 compatible = "snps,dwc3"; 314 reg = <0x4a000000 0xcfff>; 315 interrupts = <0 92 4>; 316 clocks = <&clk 1>, <&clk 2>, <&clk 3>; 317 clock-names = "bus_early", "ref", "suspend"; 318 phys = <&usb2_phy>, <&usb3_phy>; 319 phy-names = "usb2-phy", "usb3-phy"; 320 snps,dis_u2_susphy_quirk; 321 snps,dis_enblslpm_quirk; 322 }; 323... 324