Home
last modified time | relevance | path

Searched +full:- +full:pins (Results 1 – 25 of 453) sorted by relevance

12345678910>>...19

/Documentation/devicetree/bindings/pinctrl/
Dste,abx500.txt4 - compatible: "stericsson,ab8500-gpio", "stericsson,ab8540-gpio",
5 "stericsson,ab8505-gpio", "stericsson,ab9540-gpio",
7 Please refer to pinctrl-bindings.txt in this directory for details of the
12 and pin configuration bindings, see pinctrl-bindings.txt
17 pinctrl-names = "default";
18 …pinctrl-0 = <&sysclkreq2_default_mode>, <&sysclkreq3_default_mode>, <&gpio3_default_mode>, <&syscl…
27 pins = "GPIO1";
28 bias-disable;
39 pins = "GPIO2";
40 output-low;
[all …]
Dmarvell,mvebu-pinctrl.txt3 The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
7 Please refer to pinctrl-bindings.txt in this directory for details of the
11 A Marvell SoC pin configuration node is a node of a group of pins which can
13 mpp pins or group of pins and a mpp function common to all pins.
16 - compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
20 - marvell,pins: string array of mpp pins or group of pins to be muxed.
21 - marvell,function: string representing a function to mux to for all
22 marvell,pins given in this pin configuration node. The function has to be
23 common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
[all …]
Dmarvell,armada-37xx-pinctrl.txt12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
33 - pins 20-24
34 - functions jtag, gpio
37 - pins 8-10
38 - functions sdio, gpio
[all …]
Dnxp,lpc1850-scu.txt2 --------------------------------------------------------
5 - compatible : Should be "nxp,lpc1850-scu"
6 - reg : Address and length of the register set for the device
7 - clocks : Clock specifier (see clock bindings for details)
9 The lpc1850-scu driver uses the generic pin multiplexing and generic pin
10 configuration documented in pinctrl-bindings.txt.
13 - function
14 - pins
15 - bias-disable
16 - bias-pull-up
[all …]
Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
16 name pins functions
23 uart1(cts), lcd-spi(cs1), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
39 mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
41 ac97-1(sysclko)
[all …]
Dqcom,msm8960-pinctrl.txt6 - compatible:
9 Definition: must be "qcom,msm8960-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
26 - #interrupt-cells:
30 in <dt-bindings/interrupt-controller/irq.h>
32 - gpio-controller:
[all …]
Dqcom,apq8084-pinctrl.txt6 - compatible:
9 Definition: must be "qcom,apq8084-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
26 - #interrupt-cells:
30 in <dt-bindings/interrupt-controller/irq.h>
32 - gpio-controller:
[all …]
Dpinctrl-zx.txt10 GMII_RXD3 ---+
12 DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin)
14 BGPIO16 ---+ ^
26 KEY_ROW2 ---+ v
27 PORT1_LCD_TE ---+ |
28 | AGPIO10 ---+------ KEY_ROW2 (AON pin)
29 I2S0_DOUT3 ---+ |
30 |-----------------------+
31 PWM_OUT3 ---+
33 VGA_VS1 ---+
[all …]
Dqcom,msm8976-pinctrl.txt6 - compatible:
9 Definition: must be "qcom,msm8976-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
26 - #interrupt-cells:
30 in <dt-bindings/interrupt-controller/irq.h>
32 - gpio-controller:
[all …]
Dqcom,sdm845-pinctrl.txt6 - compatible:
9 Definition: must be "qcom,sdm845-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
26 - #interrupt-cells:
30 in <dt-bindings/interrupt-controller/irq.h>
32 - gpio-controller:
[all …]
Dpinctrl-palmas.txt3 The pins of Palmas device can be set on different option and provides
7 - compatible: It must be one of following:
8 - "ti,palmas-pinctrl" for Palma series of the pincontrol.
9 - "ti,tps65913-pinctrl" for Palma series device TPS65913.
10 - "ti,tps80036-pinctrl" for Palma series device TPS80036.
12 Please refer to pinctrl-bindings.txt in this directory for details of the
18 list of pins. This configuration can include the mux function to select on
19 those pin(s), and various pin configuration parameters, such as pull-up,
32 - ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode.
35 - ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode.
[all …]
Dqcom,msm8916-pinctrl.txt6 - compatible:
9 Definition: must be "qcom,msm8916-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
26 - #interrupt-cells:
30 in <dt-bindings/interrupt-controller/irq.h>
32 - gpio-controller:
[all …]
Dqcom,mdm9615-pinctrl.txt6 - compatible:
9 Definition: must be "qcom,mdm9615-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
26 - #interrupt-cells:
30 in <dt-bindings/interrupt-controller/irq.h>
32 - gpio-controller:
[all …]
Dqcom,ipq8074-pinctrl.txt6 - compatible:
9 Definition: must be "qcom,ipq8074-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
26 - #interrupt-cells:
30 in <dt-bindings/interrupt-controller/irq.h>
32 - gpio-controller:
[all …]
Dfsl,mxs-pinctrl.txt3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
5 function is GPIO. The configuration on the pins includes drive strength,
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
13 Please refer to pinctrl-bindings.txt in this directory for details of the
18 a group of pins, and only affects those parameters that are explicitly listed.
20 information about pull-up. For this reason, even seemingly boolean values are
26 One is to set up a group of pins for a function, both mux selection and pin
[all …]
Dqcom,msm8998-pinctrl.txt6 - compatible:
9 Definition: must be "qcom,msm8998-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
26 - #interrupt-cells:
30 in <dt-bindings/interrupt-controller/irq.h>
32 - gpio-controller:
[all …]
Dqcom,msm8994-pinctrl.txt6 - compatible:
10 "qcom,msm8992-pinctrl",
11 "qcom,msm8994-pinctrl".
13 - reg:
15 Value type: <prop-encoded-array>
18 - interrupts:
20 Value type: <prop-encoded-array>
23 - interrupt-controller:
28 - #interrupt-cells:
32 in <dt-bindings/interrupt-controller/irq.h>
[all …]
Doxnas,pinctrl.txt3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
7 OXNAS 'pin configuration node' is a node of a group of pins which can be
9 pins, optional function, and optional mux related configuration.
12 - compatible: "oxsemi,ox810se-pinctrl" or "oxsemi,ox820-pinctrl"
13 - oxsemi,sys-ctrl: a phandle to the system controller syscon node
15 Required properties for pin configuration sub-nodes:
16 - pins: List of pins to which the configuration applies.
18 Optional properties for pin configuration sub-nodes:
19 ----------------------------------------------------
[all …]
Dqcom,msm8996-pinctrl.txt6 - compatible:
9 Definition: must be "qcom,msm8996-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
26 - #interrupt-cells:
30 in <dt-bindings/interrupt-controller/irq.h>
32 - gpio-controller:
[all …]
Dmscc,ocelot-pinctrl.txt2 ----------------------------------------------------
5 - compatible : Should be "mscc,ocelot-pinctrl",
6 "mscc,jaguar2-pinctrl" or "microchip,sparx5-pinctrl"
7 - reg : Address and length of the register set for the device
8 - gpio-controller : Indicates this device is a GPIO controller
9 - #gpio-cells : Must be 2.
12 <dt-bindings/gpio/gpio.h>.
13 - gpio-ranges : Range of pins managed by the GPIO controller.
16 The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin
17 configuration documented in pinctrl-bindings.txt.
[all …]
Dbrcm,bcm11351-pinctrl.txt10 - compatible: Must be "brcm,bcm11351-pinctrl"
11 - reg: Base address of the PAD Controller register block and the size
17 compatible = "brcm,bcm11351-pinctrl";
27 Each pin configuration node is a sub-node of the pin controller node and is a
31 Please refer to the pinctrl-bindings.txt in this directory for details of the
38 arbitrary number of pins. The name of the pin group node is optional and not
45 details generic pin config properties, please refer to pinctrl-bindings.txt
46 and <include/linux/pinctrl/pinconfig-generic.h>.
50 properties. A list of pins and their types is provided below.
52 Required Properties (applicable to all pins):
[all …]
/Documentation/devicetree/bindings/clock/
Dclk-palmas-clk32kg-clocks.txt3 Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
5 This binding uses the common clock binding ./clock-bindings.txt.
8 - compatible : "ti,palmas-clk32kg" for clk32kg clock
9 "ti,palmas-clk32kgaudio" for clk32kgaudio clock
10 - #clock-cells : shall be set to 0.
13 - ti,external-sleep-control: The external enable input pins controlled the
14 enable/disable of clocks. The external enable input pins ENABLE1,
15 ENABLE2 and NSLEEP. The valid values for the external pins are:
20 via register access and these pins do not have any control.
21 The macros of external control pins for DTS is defined at
[all …]
/Documentation/driver-api/
Dpinctl.rst9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up/down, open drain,
17 Top-level interface
22 - A pin controller is a piece of hardware, usually a set of registers, that
23 can control PINs. It may be able to multiplex, bias, set load capacitance,
24 set drive strength, etc. for individual pins or groups of pins.
28 - PINS are equal to pads, fingers, balls or whatever packaging input or
32 be sparse - i.e. there may be gaps in the space with numbers where no
[all …]
/Documentation/hwmon/
Dpcf8591.rst17 - Aurelien Jarno <aurelien@aurel32.net>
18 - valuable contributions by Jan M. Sendler <sendler@sendler.de>,
19 - Jean Delvare <jdelvare@suse.de>
23 -----------
25 The PCF8591 is an 8-bit A/D and D/A converter (4 analog inputs and one
29 The PCF8591 has 4 analog inputs programmable as single-ended or
32 - mode 0 : four single ended inputs
33 Pins AIN0 to AIN3 are single ended inputs for channels 0 to 3
35 - mode 1 : three differential inputs
36 Pins AIN3 is the common negative differential input
[all …]
/Documentation/devicetree/bindings/input/
Dnvidia,tegra20-kbc.txt2 The key controller has maximum 24 pins to make matrix keypad. Any pin
4 and maximum row pins can be 16 for Tegra20/Tegra30.
7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
[all …]

12345678910>>...19