Searched +full:0 +full:x3000 (Results 1 – 25 of 26) sorted by relevance
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-thunderx.txt | 20 gpio_6_0: gpio@6,0 {
22 reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */
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| /Documentation/devicetree/bindings/virtio/ |
| D | mmio.txt | 31 reg = <0x3000 0x100>;
40 reg = <0x3100 0x100>;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | snps,dw-apb-ictl.txt | 20 - 0 maps to bit 0 of low interrupts,
22 - 32 maps to bit 0 of high interrupts,
30 reg = <0x3000 0xc00>;
40 reg = <0x10130000 0x1000>;
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| /Documentation/admin-guide/media/ |
| D | dvb-usb-dw2102-cardlist.rst | 11 :stub-columns: 0
15 * - DVBWorld DVB-C 3101 USB2.0
17 * - DVBWorld DVB-S 2101 USB2.0
18 - 04b4:0x2101
19 * - DVBWorld DVB-S 2102 USB2.0
21 * - DVBWorld DW2104 USB2.0
24 - 0x1FE1:5456
25 * - Geniatech T220 DVB-T/T2 USB2.0
26 - 0x1f4d:0xD220
27 * - SU3000HD DVB-S USB2.0
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | davinci_emac.txt | 32 reg = <0x220000 0x4000>;
33 ti,davinci-ctrl-reg-offset = <0x3000>;
34 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
35 ti,davinci-ctrl-ram-offset = <0>;
36 ti,davinci-ctrl-ram-size = <0x2000>;
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| /Documentation/devicetree/bindings/mailbox/ |
| D | mtk-gce.txt | 46 reg = <0 0x10212000 0 0x1000>;
57 mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST>,
61 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>,
62 <&gce SUBSYS_1401XXXX 0x2000 0x100>;
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | st,stm32-pinctrl.yaml | 46 - The field mask of IRQ mux, needed if different of 0xf.
57 '^gpio@[0-9a-f]*$':
103 minimum: 0
113 '-[0-9]*$':
132 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
133 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
135 * 0 : GPIO
136 * 1 : Alternate Function 0
175 0: Low speed
180 enum: [0, 1, 2, 3]
[all …]
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| /Documentation/devicetree/bindings/dma/ |
| D | st_fdma.txt | 27 reg = <0x8e20000 0x8000>,
28 <0x8e30000 0x3000>,
29 <0x8e37000 0x1000>,
30 <0x8e38000 0x8000>;
51 -bit 2-0: Holdoff value, dreq will be masked for
52 0x0: 0-0.5us
53 0x1: 0.5-1us
54 0x2: 1-1.5us
56 0x0: disabled
57 0x1: enabled
[all …]
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,wcnss.txt | 83 interrupts = <0 142 1>;
107 interrupts = <0 145 0>, <0 146 0>;
121 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
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| /Documentation/devicetree/bindings/sound/ |
| D | davinci-mcasp-audio.txt | 15 - op-mode : I2S/DIT ops mode. 0 for I2S mode. 1 for DIT mode used for S/PDIF,
21 (0 - INACTIVE, 1 - TX, 2 - RX)
30 - ti,hwmods : Must be "mcasp<n>", n is controller instance starting 0
34 0 : 3-state
42 - pinctrl-0: Should specify pin control group used for this controller.
61 function-gpios = <&mcasp8 2 0>;
64 function-gpios = <&mcasp8 29 0>;
72 reg = <0x100000 0x3000>;
76 op-mode = <0>; /* MCASP_IIS_MODE */
79 0 0 0 0 /* 0: INACTIVE, 1: TX, 2: RX */
[all …]
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| /Documentation/devicetree/bindings/iommu/ |
| D | qcom,iommu.txt | 58 ranges = <0 0x1e20000 0x40000>;
59 reg = <0x1ef0000 0x3000>;
68 reg = <0x4000 0x1000>;
75 reg = <0x5000 0x1000>;
85 ranges = <0 0x1f08000 0x10000>;
94 reg = <0x1000 0x1000>;
101 reg = <0x2000 0x1000>;
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-mtk-xsphy.txt | 59 u2 port0 0x0000 MISC
60 0x0100 FMREG
61 0x0300 U2PHY_COM
62 u2 port1 0x1000 MISC
63 0x1100 FMREG
64 0x1300 U2PHY_COM
65 u2 port2 0x2000 MISC
67 u31 common 0x3000 DIG_GLB
68 0x3100 PHYA_GLB
69 u31 port0 0x3400 DIG_LN_TOP
[all …]
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| /Documentation/devicetree/bindings/display/msm/ |
| D | mdp5.txt | 63 Port 0 -> MDP_INTF0 (eDP)
69 Port 0 -> MDP_INTF1 (DSI1)
72 Port 0 -> MDP_INTF1 (DSI1)
89 reg = <0x1a00000 0x1000>,
90 <0x1ac8000 0x3000>;
102 interrupts = <0 72 0>;
113 reg = <0x1a01000 0x90000>;
117 interrupts = <0 0>;
130 #size-cells = <0>;
132 port@0 {
[all …]
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,wcnss-pil.txt | 104 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
107 interrupts-extended = <&intc 0 149 1>,
108 <&wcnss_smp2p_slave 0 0>,
109 <&wcnss_smp2p_slave 1 0>,
110 <&wcnss_smp2p_slave 2 0>,
111 <&wcnss_smp2p_slave 3 0>;
118 qcom,smem-states = <&wcnss_smp2p_out 0>;
124 pinctrl-0 = <&wcnss_pin_a>;
139 interrupts = <0 142 1>;
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| /Documentation/devicetree/bindings/pci/ |
| D | ti-pci.txt | 74 ranges = <0x51000000 0x51000000 0x3000
75 0x0 0x20000000 0x10000000>;
78 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
80 interrupts = <0 232 0x4>, <0 233 0x4>;
84 ranges = <0x81000000 0 0 0x03000 0 0x00010000
85 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
91 interrupt-map-mask = <0 0 0 7>;
92 interrupt-map = <0 0 0 1 &pcie_intc 1>,
93 <0 0 0 2 &pcie_intc 2>,
94 <0 0 0 3 &pcie_intc 3>,
[all …]
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| D | mvebu-pci.txt | 23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
93 bus-range = <0x00 0xff>;
97 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
98 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
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| /Documentation/devicetree/bindings/usb/ |
| D | mediatek,mtu3.txt | 1 The device node for Mediatek USB3.0 DRD controller
42 - pinctrl-0 : pin control group
77 reg = <0 0x11271000 0 0x3000>,
78 <0 0x11280700 0 0x0100>;
93 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
100 reg = <0 0x11270000 0 0x1000>;
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | pamu.txt | 12 "fsl,pamu-v1.0". The second is "fsl,pamu".
18 PAMU v1.0, on an SOC that has five PAMU devices, the size
19 is 0x5000.
56 For PAMU v1.0, this size is 0x1000.
95 compatible = "fsl,pamu-v1.0", "fsl,pamu";
96 reg = <0x20000 0x5000>;
97 ranges = <0 0x20000 0x5000>;
98 fsl,portid-mapping = <0xf80000>;
102 24 2 0 0
105 pamu0: pamu@0 {
[all …]
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| D | mpic.txt | 19 Revision Registers BRR1 and BRR2 at offset 0x0 and
20 0x10 in the MPIC.
45 Definition: Shall be 0.
93 interrupt-type 0-- i.e. an external or
97 0 = low-to-high edge triggered
106 0 = external or normal SoC device interrupt
116 region. So interrupt 0 is at offset 0x0,
117 interrupt 1 is at offset 0x20, and so on.
156 #address-cells = <0>;
157 reg = <0x40000 0x40000>;
[all …]
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| D | interlaken-lac.txt | 31 There is a full register set at 0x0000-0x0FFF (also known as the "hypervisor"
32 version), and a subset at 0x1000-0x1FFF. The former is a superset of the
45 IP Block Revision Register (IPBRR0) at offset 0x0BF8.
51 0x02000100 T4240
78 reg = <0x229000 0x1000>;
84 reg = <0x228000 0x1000>;
136 Register (IPBRR0), at offset 0x0BF8, and Y is the Minor version
161 #address-cells = <0x1>;
162 #size-cells = <0x1>;
164 ranges = <0x0 0xf 0xf4400000 0x20000>;
[all …]
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| /Documentation/filesystems/ |
| D | qnx6.rst | 8 It got introduced in QNX 6.4.0 and is used default since 6.4.1.
57 If the level value is 0, up to 16 direct blocks can be addressed by each
65 Unused block pointers are always set to ~0 - regardless of root node,
71 The first Superblock is located at 0x2000. (0x2000 is the bootblock size)
72 The Audi MMI 3G first superblock directly starts at byte 0.
76 device address, zeroing the last 3 bytes and then subtracting 0x1000 from
79 0x1000 is the size reserved for each superblock - regardless of the
101 filename inodes start with 0)
118 These got set a filename length field of 0xff in the corresponding directory
160 The first block is block 0, which starts 0x1000 after superblock start.
[all …]
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| /Documentation/powerpc/ |
| D | syscall64-abi.rst | 14 scv 0 instruction is an alternative that may provide better performance,
38 - For the scv 0 instruction, the return value indicates failure if it is
62 | For the scv 0 instruction, differences with the ELF ABI |
97 scv 0 syscalls will always behave as PPC_FEATURE2_HTM_NOSC.
102 the system call type that can be used to distinguish between sc and scv 0
105 If the value of (pt_regs.trap & 0xfff0) is 0xc00 then the system call was
106 performed with the sc instruction, if it is 0x3000 then the system call was
107 performed with the scv 0 instruction.
|
| /Documentation/trace/coresight/ |
| D | coresight-etm4x-reference.rst | 35 ``$> echo 0x012 > mode``
52 - > 0 : Programs up the hardware with the current values held in the driver
55 - = 0 : disable trace hardware.
70 ``$> 0``
103 - 0 for include
106 ``$> echo 0x0000 0x2000 0 > addr_range``
189 ``$> echo 0x4F > addr_exlevel_s_ns``
194 :Trace Registers: ACATR[idx,{1:0}]
215 ``addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00)``
259 ``0x1``
[all …]
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| /Documentation/devicetree/bindings/ |
| D | example-schema.yaml | 244 reg = <0x1000 0x80>,
245 <0x3000 0x80>;
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | ti,pruss.yaml | 36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
155 const: 0
169 const: 0
203 const: 0
294 "^(pru|rtu|txpru)@[0-9a-f]+$":
335 pruss: pruss@0 {
337 reg = <0x0 0x80000>;
[all …]
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