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/Documentation/devicetree/bindings/pci/
D83xx-512x-pci.txt12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
/Documentation/devicetree/bindings/power/reset/
Dqcom,pon.txt30 reg = <0x800>;
31 mode-bootloader = <0x2>;
32 mode-recovery = <0x1>;
36 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
44 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
/Documentation/devicetree/bindings/mips/cavium/
Dcib.txt26 reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */
27 <0x10700 0x0000e100 0x0 0x8>; /* EN */
Ddma-engine.txt19 reg = <0x11800 0x00000100 0x0 0x8>;
20 interrupts = <0 63>;
/Documentation/devicetree/bindings/regulator/
Dti-abb-regulator.txt17 - #address-cells: should be 0
18 - #size-cells: should be 0
32 0-bypass
56 from efuse-address to pick up ABB characteristics. Set to 0 if
60 + efuse maps to RBB mask. Set to 0 to ignore this.
64 Set to 0 to ignore this.
72 #address-cells = <0>;
73 #size-cells = <0>;
74 reg = <0x483072f0 0x8>, <0x48306818 0x4>;
76 ti,tranxdone-status-mask = <0x4000000>;
[all …]
/Documentation/devicetree/bindings/timer/
Darm,arch_timer_mmio.yaml63 '^frame@[0-9a-z]*$':
69 minimum: 0
105 ranges = <0 0xf0001000 0x1000>;
106 reg = <0xf0000000 0x1000>;
109 frame@0 {
110 frame-number = <0>;
111 interrupts = <0 13 0x8>,
112 <0 14 0x8>;
113 reg = <0x0000 0x1000>,
114 <0x1000 0x1000>;
[all …]
/Documentation/devicetree/bindings/powerpc/fsl/
Dmpc5121-psc.txt55 cell-index = <0>;
56 reg = <0x11000 0x100>;
57 interrupts = <40 0x8>;
66 reg = <0x11100 0x100>;
67 interrupts = <40 0x8>;
75 reg = <0x11f00 0x100>;
76 interrupts = <40 0x8>;
/Documentation/devicetree/bindings/mailbox/
Daltera-mailbox.txt18 reg = <0x100 0x8>;
26 reg = <0x200 0x8>;
37 device node and second argument is the channel index. It must be 0 (hardware
44 reg = <0x400 0x10>;
46 mboxes = <&mbox_tx 0>,
47 <&mbox_rx 0>;
/Documentation/devicetree/bindings/net/can/
Dmpc5xxx-mscan.txt41 interrupts = <12 0x8>;
43 reg = <0x1300 0x80>;
48 interrupts = <13 0x8>;
50 reg = <0x1380 0x80>;
/Documentation/input/devices/
Dalps.rst32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
33 00-00-64 if no buttons are pressed. The bits 0-2 of the first byte will be 1s
45 The new ALPS touchpads have an E7 signature of 73-03-50 or 73-03-0A but
94 byte 0: 0 0 YSGN XSGN 1 M R L
109 byte 0: 1 0 0 0 1 x9 x8 x7
110 byte 1: 0 x6 x5 x4 x3 x2 x1 x0
111 byte 2: 0 ? ? l r ? fin ges
112 byte 3: 0 ? ? ? ? y9 y8 y7
113 byte 4: 0 y6 y5 y4 y3 y2 y1 y0
114 byte 5: 0 z6 z5 z4 z3 z2 z1 z0
[all …]
/Documentation/devicetree/bindings/i2c/
Di2c-mpc.txt28 #size-cells = <0>;
30 reg = <0x1740 0x20>;
31 interrupts = <11 0x8>;
38 reg = <0x1760 0x8>;
44 #size-cells = <0>;
46 reg = <0x3d00 0x40>;
47 interrupts = <2 15 0>;
55 #size-cells = <0>;
57 reg = <0x3100 0x100>;
Di2c-ocores.txt16 - #size-cells : should be <0>
43 #size-cells = <0>;
45 reg = <0xa0000000 0x8>;
49 reg-shift = <0>; /* 8 bit registers */
54 reg = <0x60>;
60 #size-cells = <0>;
62 reg = <0xa0000000 0x8>;
67 reg-shift = <0>; /* 8 bit registers */
72 reg = <0x60>;
/Documentation/devicetree/bindings/phy/
Dphy-hi3798cv200-combphy.txt37 reg = <0x8a20000 0x1000>;
40 ranges = <0x0 0x8a20000 0x1000>;
44 reg = <0x850 0x8>;
47 resets = <&crg 0x188 4>;
53 reg = <0x858 0x8>;
56 resets = <&crg 0x188 12>;
57 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
/Documentation/devicetree/bindings/opp/
Dti-omap5-opp-supply.txt42 cpu0: cpu@0 {
55 reg = <0x4a003b20 0x8>;
58 1060000 0x0
59 1160000 0x4
60 1210000 0x8
/Documentation/devicetree/bindings/rng/
Dnuvoton,npcm-rng.txt11 reg = <0xf000b000 0x8>;
/Documentation/devicetree/bindings/watchdog/
Dqca-ar7130-wdt.txt12 reg = <0x18060008 0x8>;
Dmeson-wdt.txt19 reg = <0xc1109900 0x8>;
Dqcom,pm8916-wdt.txt14 pm8916_0: pm8916@0 {
16 reg = <0x0 SPMI_USID>;
20 reg = <0x800>;
24 interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>;
/Documentation/devicetree/bindings/gpio/
D8xxx_gpio.txt48 reg = <0xc00 0x100>;
50 interrupts = <74 0x8>;
59 reg = <0xd00 0x100>;
61 interrupts = <75 0x8>;
67 funkyfpga@0 {
/Documentation/devicetree/bindings/net/
Dbrcm,bcmgenet.txt46 - #size-cells: size of the cells for MDIO bus addressing, should be 0
60 #address-cells = <0x1>;
61 #size-cells = <0x1>;
62 reg = <0xf0b60000 0xfc4c>;
63 interrupts = <0x0 0x14 0x0>, <0x0 0x15 0x0>;
67 #address-cells = <0x1>;
68 #size-cells = <0x0>;
69 reg = <0xe14 0x8>;
73 reg = <0x1>;
83 fixed-link = <1 0 1000 0 0>;
[all …]
Dbrcm,iproc-mdio.txt7 - #address-cells: must be 0
16 reg = <0x18002000 0x8>;
18 #address-cells = <0>;
20 enet-gphy@0 {
21 reg = <0>;
/Documentation/devicetree/bindings/media/i2c/
Dpanasonic,amg88xx.txt4 8x8 10Hz video which consists of thermal datapoints
16 reg = <0x69>;
/Documentation/devicetree/bindings/clock/
Dxgene.txt50 Default is 0.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
53 Default is 0x8.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
56 Default is 0x0.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
65 clocks = <&refclk 0>;
67 reg = <0x0 0x17000100 0x0 0x1000>;
69 type = <0>;
[all …]
/Documentation/devicetree/bindings/arm/socionext/
Dsocionext,uniphier-system-cache.yaml70 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
71 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
73 cache-size = <0x140000>;
83 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
84 interrupts = <0 190 4>, <0 191 4>;
86 cache-size = <0x200000>;
95 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
96 interrupts = <0 174 4>, <0 175 4>;
98 cache-size = <0x200000>;
/Documentation/devicetree/bindings/arm/marvell/
Dmvebu-cpu-config.txt19 reg = <0x21000 0x8>;

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