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| /Documentation/devicetree/bindings/timer/ |
| D | renesas,cmt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
26 - items:
27 - enum:
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
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| D | ti,keystone-timer.txt | 3 This document provides bindings for the 64-bit timer in the KeyStone
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
9 It is global timer is a free running up-counter and can generate interrupt
17 - compatible : should be "ti,keystone-timer".
18 - reg : specifies base physical address and count of the registers.
19 - interrupts : interrupt generated by the timer.
20 - clocks : the clock feeding the timer clock.
25 compatible = "ti,keystone-timer";
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| D | ti,davinci-timer.txt | 3 This document provides bindings for the 64-bit timer in the DaVinci
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
9 The timer is a free running up-counter and can generate interrupts when the
12 Also see ../watchdog/davinci-wdt.txt for timers that are configurable as
17 - compatible : should be "ti,da830-timer".
18 - reg : specifies base physical address and count of the registers.
19 - interrupts : interrupts generated by the timer.
20 - interrupt-names: should be "tint12", "tint34", "cmpint0", "cmpint1",
24 - clocks : the clock feeding the timer clock.
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| /Documentation/devicetree/bindings/mfd/ |
| D | mc13xxx.txt | 4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892"
7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used
8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
12 Sub-nodes:
13 - codec: Contain the Audio Codec node.
14 - adc-port: Contain PMIC SSI port number used for ADC.
15 - dac-port: Contain PMIC SSI port number used for DAC.
16 - leds : Contain the led nodes and initial register values in property
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| /Documentation/admin-guide/ |
| D | highuid.rst | 2 Notes on the change from 16-bit UIDs to 32-bit UIDs
8 - kernel code MUST take into account __kernel_uid_t and __kernel_uid32_t
12 - kernel code should use uid_t and gid_t in kernel-private structures and
15 What's left to be done for 32-bit UIDs on all Linux architectures:
17 - Disk quotas have an interesting limitation that is not related to the
22 properly with huge UIDs. If it can deal with 64-bit file offsets on all
25 - Decide whether or not to keep backwards compatibility with the system
27 (currently, the old 16-bit UID and GID are still written to disk, and
28 part of the former pad space is used to store separate 32-bit UID and
31 - Need to validate that OS emulation calls the 16-bit UID
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| /Documentation/staging/ |
| D | crc32.rst | 5 A CRC is a long-division remainder. You add the CRC to the message,
11 protocols put the end-of-frame flag after the CRC.
15 - We're working in binary, so the digits are only 0 and 1, and
16 - When dividing polynomials, there are no carries. Rather than add and
17 subtract, we just xor. Thus, we tend to get a bit sloppy about
21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
23 CRC is written in hex with the most significant bit omitted. (If you're
24 familiar with the IEEE 754 floating-point format, it's the same idea.)
28 the best error-detecting properties, this should correspond to the
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| /Documentation/devicetree/bindings/dma/ |
| D | st,stm32-mdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
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| D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
17 3. A 32bit mask specifying the DMA channel configuration which are device
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
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| /Documentation/scsi/ |
| D | aic7xxx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 Adaptec Aic7xxx Fast -> Ultra160 Family Manager Set v7.0
26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
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| D | NinjaSCSI.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 WorkBiT NinjaSCSI-3/32Bi driver for Linux
10 This is Workbit corp.'s(http://www.workbit.co.jp/) NinjaSCSI-3
17 :pcmcia-cs: 3.1.27
18 :gcc: gcc-2.95.4
19 :PC card: I-O data PCSC-F (NinjaSCSI-3),
20 I-O data CBSC-II in 16 bit mode (NinjaSCSI-32Bi)
21 :SCSI device: I-O data CDPS-PX24 (CD-ROM drive),
22 Media Intelligent MMO-640GT (Optical disk drive)
27 (a) Check your PC card is true "NinjaSCSI-3" card.
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| /Documentation/filesystems/ext4/ |
| D | blocks.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ------
12 pages). By default a filesystem can contain 2^32 blocks; if the '64bit'
17 For 32-bit filesystems, limits are as follows:
19 .. list-table::
21 :header-rows: 1
23 * - Item
24 - 1KiB
25 - 2KiB
26 - 4KiB
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| D | checksums.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ---------
10 structures did not have space to fit a full 32-bit checksum, so only the
11 lower 16 bits are stored. Enabling the 64bit feature increases the data
12 structure size so that full 32-bit checksums can be stored for many data
13 structures. However, existing 32-bit filesystems cannot be extended to
14 enable 64bit mode, at least not without the experimental resize2fs
18 ``tune2fs -O metadata_csum`` against the underlying device. If tune2fs
20 checksum, it will request that you run ``e2fsck -D`` to have the
30 .. list-table::
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| /Documentation/locking/ |
| D | robust-futex-ABI.rst | 43 consisting of three words. Each word is 32 bits on 32 bit arch's, or 64
44 bits on 64 bit arch's, and local byte order. Each thread should have
47 If a thread is running in 32 bit compatibility mode on a 64 native arch
48 kernel, then it can actually have two such structures - one using 32 bit
49 words for 32 bit compatibility mode, and one using 64 bit words for 64
50 bit native mode. The kernel, if it is a 64 bit kernel supporting 32 bit
63 is always a 32 bit word, unlike the other words above. The 'lock
79 The 'lock word' is always 32 bits, and is intended to be the same 32 bit
89 the kernel will walk this list, mark any such locks with a bit
162 1) if bit 31 (0x80000000) is set in that word, then attempt a futex
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| /Documentation/driver-api/ |
| D | ioctl.rst | 18 the ioctl system call. While this can be any 32-bit number that uniquely
22 ``include/uapi/asm-generic/ioctl.h`` provides four macros for defining
36 An 8-bit number, often a character literal, specific to a subsystem
37 or driver, and listed in :doc:`../userspace-api/ioctl/ioctl-number`
40 An 8-bit number identifying the specific command, unique for a give
45 encodes the ``sizeof(data_type)`` value in a 13-bit or 14-bit integer,
74 handler returns either -ENOTTY or -ENOIOCTLCMD, which also results in
75 -ENOTTY being returned from the system call. Some subsystems return
76 -ENOSYS or -EINVAL here for historic reasons, but this is wrong.
79 -ENOIOCTLCMD in order to use the fallback conversion into native
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| /Documentation/devicetree/bindings/nvmem/ |
| D | brcm,ocotp.txt | 4 - compatible: "brcm,ocotp" for the first generation Broadcom OTPC which is used
5 in Cygnus and supports 32 bit read/write. Use "brcm,ocotp-v2" for the second
7 64-bit read/write.
8 - reg: Base address of the OTP controller.
9 - brcm,ocotp-size: Amount of memory available, in 32 bit words
16 brcm,ocotp-size = <2048>;
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| /Documentation/userspace-api/media/rc/ |
| D | rc-protos.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
20 toggle bit will invert from one IR message to the next.
22 Some remotes have a pointer-type device which can used to control the
29 rc-5 (RC_PROTO_RC5)
30 -------------------
38 .. flat-table:: rc5 bits scancode mapping
41 * - rc-5 bit
43 - scancode bit
45 - description
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| /Documentation/x86/ |
| D | entry_64.rst | 1 .. SPDX-License-Identifier: GPL-2.0
16 for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
17 arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
18 syscall entry points and thus provides for 32-bit processes the
19 ability to execute syscalls when running on 64-bit kernels.
25 - system_call: syscall instruction from 64-bit code.
27 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
30 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
33 - interrupt: An array of entries. Every IDT vector that doesn't
36 magically-generated functions that make their way to do_IRQ with
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| /Documentation/devicetree/bindings/net/can/ |
| D | bosch,m_can.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Sriram Dash <sriram.dash@samsung.com>
20 - description: M_CAN registers map
21 - description: message RAM
23 reg-names:
25 - const: m_can
26 - const: message_ram
30 - description: interrupt line0
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| /Documentation/arm/ |
| D | microchip.rst | 7 ------------
11 It is important to note that the Microchip (previously Atmel) ARM-based MPU
15 git branches/tags and email subject always contain this "at91" sub-string.
19 ---------
25 - at91rm9200
29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-1768-32-bit-ARM920T-Embedded-Microprocessor-…
32 - at91sam9260
36 …ttp://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6221-32-bit-ARM926EJ-S-Embedded-Microprocesso…
38 - at91sam9xe
42 …ttp://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6254-32-bit-ARM926EJ-S-Embedded-Microprocesso…
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| /Documentation/devicetree/bindings/power/reset/ |
| D | syscon-poweroff.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/reset/syscon-poweroff.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
17 Default will be little endian mode, 32 bit access only.
21 const: syscon-poweroff
25 description: Update only the register bits defined by the mask (32 bit).
37 description: The poweroff value written to the poweroff register (32 bit access).
40 - compatible
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| /Documentation/devicetree/bindings/clock/ |
| D | st,stm32-rcc.txt | 6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
19 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
23 - clocks: External oscillator clock phandle
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | firmware.txt | 9 - id: The string name of the firmware. This is taken from the 'id'
13 - extended-modes: The Extended Modes bitfield, taken from the
14 firmware binary. It is a 64-bit number represented
15 as an array of two 32-bit numbers.
16 - virtual-traps: The virtual traps, taken from the firmware binary.
17 It is an array of 8 32-bit numbers.
21 id = "Soft-UART";
22 extended-modes = <0 0>;
23 virtual-traps = <0 0 0 0 0 0 0 0>;
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| /Documentation/core-api/ |
| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
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| /Documentation/process/ |
| D | adding-syscalls.rst | 9 :ref:`Documentation/process/submitting-patches.rst <submittingpatches>`.
13 ------------------------
18 kernel, there are other possibilities -- choose what fits best for your
21 - If the operations involved can be made to look like a filesystem-like
26 - If the new functionality involves operations where the kernel notifies
30 - However, operations that don't map to
31 :manpage:`read(2)`/:manpage:`write(2)`-like operations
35 - If you're just exposing runtime system information, a new node in sysfs
41 - If the operation is specific to a particular file or file descriptor, then
47 - If the operation is specific to a particular task or process, then an
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| /Documentation/devicetree/bindings/pwm/ |
| D | pwm-samsung.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
17 outputs - see SoC and board manual).
24 - samsung,s3c2410-pwm # 16-bit, S3C24xx
25 - samsung,s3c6400-pwm # 32-bit, S3C64xx
26 - samsung,s5p6440-pwm # 32-bit, S5P64x0
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