Searched full:cpuid (Results 1 – 25 of 28) sorted by relevance
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| /Documentation/virt/kvm/ |
| D | cpuid.rst | 4 KVM CPUID bits
10 cpuid. This is not always guaranteed to work, since userspace can
11 mask-out some, or even all KVM-related cpuid features before launching
14 KVM cpuid functions are:
26 The value in eax corresponds to the maximum cpuid function present in this leaf,
30 This function queries the presence of KVM cpuid leafs.
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| D | msr.rst | 56 Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
128 of specific flags has to be checked in 0x40000001 cpuid leaf.
133 | flag bit | cpuid bit | meaning |
144 Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
157 Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
169 Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
174 if (!kvm_para_available()) /* refer to cpuid.txt */
215 present in CPUID. Bit 3 enables interrupt based delivery of 'page ready'
217 CPUID.
247 available if KVM_FEATURE_ASYNC_PF_INT is present in CPUID.
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| D | index.rst | 12 cpuid
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| D | amd-memory-encryption.rst | 15 The hypervisor can determine the SEV support through the CPUID
16 instruction. The CPUID function 0x8000001f reports information related
45 defined in the CPUID 0x8000001f[ecx] field.
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| D | hypercalls.rst | 70 :Purpose: Expose hypercall availability to the guest. On x86 platforms, cpuid
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| D | timekeeping.rst | 348 The presence of this instruction must be determined by consulting CPUID feature
427 dependent and must be determined by inspecting CPUID, chipset or vendor
544 measurement with the TSC, and requires a serializing instruction, such as CPUID
547 Since CPUID may actually be virtualized by a trap and emulate mechanism, this
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| D | api.rst | 677 Defines the vcpu responses to the cpuid instruction. Applications
680 Note, when this IOCTL fails, KVM gives no guarantees that previous valid CPUID
682 resulting CPUID configuration through KVM_GET_CPUID2 in case.
1606 This ioctl returns x86 cpuid features which are supported by both the
1608 information returned by this ioctl to construct cpuid information (for
1611 user may wish to constrain cpuid to emulate older hardware, or for
1615 expose cpuid features (e.g. MONITOR) which are not supported by kvm in
1627 The entries returned are the host cpuid as returned by the cpuid instruction,
1646 the values returned by the cpuid instruction for
1649 The TSC deadline timer feature (CPUID leaf 1, ecx[24]) is always returned
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| /Documentation/x86/ |
| D | cpuinfo.rst | 29 shows features which the kernel supports. For a full list of CPUID flags
35 a: Feature flags can be derived from the contents of CPUID leaves.
37 These feature definitions are organized mirroring the layout of CPUID
45 b: Flags can be from scattered CPUID-based features.
47 Hardware features enumerated in sparsely populated CPUID leaves get
48 software-defined values. Still, CPUID needs to be queried to determine
51 checked at runtime in the respective CPUID leaf [EAX=f, ECX=0] bit EDX[1].
53 The intent of scattering CPUID leaves is to not bloat struct
54 cpuinfo_x86.x86_capability[] unnecessarily. For instance, the CPUID leaf
55 [EAX=7, ECX=0] has 30 features and is dense, but the CPUID leaf [EAX=7, EAX=1]
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| D | amd-memory-encryption.rst | 42 Support for SME and SEV can be determined through the CPUID instruction. The
43 CPUID function 0x8000001f reports information related to SME::
72 CPUID information above) will not conflict with the address space resource
79 The CPU supports SME (determined through CPUID instruction).
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| D | tsx_async_abort.rst | 27 controls the enumeration of the TSX feature bits (RTM and HLE) in CPUID.
44 advertised in CPUID.
47 advertised in CPUID. That is mainly for virtualization
49 hypervisor does not expose MD_CLEAR in CPUID. It's a best
55 status of RTM and MD_CLEAR CPUID bits.
116 (i.e. it will make CPUID(EAX=7).EBX{bit4} and
117 CPUID(EAX=7).EBX{bit11} read as 0).
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| D | mds.rst | 103 MD_CLEAR CPUID bit to guests, the kernel issues the VERW instruction in the
120 advertised in CPUID.
123 advertised in CPUID. That is mainly for virtualization
125 hypervisor does not expose MD_CLEAR in CPUID. It's a best
131 the availability of the MD_CLEAR CPUID bit.
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| D | topology.rst | 52 The number of cores in a package. This information is retrieved via CPUID.
56 The number of dies in a package. This information is retrieved via CPUID.
60 The physical ID of the die. This information is retrieved via CPUID.
64 The physical ID of the package. This information is retrieved via CPUID
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| D | resctrl_ui.rst | 356 is found using CPUID, but is also provided in the "info" directory of
922 static int cpuid = 2;
935 CPU_SET(cpuid, &cpuset);
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| /Documentation/hwmon/ |
| D | fam15h_power.rst | 64 indicated by CPUID Fn8000_0007_EDX[12].
93 i. Determine the ratio of Tsample to Tref by executing CPUID Fn8000_0007.
95 N = value of CPUID Fn8000_0007_ECX[CpuPwrSampleTimeRatio[15:0]].
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| D | coretemp.rst | 9 CPUID: family 0x6, models
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| /Documentation/arm/ |
| D | marvel.rst | 436 CPUID 0x69052xxx
439 CPUID 0x69054xxx
442 CPUID 0x69056xxx or 0x69056xxx
445 CPUID 0x5615331x or 0x41xx926x
448 CPUID 0x5605531x or 0x41xx926x
451 CPUID 0x5615571x
454 CPUID 0x5625131x
457 CPUID 0x561584xx
460 CPUID 0x560f581x
463 CPUID 0x561f581x
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| /Documentation/driver-api/thermal/ |
| D | x86_pkg_temperature_thermal.rst | 9 (Verify using: CPUID.06H:EAX[bit 6] =1)
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| /Documentation/admin-guide/hw-vuln/ |
| D | tsx_async_abort.rst | 115 mitigation mechanism is not advertised via CPUID the kernel selects a best
121 CPUID to the guest. If the host has updated microcode the protection takes
183 and HLE) in CPUID.
232 combinations of CPUID bit MD_CLEAR and IA32_ARCH_CAPABILITIES MSR bits MDS_NO
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| D | mds.rst | 128 mitigation mechanism is not advertised via CPUID the kernel selects a best
134 the CPUID to the guest. If the host has updated microcode the protection
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| D | special-register-buffer-data-sampling.rst | 98 RNGDS_MITG_DIS (bit 0) is enumerated by CPUID.(EAX=07H,ECX=0).EDX[SRBDS_CTRL =
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| /Documentation/virt/kvm/devices/ |
| D | vm.rst | 66 __u64 cpuid; # CPUID of host
85 __u64 cpuid; # CPUID currently (to be) used by this vcpu
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| /Documentation/x86/x86_64/ |
| D | fsgs.rst | 92 The instructions are enumerated in CPUID leaf 7, bit 0 of EBX. If
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| /Documentation/admin-guide/pm/ |
| D | cpufreq_drivers.rst | 30 is detected with the cpuid instruction.
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| D | intel_idle.rst | 137 the ``MWAIT`` support in the processor is enumerated through ``CPUID`` and the
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| /Documentation/devicetree/bindings/arm/ |
| D | cpus.yaml | 52 required and matches the CPUID[11:0] register bits.
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