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/Documentation/devicetree/bindings/edac/
Dsocfpga-eccmgr.txt1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
6 Cyclone5 and Arria5 ECC Manager
8 - compatible : Should be "altr,socfpga-ecc-manager"
15 L2 Cache ECC
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
22 On Chip RAM ECC
24 - compatible : Should be "altr,socfpga-ocram-ecc"
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Daspeed-sdram-edac.txt3 The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error
10 Note, the bootloader must configure ECC mode in the memory controller.
/Documentation/devicetree/bindings/mtd/
Dnand-controller.yaml19 The ECC strength and ECC step size properties define the user
21 they request the ECC engine to correct {strength} bit errors per
49 nand-ecc-mode:
51 Desired ECC engine, either hardware (most of the time
54 and should be replaced by soft and nand-ecc-algo.
58 nand-ecc-engine:
62 A phandle on the hardware ECC engine if any. There are
64 1/ The ECC engine is part of the NAND controller, in this
66 2/ The ECC engine is part of the NAND part (on-die), in this
68 3/ The ECC engine is external, in this case the phandle should
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Dgpmc-nand.txt10 For NAND specific properties such as ECC modes or bus width, please refer to
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
31 "ham1" 1-bit Hamming ecc code
32 "bch4" 4-bit BCH ecc code
33 "bch8" 8-bit BCH ecc code
34 "bch16" 16-bit BCH ECC code
35 Refer below "How to select correct ECC scheme for your device ?"
47 locating ECC errors for BCHx algorithms. SoC devices which have
49 Using ELM for ECC error correction frees some CPU cycles.
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Dmtk-nand.txt5 the nand controller interface driver and the ECC engine driver.
23 - ecc-engine: Required ECC Engine node.
36 ecc-engine = <&bch>;
49 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
50 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
55 - nand-ecc-strength: Number of bits to correct per ECC step.
65 E : nand-ecc-strength.
71 Q : nand-ecc-step-size.
75 this number depends on max ecc step size
77 If max ecc step size supported is 1024,
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Dhisi504-nand.txt11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
20 The following ECC strength and step size are currently supported:
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
34 nand-ecc-mode = "hw";
35 nand-ecc-strength = <16>;
36 nand-ecc-step-size = <1024>;
Dnvidia-tegra20-nand.txt25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
28 Supported values with "hw" ECC mode are: "rs", "bch".
31 - nand-ecc-strength: integer representing the number of bits to correct
32 per ECC step (always 512). Supported strength using HW ECC
36 - nand-ecc-maximize: See nand-controller.yaml
37 - nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
60 nand-ecc-algo = "bch";
61 nand-ecc-strength = <8>;
Ddenali,nand.yaml40 ecc: ECC circuit clock
44 - const: ecc
79 nand-ecc-strength:
83 nand-ecc-step-size:
97 nand-ecc-strength:
102 nand-ecc-step-size:
116 nand-ecc-strength:
120 nand-ecc-step-size:
140 clock-names = "nand", "nand_x", "ecc";
Ddavinci-nand.txt42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
48 - ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
58 - ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
86 nand-ecc-mode = "hw";
87 ti,davinci-ecc-bits = <4>;
Dvf610-nfc.txt17 there might be restrictions on maximum rates when using hardware ECC.
29 - nand-ecc-mode: see nand-controller.yaml
31 Required properties for hardware ECC:
32 - nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml)
33 - nand-ecc-step-size: step size equals page size, currently only 2k pages are
54 nand-ecc-mode = "hw";
55 nand-ecc-strength = <32>;
56 nand-ecc-step-size = <2048>;
Dmarvell-nand.txt47 - nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
48 - nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
49 not using hardware ECC. Howerver, it may be added when using hardware
50 ECC for clarification but will be ignored by the driver because ECC
52 the NAND chip. This value may be overwritten with nand-ecc-strength
54 - nand-ecc-strength: see nand-controller.yaml.
55 - nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
59 patterns described in AN-379, "Marvell SoC NFC ECC".
78 nand-ecc-mode = "hw";
81 nand-ecc-strength = <4>;
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Dtango-nand.txt29 nand-ecc-strength = <14>;
30 nand-ecc-step-size = <1024>;
35 nand-ecc-strength = <14>;
36 nand-ecc-step-size = <1024>;
Datmel-nand.txt6 The NAND controller might be connected to an ECC engine.
27 - ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
53 * ECC engine (PMECC) bindings:
80 pmecc: ecc-engine@ffffc070 {
103 ecc-engine = <&pmecc>;
130 and hardware ECC controller if available.
131 If the hardware ECC is PMECC, it should contain address and size for
145 - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
148 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
150 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
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Dallwinner,sun4i-a10-nand.yaml64 nand-ecc-mode: true
66 nand-ecc-algo:
69 nand-ecc-step-size:
72 nand-ecc-strength:
Dst,stm32-fmc2-nand.yaml29 - description: ecc DMA channel
35 - const: ecc
41 nand-ecc-step-size:
44 nand-ecc-strength:
117 dma-names = "tx", "rx", "ecc";
Dfsmc-nand.txt33 - nand-ecc-mode : see nand-controller.yaml
34 - nand-ecc-strength : see nand-controller.yaml
35 - nand-ecc-step-size : see nand-controller.yaml
37 Can support 1-bit HW ECC (default) or if stronger correction is required,
Dingenic,nand.yaml30 ecc-engine: true
80 ecc-engine = <&bch>;
94 nand-ecc-step-size = <1024>;
95 nand-ecc-strength = <24>;
96 nand-ecc-mode = "hw";
Dbrcm,brcmnand.txt109 - nand-ecc-strength : see nand-controller.yaml
110 - nand-ecc-step-size : must be 512 or 1024. See nand-controller.yaml
114 expected for the ECC layout in use. This size, in
122 number of available options for its default ECC
146 nand-ecc-strength = <12>;
147 nand-ecc-step-size = <512>;
183 nand-ecc-strength = <1>;
184 nand-ecc-step-size = <512>;
Dgpmi-nand.yaml78 fsl,use-minimum-ecc:
81 Protect this NAND flash with the minimum ECC strength required.
82 The required ECC strength is automatically discoverable for some
85 the software may chooses an implementation-defined ECC scheme.
/Documentation/devicetree/bindings/memory-controllers/
Dsynopsys.txt3 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
6 The Zynq DDR ECC controller has an optional ECC support in half-bus width
9 These both ECC controllers correct single bit ECC errors and detect double bit
10 ECC errors.
14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
/Documentation/arm/samsung-s3c24xx/
Dnand.rst11 The driver uses a 512 byte (1 page) ECC code for this setup. The
12 ECC code is not directly compatible with the default kernel ECC
13 code, so the driver enforces its own OOB layout and ECC parameters
19 size, with support for hardware ECC generation and correction.
21 Unlike the 512byte page mode, the driver generates ECC data for
/Documentation/driver-api/
Dmtdnand.rst357 Hardware ECC support
363 The nand driver supports three different types of hardware ECC.
367 Hardware ECC generator providing 3 bytes ECC per 256 byte.
371 Hardware ECC generator providing 3 bytes ECC per 512 byte.
375 Hardware ECC generator providing 6 bytes ECC per 512 byte.
379 Hardware ECC generator providing 8 bytes ECC per 512 byte.
396 Transfer the ECC from the hardware to the buffer. If the option
402 In case of an ECC error this function is called for error detection
409 Hardware ECC with syndrome calculation
412 Many hardware ECC implementations provide Reed-Solomon codes and
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/Documentation/ABI/testing/
Dsysfs-class-mtd123 In the case of ECC NOR, it is the ECC block size.
131 correcting within each region covering an ECC step (see
134 In the case of devices lacking any ECC capability, it is 0.
144 region comprising an ecc step (as reported by the driver) equals
159 more regions comprising an ecc step". The precise definition of
172 This is generally applicable only to NAND flash devices with ECC
173 capability. It is ignored on devices lacking ECC capability;
181 The size of a single region covered by ECC, known as the ECC
182 step. Devices may have several equally sized ECC steps within
186 devices lacking any ECC capability, it is 0.
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/Documentation/devicetree/bindings/arm/calxeda/
Dl2ecc.yaml7 title: Calxeda Highbank L2 cache ECC
10 Binding for the Calxeda Highbank L2 cache controller ECC device.
19 const: "calxeda,hb-sregs-l2-ecc"
39 compatible = "calxeda,hb-sregs-l2-ecc";
/Documentation/devicetree/bindings/reserved-memory/
Dramoops.txt10 as kernel log messages, or for optional ECC error-correction data. The total
30 - ecc-size: enables ECC support and specifies ECC buffer size in bytes
31 (defaults to 0: no ECC)

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