/Documentation/devicetree/bindings/mtd/ |
D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller 5 - "nvidia,tegra20-nand" 11 - nand 15 - nand 18 Individual NAND chips are children of the NAND controller node. Currently 19 only one NAND chip supported. 25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only 27 - nand-ecc-algo: string, algorithm of NAND ECC. 29 - nand-bus-width : See nand-controller.yaml 30 - nand-on-flash-bbt: See nand-controller.yaml [all …]
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D | marvell-nand.txt | 1 Marvell NAND Flash Controller (NFC) 5 * "marvell,armada-8k-nand-controller" 6 * "marvell,armada370-nand-controller" 7 * "marvell,pxa3xx-nand-controller" 8 * "marvell,armada-8k-nand" (deprecated) 9 * "marvell,armada370-nand" (deprecated) 10 * "marvell,pxa3xx-nand" (deprecated) 13 - reg: NAND flash controller memory area. 14 - #address-cells: shall be set to 1. Encode the NAND CS. 16 - interrupts: shall define the NAND controller interrupt. [all …]
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D | denali,nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/denali,nand.yaml# 7 title: Denali NAND controller 15 - altr,socfpga-denali-nand 16 - socionext,uniphier-denali-nand-v5a 17 - socionext,uniphier-denali-nand-v5b 38 nand: controller core clock 42 - const: nand 53 nand: controller core reset 57 - const: nand 59 - const: nand [all …]
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D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC) 3 This variant of the Freescale NAND flash controller (NFC) can be found on 10 - #address-cells: shall be set to 1. Encode the nand CS. 13 - assigned-clock-rates: The NAND bus timing is derived from this clock 14 rate and should not exceed maximum timing for any NAND memory chip 15 in a board stuffing. Typical NAND memory timings derived from this 23 Children nodes represent the available nand chips. Currently the driver can 24 only handle one NAND chip. 28 - nand-bus-width: see nand-controller.yaml 29 - nand-ecc-mode: see nand-controller.yaml [all …]
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D | samsung-s3c2410.txt | 1 * Samsung S3C2410 and compatible NAND flash controller 5 "samsung,s3c2410-nand" 6 "samsung,s3c2412-nand" 7 "samsung,s3c2440-nand" 9 - #address-cells, #size-cells : see nand-controller.yaml 10 - clocks : phandle to the nand controller clock 11 - clock-names : must contain "nand" 14 Child nodes representing the available nand chips. 17 - nand-ecc-mode : see nand-controller.yaml 18 - nand-on-flash-bbt : see nand-controller.yaml [all …]
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D | brcm,brcmnand.txt | 1 * Broadcom STB NAND Controller 3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND 19 the core NAND controller, of the following form: 35 - reg : the register start and length for NAND register region. 37 (optional) NAND flash cache range (if at non-standard offset) 39 ranges. Should contain "nand" and (optionally) 40 "flash-dma" or "flash-edu" and/or "nand-cache". 41 - interrupts : The NAND CTLRDY interrupt, (if Flash DMA is available) 45 May be "nand", if the SoC has the individual NAND 52 - clock : reference to the clock for the NAND controller [all …]
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D | qcom_nandc.txt | 1 * Qualcomm NAND controller 5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x 7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in 9 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in 20 NAND. Refer to dma.txt and qcom_adm.txt for more details 23 number specified for the NAND controller on the given 26 number specified for the NAND controller on the given 31 and the channel number to be used for NAND. Refer to 37 * NAND chip-select 40 chip-selects which (may) contain NAND flash chips. Their properties are as [all …]
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D | hisi504-nand.txt | 1 Hisilicon Hip04 Soc NAND controller DT binding 7 NAND controller's registers. The second contains base 8 physical address and size of NAND controller's buffer. 10 - nand-bus-width: See nand-controller.yaml. 11 - nand-ecc-mode: Support none and hw ecc mode. 17 - nand-ecc-strength: Number of bits to correct per ECC step. 18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step. 22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024> 29 nand: nand@4020000 { 33 nand-bus-width = <8>; [all …]
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D | atmel-nand.txt | 1 Atmel NAND flash controller bindings 3 The NAND flash controller node should be defined under the EBI bus (see 5 One or several NAND devices can be defined under this NAND controller. 6 The NAND controller might be connected to an ECC engine. 8 * NAND controller bindings: 12 "atmel,at91rm9200-nand-controller" 13 "atmel,at91sam9260-nand-controller" 14 "atmel,at91sam9261-nand-controller" 15 "atmel,at91sam9g45-nand-controller" 16 "atmel,sama5d3-nand-controller" [all …]
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D | nand-controller.yaml | 4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml# 7 title: NAND Chip and NAND Controller Generic Binding 14 The NAND controller should be represented with its own DT node, and 15 all NAND chips attached to this controller should be defined as 16 children nodes of the NAND controller. This representation should be 31 pattern: "^nand-controller(@.*)?" 42 "^nand@[a-f0-9]$": 49 nand-ecc-mode: 52 embedded in the NAND controller) or software correction 54 and should be replaced by soft and nand-ecc-algo. [all …]
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D | oxnas-nand.txt | 1 * Oxford Semiconductor OXNAS NAND Controller 3 Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings. 6 - compatible: "oxsemi,ox820-nand" 7 - reg: Base address and length for NAND mapped memory. 10 - clocks: phandle to the NAND gate clock if needed. 11 - resets: phandle to the NAND reset control if needed. 15 nandc: nand-controller@41000000 { 16 compatible = "oxsemi,ox820-nand"; 23 nand@0 { 27 nand-ecc-mode = "soft"; [all …]
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D | fsmc-nand.txt | 2 NAND Interface 5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand" 12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped 13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes 27 NAND flash in response to SMWAITn. Zero means 1 cycle, 32 - bank: default NAND bank to use (0-3 are valid, 0 is the default). 33 - nand-ecc-mode : see nand-controller.yaml 34 - nand-ecc-strength : see nand-controller.yaml 35 - nand-ecc-step-size : see nand-controller.yaml 43 compatible = "st,spear600-fsmc-nand"; [all …]
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D | davinci-nand.txt | 1 Device tree bindings for Texas instruments Davinci/Keystone NAND controller 4 NAND interface contains. 12 - compatible: "ti,davinci-nand" 13 "ti,keystone-nand" 22 for accessing the nand. 29 address for the chip select space the NAND Flash 35 address for the chip select space the NAND Flash 42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode 50 - nand-bus-width: buswidth 8 or 16. If not present 8. 52 - nand-on-flash-bbt: use flash based bad block table support. OOB [all …]
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D | tango-nand.txt | 1 Sigma Designs Tango4 NAND Flash Controller (NFC) 5 - compatible: "sigma,smp8758-nand" 13 Children nodes represent the available NAND chips. 14 See Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings. 18 nandc: nand-controller@2c000 { 19 compatible = "sigma,smp8758-nand"; 27 nand@0 { 29 nand-ecc-strength = <14>; 30 nand-ecc-step-size = <1024>; 33 nand@1 { [all …]
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D | gpmi-nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml# 13 - $ref: "nand-controller.yaml" 16 The GPMI nand controller provides an interface to control the NAND 25 - fsl,imx23-gpmi-nand 26 - fsl,imx28-gpmi-nand 27 - fsl,imx6q-gpmi-nand 28 - fsl,imx6sx-gpmi-nand 29 - fsl,imx7d-gpmi-nand 32 - fsl,imx8mm-gpmi-nand 33 - fsl,imx8mn-gpmi-nand [all …]
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D | mxic-nand.txt | 1 Macronix Raw NAND Controller Device Tree Bindings 5 - compatible: should be "mxic,multi-itfc-v009-nand-controller" 9 - interrupts: interrupt line connected to this raw NAND controller 15 - children nodes represent the available NAND chips. 17 See Documentation/devicetree/bindings/mtd/nand-controller.yaml 22 nand: nand-controller@43c30000 { 23 compatible = "mxic,multi-itfc-v009-nand-controller"; 31 nand@0 { 33 nand-ecc-mode = "soft"; 34 nand-ecc-algo = "bch";
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D | ingenic,nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml# 7 title: Ingenic SoCs NAND controller devicetree bindings 13 - $ref: nand-controller.yaml# 18 - ingenic,jz4740-nand 19 - ingenic,jz4725b-nand 20 - ingenic,jz4780-nand 24 - description: Bank number, offset and size of first attached NAND chip 25 - description: Bank number, offset and size of second attached NAND chip 26 - description: Bank number, offset and size of third attached NAND chip 27 - description: Bank number, offset and size of fourth attached NAND chip [all …]
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D | mtk-nand.txt | 1 MTK SoCs NAND FLASH controller (NFC) DT binding 3 This file documents the device tree bindings for MTK SoCs NAND controllers. 5 the nand controller interface driver and the ECC engine driver. 10 1) NFC NAND Controller Interface (NFI): 13 The first part of NFC is NAND Controller Interface (NFI) HW. 24 - #address-cells: NAND chip index, should be 1. 42 - children nodes: NAND chips. 48 - nand-on-flash-bbt: Store BBT on NAND Flash. 49 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes) 50 - nand-ecc-step-size: Number of data bytes covered by a single ECC step. [all …]
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D | cadence-nand-controller.txt | 1 * Cadence NAND controller 16 - dmas: shall reference DMA channel associated to the NAND controller 24 Child nodes represent the available NAND chips. 26 Required properties of NAND chips: 28 the cadence nand flash controller 30 See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on 35 nand_controller: nand-controller@60000000 { 44 nand@0 { 46 label = "nand-1"; 48 nand@1 { [all …]
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D | allwinner,sun4i-a10-nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml# 7 title: Allwinner A10 NAND Controller Device Tree Bindings 10 - $ref: "nand-controller.yaml" 22 - allwinner,sun4i-a10-nand 23 - allwinner,sun8i-a23-nand-controller 57 "^nand@[a-f0-9]+$": 64 nand-ecc-mode: true 66 nand-ecc-algo: 69 nand-ecc-step-size: 72 nand-ecc-strength:
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D | gpio-control-nand.txt | 1 GPIO assisted NAND flash 3 The GPIO assisted NAND flash uses a memory mapped interface to 4 read/write the NAND commands and data and GPIO pins for the control 8 - compatible : "gpio-control-nand" 10 resource describes the data bus connected to the NAND flash and all accesses 14 - gpios : Specifies the GPIO pins to control the NAND device. The order of 22 - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read 24 the GPIO's and the NAND flash data bus. If present, then after changing 33 gpio-nand@1,0 { 34 compatible = "gpio-control-nand";
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D | mxc-nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/mxc-nand.yaml# 13 - $ref: "nand-controller.yaml" 17 const: fsl,imx27-nand 34 nand-controller@d8000000 { 37 compatible = "fsl,imx27-nand"; 40 nand-bus-width = <8>; 41 nand-ecc-mode = "hw";
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/Documentation/devicetree/bindings/pinctrl/ |
D | lantiq,pinctrl-xway.txt | 51 ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3, 62 ebu clk, ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, 63 nand rd, spi, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, 83 ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1, 94 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd, 106 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd, 120 exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle, 121 nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5, 122 nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
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D | marvell,kirkwood-pinctrl.txt | 24 mpp0 0 gpio, nand(io2), spi(cs) 25 mpp1 1 gpo, nand(io3), spi(mosi) 26 mpp2 2 gpo, nand(io4), spi(sck) 27 mpp3 3 gpo, nand(io5), spi(miso) 28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk) 29 mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig) 45 mpp18 18 gpo, nand(io0) 46 mpp19 19 gpo, nand(io1) 62 mpp0 0 gpio, nand(io2), spi(cs) 63 mpp1 1 gpo, nand(io3), spi(mosi) [all …]
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/Documentation/devicetree/bindings/gpio/ |
D | ni,169445-nand-gpio.txt | 1 Bindings for the National Instruments 169445 GPIO NAND controller 3 The 169445 GPIO NAND controller has two memory mapped GPIO registers, one 5 intended to be used with the GPIO NAND driver. 8 - compatible: should be "ni,169445-nand-gpio" 23 gpio1: nand-gpio-out@1f300010 { 24 compatible = "ni,169445-nand-gpio"; 31 gpio2: nand-gpio-in@1f300014 { 32 compatible = "ni,169445-nand-gpio";
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