Searched +full:non +full:- +full:secure (Results 1 – 25 of 68) sorted by relevance
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| /Documentation/devicetree/bindings/nvmem/ |
| D | st,stm32-romem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data bindings
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@st.com>
19 - $ref: "nvmem.yaml#"
24 - st,stm32f4-otp
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| D | snvs-lpgpr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/snvs-lpgpr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Low Power General Purpose Register found in i.MX Secure Non-Volatile Storage
10 - Oleksij Rempel <o.rempel@pengutronix.de>
15 - fsl,imx6q-snvs-lpgpr
16 - fsl,imx6ul-snvs-lpgpr
17 - fsl,imx7d-snvs-lpgpr
20 - compatible
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| /Documentation/devicetree/bindings/arm/ |
| D | secure.txt | 1 * ARM Secure world bindings
4 "Normal" and "Secure". Most devicetree consumers (including the Linux
6 world or the Secure world. However some devicetree consumers are
8 visible only in the Secure address space, only in the Normal address
10 virtual machine which boots Secure firmware and wants to tell the
13 The general principle of the naming scheme for Secure world bindings
14 is that any property that needs a different value in the Secure world
15 can be supported by prefixing the property name with "secure-". So for
16 instance "secure-foo" would override "foo". For property names with
17 a vendor prefix, the Secure variant of "vendor,foo" would be
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| D | juno,scpi.txt | 5 ------------------------------------
8 - compatible : should be "arm,juno-sram-ns" for Non-secure SRAM
10 Each sub-node represents the reserved area for SCPI.
12 Required sub-node properties:
13 - reg : The base offset and size of the reserved area with the SRAM
14 - compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
18 --------------------------------------------------------------
20 - compatible : should be "arm,scpi-sensors".
21 - #thermal-sensor-cells: should be set to 1.
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| D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3 # Only for s/w models
24 - arm,arm1136-pmu
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| /Documentation/devicetree/bindings/iommu/ |
| D | qcom,iommu.txt | 3 Qualcomm "B" family devices which are not compatible with arm-smmu have
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
16 - clock-names : Should be a pair of "iface" (required for IOMMUs
20 - clocks : Phandles for respective clocks described by
21 clock-names.
23 - #address-cells : must be 1.
25 - #size-cells : must be 1.
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| D | msm,iommu-v0.txt | 5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
13 secure mode, in that order. For instances that don't support secure mode a
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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| D | arm,smmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
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| D | renesas,ipmmu-vmsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas VMSA-Compatible IOMMU
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 connected to the IPMMU through a port called micro-TLB.
20 - items:
21 - enum:
22 - renesas,ipmmu-r8a73a4 # R-Mobile APE6
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| /Documentation/devicetree/bindings/arm/samsung/ |
| D | samsung-secure-firmware.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/samsung/samsung-secure-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos Secure Firmware
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - const: samsung,secure-firmware
19 Address of non-secure SYSRAM used for communication with firmware.
23 - compatible
24 - reg
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| /Documentation/devicetree/bindings/misc/ |
| D | brcm,kona-smc.txt | 1 Broadcom Secure Monitor Bounce buffer
2 -----------------------------------------------------
4 used for non-secure to secure communications.
7 - compatible : "brcm,kona-smc"
8 - DEPRECATED: compatible : "bcm,kona-smc"
9 - reg : Location and size of bounce buffer
13 compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
|
| /Documentation/devicetree/bindings/soc/rockchip/ |
| D | grf.txt | 7 - GRF, used for general non-secure system,
8 - SGRF, used for general secure system,
9 - PMUGRF, used for always on system
14 - GRF, used for general non-secure system,
15 - SGRF, used for general secure system,
16 - DETECTGRF, used for audio codec system,
17 - COREGRF, used for pvtm,
21 - compatible: GRF should be one of the following:
22 - "rockchip,px30-grf", "syscon": for px30
23 - "rockchip,rk3036-grf", "syscon": for rk3036
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| /Documentation/devicetree/bindings/mailbox/ |
| D | arm,mhu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jassi Brar <jaswinder.singh@linaro.org>
13 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
19 be a 'Secure' resource, hence can't be used by Linux running NS.
22 interrupt signal using a 32-bit register, with all 32-bits logically ORed
28 interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
37 - arm,mhu
38 - arm,mhu-doorbell
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| /Documentation/devicetree/bindings/clock/ |
| D | fujitsu,mb86s70-crg11.txt | 2 -----------------------------------
5 - compatible : Shall contain "fujitsu,mb86s70-crg11"
6 - #clock-cells : Shall be 3 {cntrlr domain port}
13 compatible = "fujitsu,mb86s70-crg11";
14 #clock-cells = <3>;
18 #mbox-cells = <1>;
21 interrupts = <0 36 4>, /* LP Non-Sec */
22 <0 35 4>, /* HP Non-Sec */
23 <0 37 4>; /* Secure */
25 clock-names = "clk";
|
| /Documentation/virt/kvm/ |
| D | s390-pv-boot.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 -------
13 :doc:`s390-pv` for details."
20 to the Ultravisor (UV) and instruct it to secure the memory of the
33 -------
46 The new PV load-device-specific-parameters field specifies all data
52 * AES-XTS Tweak prefix
63 contain the guest content. All non-specified pages will start out as
72 UV will clear all memory when a secure VM is removed, and therefore
73 non-clearing IPL subcodes are not allowed.
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| D | s390-pv.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 -------
15 Each guest starts in non-protected mode and then may make a request to
20 The Ultravisor will secure and decrypt the guest's boot memory
33 -------------------
54 -------------------------------
64 ---------------------
70 The control structures associated with SIE provide the Secure
72 Secure Interception General Register Save Area. Guest GRs and most of
75 GRs are put into / retrieved from the Secure Interception General
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| /Documentation/arm/samsung/ |
| D | bootloader-interface.rst | 14 In the document "boot loader" means any of following: U-boot, proprietary
19 1. Non-Secure mode
37 2. Secure mode
65 3. Other (regardless of secure/non-secure mode)
72 0x0908 Non-zero Secondary CPU boot up indicator
79 AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other
81 MCPM - Multi-Cluster Power Management
|
| /Documentation/ABI/testing/ |
| D | sysfs-platform-mellanox-bootctl | 6 The Life-cycle state of the SoC, which could be one of the
10 Production Production state and can be updated to secure
11 GA Secured Secure chip and not able to change state
12 GA Non-Secured Non-Secure chip and not able to change state
|
| /Documentation/powerpc/ |
| D | ultravisor.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 POWER 9 that enables Secure Virtual Machines (SVMs). DD2.3 chips
16 (PVR=0x004e1203) or greater will be PEF-capable. A new ISA release
25 +------------------+
29 +------------------+
31 +------------------+
33 +------------------+
35 +------------------+
56 process is running in secure mode, MSR(S) bit 41. MSR(S)=1, process
57 is in secure mode, MSR(s)=0 process is in normal mode.
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| /Documentation/arm64/ |
| D | booting.rst | 13 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
14 counterpart. EL2 is the hypervisor level and exists only in non-secure
15 mode. EL3 is the highest priority level and exists only in secure mode.
19 is passed to the Linux kernel. This may include secure monitor and
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
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| /Documentation/arm/ |
| D | firmware.rst | 2 Interface for registering and calling firmware-specific operations for ARM
7 Some boards are running with secure firmware running in TrustZone secure
18 The ops pointer must be non-NULL. More information about struct firmware_ops
27 ((firmware_ops->op) ? firmware_ops->op(__VA_ARGS__) : (-ENOSYS))
30 -ENOSYS to signal that given operation is not available (for example, to allow
69 if (call_firmware_op(cpu_boot, cpu) == -ENOSYS)
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | marvell,icu.txt | 2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
28 - #interrupt-cells: Specifies the number of cells needed to encode an
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - enum:
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| /Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
20 to sample CPU program counter, secure state and exception level, etc; usually
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
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| /Documentation/devicetree/bindings/sram/ |
| D | sram.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
19 Following the generic-names recommended practice, node names should
30 - mmio-sram
31 - atmel,sama5d2-securam
32 - rockchip,rk3288-pmu-sram
42 "#address-cells":
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