Searched full:bank (Results 1 – 25 of 146) sorted by relevance
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-st.txt | 14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
28 [irqN]----> [gpio-bank (n)]
37 bank are capable of retiming. Retiming is mainly used to improve the
39 - ranges : defines mapping between pin controller node (parent) to gpio-bank
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| D | pinctrl-sirf.txt | 10 - sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m
11 - sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m
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| D | allwinner,sun4i-a10-pinctrl.yaml | 18 bank, then the pin number inside that bank, and finally the GPIO
25 of the bank, then the pin number inside that bank, and finally
66 One interrupt per external interrupt bank supported on the
67 controller, sorted by bank number ascending order.
91 bank found in the controller
103 # - Then, the bank name is optional and will be between pa and pg,
144 # FIXME: We should have the pin bank supplies here, but not a lot of
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| D | rockchip,pinctrl.txt | 53 - compatible: "rockchip,gpio-bank"
54 - reg: register of the gpio bank (different than the iomux registerset)
55 - interrupts: base interrupt of the gpio bank in the interrupt controller
56 - clocks: clock that drives this bank
57 - gpio-controller: identifies the node as a gpio controller and pin bank.
93 compatible = "rockchip,gpio-bank";
155 compatible = "rockchip,gpio-bank";
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| D | samsung-pinctrl.txt | 48 nodes of the controller node. Bank name is taken from name of the node. Each
49 bank node must contain following properties:
51 - gpio-controller: identifies the node as a gpio controller and pin bank.
81 an example, the pins in GPA0 bank of the pin controller can be represented
84 "[pin bank name]-[pin number within the bank]".
93 function selector register of the pin-bank.
130 In addition, following properties must be present in node of every bank
170 In addition, following properties must be present in node of every bank
184 Node of every bank of pins supporting direct wake-up interrupts (without
188 wakeup interrupts from pins of the bank, must contain interrupts for all
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| D | atmel,at91-pinctrl.txt | 23 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
24 configured in this periph mode. All the periph and bank need to be describe.
29 Each line will represent a pio bank
33 Bank: 3 (A, B and C)
41 For each peripheral/bank we will describe in a u32 if a pin can be
120 For each bank the required properties are:
131 - clocks: bank clock
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| /Documentation/hwmon/ |
| D | abituguru-datasheet.rst | 60 level we will call banks. A bank holds data for one or more sensors. The data
61 in a bank for a sensor is one or more bytes large.
63 The number of bytes is fixed for a given bank, you should always read or write
65 less then the number of bytes for a given bank are undetermined.
67 See below for all known bank addresses, numbers of sensors in that bank,
71 terminology for the addressing within a bank this is not 100% correct, in
72 bank 0x24 for example the addressing within the bank selects a PWM output not
76 uGuru determines if a read from or a write to the bank is taking place, thus
97 not yet reported 0x08 at DATA and you proceed with writing a bank address.
100 Sending bank and sensor addresses to the uGuru
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| D | w83795.rst | 75 41 FANCTL1 10h (bank 2) pwm1
76 43 FANCTL2 11h (bank 2) pwm2
77 45 FANCTL3 12h (bank 2) pwm3
78 47 FANCTL4 13h (bank 2) pwm4
79 49 FANCTL5 14h (bank 2) pwm5
80 51 FANCTL6 15h (bank 2) pwm6
81 53 FANCTL7 16h (bank 2) pwm7
82 55 FANCTL8 17h (bank 2) pwm8
131 33 FANCTL1 10h (bank 2) pwm1
132 35 FANCTL2 11h (bank 2) pwm2
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | gpio.txt | 10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
29 compatible = "fsl,cpm1-pario-bank-a";
36 compatible = "fsl,cpm1-pario-bank-b";
43 compatible = "fsl,cpm1-pario-bank-c";
53 compatible = "fsl,cpm1-pario-bank-e";
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | par_io.txt | 26 the new device trees. Instead, each Par I/O bank should be represented
31 - compatible : should be "fsl,<chip>-qe-pario-bank",
32 "fsl,mpc8323-qe-pario-bank".
39 compatible = "fsl,mpc8360-qe-pario-bank",
40 "fsl,mpc8323-qe-pario-bank";
47 compatible = "fsl,mpc8360-qe-pario-bank",
48 "fsl,mpc8323-qe-pario-bank";
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | exynos-srom.yaml | 32 Reflects the memory layout with four integer values per bank. Format:
33 <bank-number> 0 <parent address of bank> <size>
43 of the relevant SROM bank.
48 Bank number, base address (relative to start of the bank) and size
50 typically 0 as this is the start of the bank.
70 Array of 6 integers, specifying bank timings in the following order:
100 // Example: SROMc with SMSC911x ethernet chip on bank 3
114 reg = <3 0 0x10000>; // Bank 3, offset = 0
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| /Documentation/devicetree/bindings/bus/ |
| D | socionext,uniphier-system-bus.yaml | 16 within each bank to the CPU-viewed address. The needed setup includes the
17 base address, the size of each bank. Optionally, some timing parameters can
32 The first cell is the bank number (chip select).
33 The second cell is the address offset within the bank.
53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | brcm,bcm2835-armctrl-ic.txt | 21 The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
25 The 2nd cell contains the interrupt number within the bank. Valid values
26 are 0..7 for bank 0, and 0..31 for bank 1.
34 Bank 0:
44 Bank 1:
78 Bank 2:
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| /Documentation/devicetree/bindings/net/ |
| D | cavium-mix.txt | 10 bank contains the MIX registers. The second bank the corresponding
11 AGL registers. The third bank are the AGL registers shared by all
12 MIX devices present. The fourth bank is the AGL_PRT_CTL shared by
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-lm3697.txt | 21 - reg : 0 - LED is Controlled by bank A
22 1 - LED is Controlled by bank B
24 control bank. This is a zero based property so
39 HVLED string 1 and 3 are controlled by control bank A and HVLED 2 string is
40 controlled by control bank B.
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| /Documentation/devicetree/bindings/mtd/ |
| D | fsmc-nand.txt | 10 - bank-width : Width (in bytes) of the device. If not present, the width
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
52 bank-width = <1>;
55 bank = <1>;
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| D | mtd-physmap.txt | 12 - bank-width : Width (in bytes) of the bank. Equal to the
15 omitted, assumed to be equal to 'bank-width'.
61 bank-width = <4>;
84 bank-width = <2>;
96 bank-width = <2>;
108 bank-width = <2>;
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| D | ibm,ndfc.txt | 9 - bank-settings : NDFC bank configuration register value (default 0).
20 bank-settings = <0x80002222>;
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | ciu.txt | 10 - reg: The base address of the CIU's register bank.
12 - #interrupt-cells: Must be <2>. The first cell is the bank within
14 within the bank and may have a value between 0 and 63.
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| D | ciu2.txt | 10 - reg: The base address of the CIU's register bank.
12 - #interrupt-cells: Must be <2>. The first cell is the bank within
14 the bit within the bank and may also have a value between 0 and 63.
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| /Documentation/devicetree/bindings/gpio/ |
| D | brcm,brcmstb-gpio.txt | 4 registers with each set controlling a bank of up to 32 pins. A single
24 - brcm,gpio-bank-widths:
25 Number of GPIO lines for each bank. Number of elements must
67 brcm,gpio-bank-widths = <32 32 32 24>;
82 brcm,gpio-bank-widths = <18 4>;
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| D | gpio-nmk.txt | 17 - gpio-bank : Specifies which bank a controller owns.
30 gpio-bank = <1>;
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| D | brcm,kona-gpio.txt | 8 support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
17 interrupt per GPIO bank. The number of interrupts listed depends on the
18 number of GPIO banks on the SoC. The interrupts must be ordered by bank,
19 starting with bank 0. There is always a 1:1 mapping between banks and
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| /Documentation/devicetree/bindings/iommu/ |
| D | qcom,iommu.txt | 27 - #iommu-cells : Must be 1. Index identifies the context-bank #.
33 - List of sub-nodes, one per translation context bank. Each sub-node
37 - "qcom,msm-iommu-v1-ns" : non-secure context bank
38 - "qcom,msm-iommu-v1-sec" : secure context bank
39 - reg : Base address and size of context bank within the iommu
46 for routing of context bank irq's to secure vs non-
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| /Documentation/sh/ |
| D | register-banks.rst | 4 Notes on register bank usage in the kernel
11 bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families
18 r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc
20 when in the context of another bank. The developer must keep the SR.RB value
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