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/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mssr.yaml4 $id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
18 - The CPG block generates various core clocks,
27 - renesas,r7s9210-cpg-mssr # RZ/A2
28 - renesas,r8a7742-cpg-mssr # RZ/G1H
29 - renesas,r8a7743-cpg-mssr # RZ/G1M
30 - renesas,r8a7744-cpg-mssr # RZ/G1N
31 - renesas,r8a7745-cpg-mssr # RZ/G1E
32 - renesas,r8a77470-cpg-mssr # RZ/G1C
33 - renesas,r8a774a1-cpg-mssr # RZ/G2M
[all …]
Drenesas,cpg-clocks.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
7 title: Renesas Clock Pulse Generator (CPG)
13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
16 The CPG may also provide a Clock Domain for SoC devices, in combination with
17 the CPG Module Stop (MSTP) Clocks.
22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
23 - const: renesas,r8a7740-cpg-clocks # R-Mobile A1
24 - const: renesas,r8a7778-cpg-clocks # R-Car M1
25 - const: renesas,r8a7779-cpg-clocks # R-Car H1
28 - renesas,r7s72100-cpg-clocks # RZ/A1H
[all …]
Drenesas,cpg-div6-clock.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
7 title: Renesas CPG DIV6 Clock
13 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
14 Generator (CPG). Their clock input is divided by a configurable factor from 1
24 - const: renesas,cpg-div6-clock
55 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
Drenesas,cpg-mstp-clocks.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
30 - const: renesas,cpg-mstp-clocks
68 "renesas,cpg-mstp-clocks";
Drenesas,rcar-usb2-clock-sel.txt61 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
66 resets = <&cpg 703>, <&cpg 704>;
/Documentation/devicetree/bindings/media/
Drenesas,vsp1.yaml68 #include <dt-bindings/clock/renesas-cpg-mssr.h>
76 clocks = <&cpg CPG_MOD 131>;
78 resets = <&cpg 131>;
83 #include <dt-bindings/clock/renesas-cpg-mssr.h>
91 clocks = <&cpg CPG_MOD 624>;
93 resets = <&cpg 624>;
Drenesas,fcp.yaml55 #include <dt-bindings/clock/renesas-cpg-mssr.h>
61 clocks = <&cpg CPG_MOD 602>;
63 resets = <&cpg 602>;
Drenesas,fdp1.yaml56 #include <dt-bindings/clock/renesas-cpg-mssr.h>
64 clocks = <&cpg CPG_MOD 119>;
66 resets = <&cpg 119>;
Drenesas,vin.yaml316 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
325 clocks = <&cpg CPG_MOD 810>;
327 resets = <&cpg 810>;
339 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
347 clocks = <&cpg CPG_MOD 811>;
349 resets = <&cpg 811>;
376 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
384 clocks = <&cpg CPG_MOD 809>;
386 resets = <&cpg 809>;
/Documentation/devicetree/bindings/mmc/
Drenesas,sdhi.yaml142 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
150 clocks = <&cpg CPG_MOD 314>;
155 resets = <&cpg 314>;
162 clocks = <&cpg CPG_MOD 313>;
167 resets = <&cpg 313>;
174 clocks = <&cpg CPG_MOD 312>;
179 resets = <&cpg 312>;
186 clocks = <&cpg CPG_MOD 311>;
191 resets = <&cpg 311>;
/Documentation/devicetree/bindings/display/bridge/
Drenesas,lvds.yaml157 #include <dt-bindings/clock/renesas-cpg-mssr.h>
163 clocks = <&cpg CPG_MOD 727>;
165 resets = <&cpg 727>;
187 #include <dt-bindings/clock/renesas-cpg-mssr.h>
193 clocks = <&cpg CPG_MOD 727>,
198 resets = <&cpg 727>;
224 clocks = <&cpg CPG_MOD 727>,
229 resets = <&cpg 726>;
/Documentation/devicetree/bindings/phy/
Drcar-gen2-phy.txt63 clocks = <&cpg CPG_MOD 704>;
66 resets = <&cpg 704>;
86 clocks = <&cpg CPG_MOD 704>;
89 resets = <&cpg 704>;
103 clocks = <&cpg CPG_MOD 706>;
106 resets = <&cpg 706>;
Drcar-gen3-phy-pcie.txt21 clocks = <&cpg CPG_MOD 319>;
23 resets = <&cpg 319>;
/Documentation/devicetree/bindings/display/
Drenesas,cmm.yaml57 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
65 clocks = <&cpg CPG_MOD 711>;
66 resets = <&cpg 711>;
Drenesas,du.txt108 clocks = <&cpg CPG_MOD 724>,
109 <&cpg CPG_MOD 723>,
110 <&cpg CPG_MOD 722>,
111 <&cpg CPG_MOD 721>;
113 resets = <&cpg 724>, <&cpg 722>;
/Documentation/devicetree/bindings/ata/
Drenesas,rcar-sata.yaml61 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
69 clocks = <&cpg CPG_MOD 815>;
71 resets = <&cpg 815>;
/Documentation/devicetree/bindings/pci/
Drcar-pci-ep.yaml66 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
78 resets = <&cpg 319>;
80 clocks = <&cpg CPG_MOD 319>;
/Documentation/devicetree/bindings/usb/
Drenesas,usb-xhci.yaml76 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
84 clocks = <&cpg CPG_MOD 328>;
86 resets = <&cpg 328>;
/Documentation/devicetree/bindings/pwm/
Drenesas,pwm-rcar.yaml69 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
75 clocks = <&cpg CPG_MOD 523>;
77 resets = <&cpg 523>;
/Documentation/devicetree/bindings/thermal/
Drcar-gen3-thermal.yaml68 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
80 clocks = <&cpg CPG_MOD 522>;
82 resets = <&cpg 522>;
/Documentation/devicetree/bindings/memory-controllers/
Drenesas,rpc-if.yaml68 #include <dt-bindings/clock/renesas-cpg-mssr.h>
77 clocks = <&cpg CPG_MOD 917>;
79 resets = <&cpg 917>;
/Documentation/devicetree/bindings/serial/
Drenesas,scifa.yaml92 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
104 clocks = <&cpg CPG_MOD 204>;
107 resets = <&cpg 204>;
Drenesas,hscif.yaml119 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
131 clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>,
137 resets = <&cpg 519>;
/Documentation/devicetree/bindings/net/can/
Drcar_canfd.txt63 clocks = <&cpg CPG_MOD 914>,
64 <&cpg CPG_CORE R8A7795_CLK_CANFD>,
67 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
69 power-domains = <&cpg>;
/Documentation/devicetree/bindings/dma/
Drenesas,usb-dmac.yaml89 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
99 clocks = <&cpg CPG_MOD 330>;
101 resets = <&cpg 330>;

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