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/Documentation/devicetree/bindings/dma/xilinx/
Dzynqmp_dma.txt1 Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
3 control and rate control support for slave/peripheral dma access.
6 - compatible : Should be "xlnx,zynqmp-dma-1.0"
7 - reg : Memory map for gdma/adma module access.
8 - interrupts : Should contain DMA channel interrupt.
9 - xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64
10 - clock-names : List of input clocks "clk_main", "clk_apb"
14 - dma-coherent : Present if dma operations are coherent.
18 fpd_dma_chan1: dma@fd500000 {
19 compatible = "xlnx,zynqmp-dma-1.0";
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/Documentation/devicetree/bindings/dma/
Dapm-xgene-dma.txt1 Applied Micro X-Gene SoC DMA nodes
3 DMA nodes are defined to describe on-chip DMA interfaces in
4 APM X-Gene SoC.
6 Required properties for DMA interfaces:
7 - compatible: Should be "apm,xgene-dma".
8 - device_type: set to "dma".
9 - reg: Address and length of the register set for the device.
11 1st - DMA control and status register address space.
12 2nd - Descriptor ring control and status register address space.
13 3rd - Descriptor ring command register address space.
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Darm-pl330.txt1 * ARM PrimeCell PL330 DMA Controller
3 The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
7 - compatible: should include both "arm,pl330" and "arm,primecell".
8 - reg: physical base address of the controller and length of memory mapped
10 - interrupts: interrupt number to the cpu.
13 - dma-coherent : Present if dma operations are coherent
14 - #dma-cells: must be <1>. used to represent the number of integer
16 - dma-channels: contains the total number of DMA channels supported by the DMAC
17 - dma-requests: contains the total number of DMA requests supported by the DMAC
18 - arm,pl330-broken-no-flushp: quirk for avoiding to execute DMAFLUSHP
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Dmv-xor-v2.txt4 - compatible: one of the following values:
5 "marvell,armada-7k-xor"
6 "marvell,xor-v2"
7 - reg: Should contain registers location and length (two sets)
8 the first set is the DMA registers
10 - msi-parent: Phandle to the MSI-capable interrupt controller used for
14 - clocks: Optional reference to the clocks used by the XOR engine.
15 - clock-names: mandatory if there is a second clock, in this case the
23 compatible = "marvell,xor-v2";
26 msi-parent = <&gic_v2m0>;
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/Documentation/devicetree/bindings/crypto/
Dti,sa2ul.yaml1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <t-kristo@ti.com>
15 - ti,j721e-sa2ul
16 - ti,am654-sa2ul
21 power-domains:
26 - description: TX DMA Channel
27 - description: RX DMA Channel #1
28 - description: RX DMA Channel #2
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Damd-ccp.txt4 - compatible: Should be "amd,ccp-seattle-v1a"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain the CCP interrupt
9 - dma-coherent: Present if dma operations are coherent
13 compatible = "amd,ccp-seattle-v1a";
15 interrupt-parent = <&gic>;
Darm-cryptocell.txt4 - compatible: Should be one of -
5 "arm,cryptocell-713-ree"
6 "arm,cryptocell-703-ree"
7 "arm,cryptocell-712-ree"
8 "arm,cryptocell-710-ree"
9 "arm,cryptocell-630p-ree"
10 - reg: Base physical address of the engine and length of memory mapped region.
11 - interrupts: Interrupt number for the device.
14 - clocks: Reference to the crypto engine clock.
15 - dma-coherent: Present if dma operations are coherent.
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Dhisilicon,hip07-sec.txt4 - compatible: Must contain one of
5 - "hisilicon,hip06-sec"
6 - "hisilicon,hip07-sec"
7 - reg: Memory addresses and lengths of the memory regions through which
11 Regions 2-18 have registers for the 16 individual queues which are isolated
13 - interrupts: Interrupt specifiers.
14 Refer to interrupt-controller/interrupts.txt for generic interrupt client node
19 - dma-coherent: The driver assumes coherent dma is possible.
22 - iommus: The SEC units are behind smmu-v3 iommus.
23 Refer to iommu/arm,smmu-v3.txt for more information.
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/Documentation/devicetree/bindings/ata/
Dahci-fsl-qoriq.txt4 - reg: Physical base address and size of the controller's register area.
5 - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
7 - clocks: Input clock specifier. Refer to common clock bindings.
8 - interrupts: Interrupt specifier. Refer to interrupt binding.
11 - dma-coherent: Enable AHCI coherent DMA operation.
12 - reg-names: register area names when there are more than 1 register area.
16 compatible = "fsl,ls1021a-ahci";
20 dma-coherent;
Dapm-xgene.txt1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
19 - interrupts : Interrupt-specifier for SATA host controller IRQ.
20 - clocks : Reference to the clock entry.
21 - phys : A list of phandles + phy-specifiers, one for each
22 entry in phy-names.
23 - phy-names : Should contain:
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Dahci-platform.txt3 SATA nodes are defined to describe on-chip Serial ATA controllers.
6 It is possible, but not required, to represent each port as a sub-node.
11 - compatible : compatible string, one of:
12 - "brcm,iproc-ahci"
13 - "hisilicon,hisi-ahci"
14 - "cavium,octeon-7130-ahci"
15 - "ibm,476gtr-ahci"
16 - "marvell,armada-380-ahci"
17 - "marvell,armada-3700-ahci"
18 - "snps,dwc-ahci"
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Dsata_highbank.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-ahci
27 dma-coherent: true
29 calxeda,pre-clocks:
35 calxeda,post-clocks:
41 calxeda,led-order:
43 $ref: /schemas/types.yaml#/definitions/uint32-array
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/Documentation/devicetree/bindings/xillybus/
Dxillybus.txt4 - compatible: Should be "xillybus,xillybus-1.00.a"
5 - reg: Address and length of the register set for the device
6 - interrupts: Contains one interrupt node, typically consisting of three cells.
9 - dma-coherent: Present if DMA operations are coherent
14 compatible = "xillybus,xillybus-1.00.a";
17 interrupt-parent = <&intc>;
/Documentation/devicetree/bindings/pci/
Dhisilicon-pcie.txt6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
12 - reg: Should contain rc_dbi, config registers location and length.
13 - reg-names: Must include the following entries:
16 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
17 - port-id: Should be 0, 1, 2 or 3.
20 - status: Either "ok" or "disabled".
21 - dma-coherent: Present if DMA operations are coherent.
25 compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
27 reg-names = "rc_dbi", "config";
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Dxgene-pci.txt1 * AppliedMicro X-Gene PCIe interface
4 - device_type: set to "pci"
5 - compatible: should contain "apm,xgene-pcie" to identify the core.
6 - reg: A list of physical base address and length for each set of controller
7 registers. Must contain an entry for each entry in the reg-names
9 - reg-names: Must include the following entries:
12 - #address-cells: set to <3>
13 - #size-cells: set to <2>
14 - ranges: ranges for the outbound memory, I/O regions.
15 - dma-ranges: ranges for the inbound memory regions.
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Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-ep.yaml#"
19 - ti,j721e-pcie-ep
24 reg-names:
26 - const: intd_cfg
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Dti,j721e-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-host.yaml#"
19 - ti,j721e-pcie-host
24 reg-names:
26 - const: intd_cfg
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Dlayerscape-pcie-gen4.txt4 the common properties defined in mobiveil-pcie.txt.
7 - compatible: should contain the platform identifier such as:
8 "fsl,lx2160a-pcie"
9 - reg: base addresses and lengths of the PCIe controller register blocks.
12 - interrupts: A list of interrupt outputs of the controller. Must contain an
13 entry for each entry in the interrupt-names property.
14 - interrupt-names: It could include the following entries:
17 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
19 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
20 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
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/Documentation/driver-api/usb/
Ddma.rst1 USB DMA
5 over how DMA may be used to perform I/O operations. The APIs are detailed
11 The big picture is that USB drivers can continue to ignore most DMA issues,
12 though they still must provide DMA-ready buffers (see
13 :doc:`/core-api/dma-api-howto`). That's how they've worked through
14 the 2.4 (and earlier) kernels, or they can now be DMA-aware.
16 DMA-aware usb drivers:
18 - New calls enable DMA-aware drivers, letting them allocate dma buffers and
19 manage dma mappings for existing dma-ready buffers (see below).
21 - URBs have an additional "transfer_dma" field, as well as a transfer_flags
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/Documentation/devicetree/bindings/display/hisilicon/
Dhisi-ade.txt1 Device-Tree bindings for hisilicon ADE display controller driver
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
20 - assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
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/Documentation/devicetree/bindings/iommu/
Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
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/Documentation/devicetree/bindings/mailbox/
Dbrcm,iproc-flexrm-mbox.txt6 FlexRM driver will create a mailbox-controller instance for given FlexRM
10 --------------------
11 - compatible: Should be "brcm,iproc-flexrm-mbox"
12 - reg: Specifies base physical address and size of the FlexRM
14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
17 Refer devicetree/bindings/interrupt-controller/msi.txt
18 - #mbox-cells: Specifies the number of cells needed to encode a mailbox
35 --------------------
36 - dma-coherent: Present if DMA operations made by the FlexRM engine (such
37 as DMA descriptor access, access to buffers pointed by DMA
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/Documentation/devicetree/bindings/infiniband/
Dhisilicon-hns-roce.txt10 - compatible: Should contain "hisilicon,hns-roce-v1".
11 - reg: Physical base address of the RoCE driver and
13 - eth-handle: phandle, specifies a reference to a node
15 - dsaf-handle: phandle, specifies a reference to a node
17 - node_guid: a number that uniquely identifies a device or component
18 - #address-cells: must be 2
19 - #size-cells: must be 2
21 - dma-coherent: Present if DMA operations are coherent.
22 - interrupts: should contain 32 completion event irq,1 async event irq
24 - interrupt-names:should be one of 34 irqs for roce device
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/Documentation/devicetree/bindings/net/
Damd-xgbe.txt1 * AMD 10GbE driver (amd-xgbe)
4 - compatible: Should be "amd,xgbe-seattle-v1a"
5 - reg: Address and length of the register sets for the device
6 - MAC registers
7 - PCS registers
8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
11 - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
13 amd,per-channel-interrupt property is specified, then one additional
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/Documentation/core-api/
Ddma-api.rst2 Dynamic DMA mapping using the generic device
7 This document describes the DMA API. For a more gentle introduction
8 of the API (and actual examples), see :doc:`/core-api/dma-api-howto`.
11 Part II describes extensions for supporting non-consistent memory
13 non-consistent platforms (this is usually only legacy platforms) you
16 Part I - dma_API
17 ----------------
19 To get the dma_API, you must #include <linux/dma-mapping.h>. This
22 A dma_addr_t can hold any valid DMA address for the platform. It can be
23 given to a device to use as a DMA source or target. A CPU cannot reference
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