Searched +full:ethernet +full:- +full:switch (Results 1 – 25 of 88) sorted by relevance
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | dsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet Switch Device Tree Bindings
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vivien Didelot <vivien.didelot@gmail.com>
15 This binding represents Ethernet Switches which have a dedicated CPU
16 port. That port is usually connected to an Ethernet Controller of the
23 pattern: "^switch(@.*)?$"
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| D | vitesse,vsc73xx.txt | 4 This defines device tree bindings for the Vitesse VSC73xx switch chips.
8 The currently supported switch chips are:
9 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
10 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
11 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
12 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
14 This switch could have two different management interface.
17 reside inside a SPI bus device tree node, see spi/spi-bus.txt
19 When the chip is connected to a parallel memory bus and work in memory-mapped
25 - compatible: must be exactly one of:
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| D | b53.txt | 1 Broadcom BCM53xx Ethernet switches
6 - compatible: For external switch chips, compatible string must be exactly one
18 "brcm,bcm11360-srab" and the mandatory "brcm,cygnus-srab" string
20 For the BCM5310x SoCs with an integrated switch, must be one of:
21 "brcm,bcm53010-srab"
22 "brcm,bcm53011-srab"
23 "brcm,bcm53012-srab"
24 "brcm,bcm53018-srab"
25 "brcm,bcm53019-srab" and the mandatory "brcm,bcm5301x-srab" string
27 For the BCM5831X/BCM1140x SoCs with an integrated switch, must be one of:
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| D | ocelot.txt | 1 Microchip Ocelot switch driver family
5 -----
9 - VSC9959 (Felix)
10 - VSC9953 (Seville)
12 The VSC9959 switch is found in the NXP LS1028A. It is a PCI device, part of the
13 larger ENETC root complex. As a result, the ethernet-switch node is a sub-node
18 in this case for the Ethernet L2Switch it is PF5 (of device 0, bus 0).
25 For the external switch ports, depending on board configuration, "phy-mode" and
26 "phy-handle" are populated by board specific device tree instances. Ports 4 and
29 The CPU port property ("ethernet") configures the feature called "NPI port" in
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| D | lan9303.txt | 1 SMSC/MicroChip LAN9303 three port ethernet switch
2 -------------------------------------------------
6 - compatible: should be
7 - "smsc,lan9303-i2c" for I2C managed mode
9 - "smsc,lan9303-mdio" for mdio managed mode
13 - reset-gpios: GPIO to be used to reset the whole device
14 - reset-duration: reset duration in milliseconds, defaults to 200 ms
18 The integrated switch subnode should be specified according to the binding
19 described in dsa/dsa.txt. The CPU port of this switch is always port 0.
23 auto-detected and mapped accordingly.
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| D | mt7530.txt | 1 Mediatek MT7530 Ethernet switch
6 - compatible: may be compatible = "mediatek,mt7530"
9 - #address-cells: Must be 1.
10 - #size-cells: Must be 0.
11 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12 on multi-chip module belong to MT7623A has or the remotely standalone
17 - core-supply: Phandle to the regulator node necessary for the core power.
18 - io-supply: Phandle to the regulator node necessary for the I/O power.
19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
24 - reset-gpios: Should be a gpio specifier for a reset line.
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| D | ar9331.txt | 1 Atheros AR9331 built-in switch
4 It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal
5 MDIO bus. All PHYs are built-in as well.
9 - compatible: should be: "qca,ar9331-switch"
10 - reg: Address on the MII bus for the switch.
11 - resets : Must contain an entry for each entry in reset-names.
12 - reset-names : Must include the following entries: "switch"
13 - interrupt-parent: Phandle to the parent interrupt controller
14 - interrupts: IRQ line for the switch
15 - interrupt-controller: Indicates the switch is itself an interrupt
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| D | lantiq-gswip.txt | 1 Lantiq GSWIP Ethernet switches
6 - compatible : "lantiq,xrx200-gswip" for the embedded GSWIP in the
8 - reg : memory range of the GSWIP core registers
17 - compatible : "lantiq,xrx200-mdio" for the MDIO bus inside the GSWIP
25 - compatible : "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw"
26 "lantiq,xrx300-gphy-fw", "lantiq,gphy-fw"
27 "lantiq,xrx330-gphy-fw", "lantiq,gphy-fw"
30 - lantiq,rcu : reference to the rcu syscon
35 - reg : Offset of the GPHY firmware register in the RCU
37 - resets : list of resets of the embedded GPHY
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| D | ksz.txt | 1 Microchip KSZ Series Ethernet switches
6 - compatible: For external switch chips, compatible string must be exactly one
8 - "microchip,ksz8765"
9 - "microchip,ksz8794"
10 - "microchip,ksz8795"
11 - "microchip,ksz9477"
12 - "microchip,ksz9897"
13 - "microchip,ksz9896"
14 - "microchip,ksz9567"
15 - "microchip,ksz8565"
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| /Documentation/networking/dsa/ |
| D | dsa.rst | 5 This document describes the **Distributed Switch Architecture (DSA)** subsystem
13 The Distributed Switch Architecture is a subsystem which was primarily designed
14 to support Marvell Ethernet switches (MV88E6xxx, a.k.a Linkstreet product line)
19 they configured/queried a switch port network device or a regular network
22 An Ethernet switch is typically comprised of multiple front-panel ports, and one
24 presence of a management port connected to an Ethernet controller capable of
25 receiving Ethernet frames from the switch. This is a very common setup for all
26 kinds of Ethernet switches found in Small Home and Office products: routers,
27 gateways, or even top-of-the rack switches. This host Ethernet controller will
32 using upstream and downstream Ethernet links between switches. These specific
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| D | bcm_sf2.rst | 2 Broadcom Starfighter 2 Ethernet switch driver
5 Broadcom's Starfighter 2 Ethernet switch hardware block is commonly found and
8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
12 The switch is typically deployed in a configuration involving between 5 to 13
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
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| D | configuration.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 DSA switch configuration from userspace
7 The DSA switch configuration is not integrated into the main userspace
10 .. _dsa-config-showcases:
13 -----------------------
15 To configure a DSA switch a couple of commands need to be executed. In this
19 Every switch port acts as a different configurable Ethernet port
22 Every switch port is part of one configurable Ethernet bridge
25 Every switch port except one upstream port is part of a configurable
26 Ethernet bridge.
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| D | lan9303.rst | 2 LAN9303 Ethernet switch driver
5 The LAN9303 is a three port 10/100 Mbps ethernet switch with integrated phys for
6 the two external ethernet ports. The third port is an RMII/MII interface to a
36 - Support for VLAN filtering is not implemented
37 - The HW does not support VLAN-specific fdb entries
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| /Documentation/devicetree/bindings/net/ |
| D | ti,cpsw-switch.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI SoC Ethernet Switch Controller (CPSW) Device Tree Bindings
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
15 communication and can be configured as an ethernet switch. It provides the
24 - const: ti,cpsw-switch
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| D | keystone-netcp.txt | 5 Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsystem with a ethernet
6 switch sub-module to send and receive packets. NetCP also includes a packet
12 Keystone II SoC's also have a 10 Gigabit Ethernet Subsystem (XGbE) which
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
14 per Ethernet port.
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
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| D | mscc-ocelot.txt | 1 Microsemi Ocelot network Switch
4 The Microsemi Ocelot network switch can be found on Microsemi SoCs (VSC7513,
8 - compatible: Should be "mscc,vsc7514-switch"
9 - reg: Must contain an (offset, length) pair of the register set for each
10 entry in reg-names.
11 - reg-names: Must include the following entries:
12 - "sys"
13 - "rew"
14 - "qs"
15 - "ptp" (optional due to backward compatibility)
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| D | hisilicon-hns-nic.txt | 4 - compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2".
5 "hisilicon,hns-nic-v1" is for hip05.
6 "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612.
7 - ae-handle: accelerator engine handle for hns,
9 see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
10 - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
16 In NIC mode of DSAF, all 6 PHYs are taken as ethernet ports to the CPU. The
17 port-id can be 2 to 7. Here is the diagram:
18 +-----+---------------+
20 +-+-+-+---+-+-+-+-+-+-+
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| D | mdio-mux.txt | 1 Common MDIO bus multiplexer/switch properties.
3 An MDIO bus multiplexer/switch will have several child busses that are
5 bus multiplexer/switch will have one child node for each child bus.
8 - #address-cells = <1>;
9 - #size-cells = <0>;
12 - mdio-parent-bus : phandle to the parent MDIO bus.
14 - Other properties specific to the multiplexer/switch hardware.
17 - #address-cells = <1>;
18 - #size-cells = <0>;
19 - reg : The sub-bus number.
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| D | ralink,rt2880-net.txt | 1 Ralink Frame Engine Ethernet controller
4 The Ralink frame engine ethernet controller can be found on Ralink and
8 directly and/or via a (gigabit-)switch.
10 * Ethernet controller node
13 - compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth",
14 "ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth",
15 "mediatek,mt7620-eth", "mediatek,mt7621-eth"
16 - reg: Address and length of the register set for the device
17 - interrupts: Should contain the frame engines interrupt
18 - resets: Should contain the frame engines resets
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| D | ralink,rt3050-esw.txt | 1 Ralink Fast Ethernet Embedded Switch
4 The ralink fast ethernet embedded switch can be found on Ralink and Mediatek
8 - compatible: Should be "ralink,rt3050-esw"
9 - reg: Address and length of the register set for the device
10 - interrupts: Should contain the embedded switches interrupt
11 - resets: Should contain the embedded switches resets
12 - reset-names: Should contain the reset names "esw"
15 - ralink,portmap: can be used to choose if the default switch setup is
17 - ralink,led_polarity: override the active high/low settings of the leds
22 compatible = "ralink,rt3050-esw";
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| D | micrel-ks8995.txt | 1 Micrel KS8995 SPI controlled Ethernet Switch families
3 Required properties (according to spi-bus.txt):
4 - compatible: either "micrel,ks8995", "micrel,ksz8864" or "micrel,ksz8795"
7 - reset-gpios : phandle of gpio that will be used to reset chip during probe
11 spi-master {
13 switch@0 {
17 spi-max-frequency = <50000000>;
18 reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
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| D | xilinx_gmii2rgmii.txt | 2 --------------------------------------------------------
5 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
6 Ethernet physical media devices (PHY) and the Gigabit Ethernet controller.
9 Speed of operation. This core can switch dynamically between the three
12 This converter sits between the ethernet MAC and the external phy.
18 - compatible : Should be "xlnx,gmii-to-rgmii-1.0"
19 - reg : The ID number for the phy, usually a small integer
20 - phy-handle : Should point to the external phy device.
21 See ethernet.txt file in the same directory.
25 #address-cells = <1>;
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| D | mdio-mux-gpio.txt | 1 Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
8 - compatible : mdio-mux-gpio.
9 - gpios : GPIO specifiers for each GPIO line. One or more must be specified.
16 compatible = "cavium,octeon-3860-mdio";
17 #address-cells = <1>;
18 #size-cells = <0>;
23 An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
27 mdio-mux {
28 compatible = "mdio-mux-gpio";
30 mdio-parent-bus = <&smi1>;
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| /Documentation/infiniband/ |
| D | opa_vnic.rst | 2 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC)
5 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC) feature
6 supports Ethernet functionality over Omni-Path fabric by encapsulating
7 the Ethernet packets between HFI nodes.
11 The patterns of exchanges of Omni-Path encapsulated Ethernet packets
12 involves one or more virtual Ethernet switches overlaid on the Omni-Path
13 fabric topology. A subset of HFI nodes on the Omni-Path fabric are
14 permitted to exchange encapsulated Ethernet packets across a particular
15 virtual Ethernet switch. The virtual Ethernet switches are logical
18 nodes across the fabric exchange encapsulated Ethernet packets over a
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-ocelot-serdes.txt | 2 -------------------------------------
5 space for setting up the SerDes to switch port muxing.
7 A SerDes X can be "muxed" to work with switch port Y or Z for example.
10 Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
13 half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports
14 10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode.
19 This is a child of the HSIO syscon ("mscc,ocelot-hsio", see
24 - compatible: should be "mscc,vsc7514-serdes"
25 - #phy-cells : from the generic phy bindings, must be 2.
28 defined in dt-bindings/phy/phy-ocelot-serdes.h
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