| /Documentation/admin-guide/pm/ |
| D | cpuidle.rst | 8 CPU Idle Time Management
21 memory or executed. Those states are the *idle* states of the processor.
23 Since part of the processor hardware is not used in idle states, entering them
27 CPU idle time management is an energy-efficiency feature concerned about using
28 the idle states of processors for this purpose.
33 CPU idle time management operates on CPUs as seen by the *CPU scheduler* (that
44 enter an idle state, that applies to the processor as a whole.
52 enter an idle state, that applies to the core that asked for it in the first
56 except for one have been put into idle states at the "core level" and the
57 remaining core asks the processor to enter an idle state, that may trigger it
[all …]
|
| D | intel_idle.rst | 5 ``intel_idle`` CPU Idle Time Management Driver
17 :doc:`CPU idle time management subsystem <cpuidle>` in the Linux kernel
18 (``CPUIdle``). It is the default CPU idle time management driver for the
27 logical CPU executing it is idle and so it may be possible to put some of the
42 .. _intel-idle-enumeration-of-states:
44 Enumeration of Idle States
50 as C-states (in the ACPI terminology) or idle states. The list of meaningful
51 ``MWAIT`` hint values and idle states (i.e. low-power configurations of the
55 In order to create a list of available idle states required by the ``CPUIdle``
56 subsystem (see :ref:`idle-states-representation` in :doc:`cpuidle`),
[all …]
|
| D | suspend-flows.rst | 27 significant differences between the :ref:`suspend-to-idle <s2idle>` code flows
42 Suspend-to-idle Suspend Code Flow
46 state to the :ref:`suspend-to-idle <s2idle>` sleep state:
101 When all devices have been suspended, CPUs enter the idle loop and are put
102 into the deepest available idle state. While doing that, each of them
106 The last CPU to enter the idle state also stops the timekeeping which
109 That allows the CPUs to stay in the deep idle state relatively long in one
113 interrupts. If that happens, they go back to the idle state unless the
120 Suspend-to-idle Resume Code Flow
124 :ref:`suspend-to-idle <s2idle>` sleep state into the working state:
[all …]
|
| /Documentation/devicetree/bindings/powerpc/opal/ |
| D | power-mgt.txt | 5 idle states. The description of these idle states is exposed via the
10 Typically each idle state has the following associated properties:
12 - name: The name of the idle state as defined by the firmware.
14 - flags: indicating some aspects of this idle states such as the
16 idle states and so on. The flag bits are as follows:
19 CPU from idle to running.
22 this idle state in order to accrue power-savings
27 The following properties provide details about the idle states. These
29 provides the value of that property for the idle state associated with
32 If idle-states are defined, then the properties
[all …]
|
| /Documentation/devicetree/bindings/arm/ |
| D | idle-states.yaml | 4 $id: http://devicetree.org/schemas/arm/idle-states.yaml#
7 title: ARM idle states binding description
20 range of dynamic idle states that a processor can enter at run-time, can be
22 enter/exit specific idle states on a given processor.
35 PM implementation to put the processor in different idle states (which include
36 states listed above; "off" state is not an idle state since it does not have
39 Idle state parameters (e.g. entry latency) are platform specific and need to
43 The device tree binding definition for ARM idle states is the subject of this
47 2 - idle-states definitions
50 Idle states are characterized for a specific system through a set of
[all …]
|
| D | psci.yaml | 100 idle state nodes with entry-method property is set to "psci", as per
103 [1] Kernel documentation - ARM idle states bindings
104 Documentation/devicetree/bindings/arm/idle-states.yaml
117 For these cases, the definitions of the idle states for the CPUs and the
118 CPU topology, must conform to the binding in [3]. The idle states
128 [4] Documentation/devicetree/bindings/power/domain-idle-state.yaml
192 // Case 4: CPUs and CPU idle states described using the hierarchical model.
216 idle-states {
219 compatible = "arm,idle-state";
227 domain-idle-states {
[all …]
|
| /Documentation/driver-api/thermal/ |
| D | intel_powerclamp.rst | 15 - Idle Injection
44 idle injection across all online CPU threads was introduced. The goal
55 Idle Injection
68 If the kernel can also inject idle time to the system, then a
71 control system, where the target set point is a user-selected idle
73 between the actual package level C-state residency ratio and the target idle
81 thread synchronizes its idle time and duration, based on the rounding
89 Alignment of idle time around jiffies ensures scalability for HZ
92 kidle_inject/cpu. During idle injection, it runs monitor/mwait idle
96 The NOHZ schedule tick is disabled during idle time, but interrupts
[all …]
|
| D | cpu-idle-cooling.rst | 4 CPU Idle Cooling
37 decrease. Acting on the idle state duration or the idle cycle
47 At a specific OPP, we can assume that injecting idle cycle on all CPUs
49 idle state target residency, we lead to dropping the static and the
51 this state). So the sustainable power with idle cycles has a linear
57 Idle Injection:
60 The base concept of the idle injection is to force the CPU to go to an
61 idle state for a specified time each control cycle, it provides
64 their idle cycles synchronously, the cluster can reach its power down
66 to almost zero. However, these idle cycles injection will add extra
[all …]
|
| /Documentation/devicetree/bindings/power/ |
| D | domain-idle-state.yaml | 4 $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
7 title: PM Domain Idle States binding description
13 A domain idle state node represents the state parameters that will be used to
18 const: domain-idle-states
24 Each state node represents a domain idle state description.
28 const: domain-idle-state
32 The worst case latency in microseconds required to enter the idle
38 The worst case latency in microseconds required to exit the idle
43 The minimum residency duration in microseconds after which the idle
45 entering the idle state.
[all …]
|
| D | power-domain.yaml | 30 domain-idle-states:
33 Phandles of idle states that defines the available states for the
34 power-domain provider. The idle state definitions are compatible with the
35 domain-idle-state bindings, specified in ./domain-idle-state.yaml.
37 Note that, the domain-idle-state property reflects the idle states of this
38 PM domain and not the idle states of the devices or sub-domains in the PM
39 domain. Devices and sub-domains have their own idle states independent of
40 the parent domain's idle states. In the absence of this property, the
108 domain-idle-states = <&DOMAIN_RET>, <&DOMAIN_PWR_DN>;
116 domain-idle-states = <&DOMAIN_PWR_DN>;
[all …]
|
| /Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 1 QCOM Idle States for cpuidle driver
3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
5 states. Idle states have different enter/exit latency and residency values.
6 The idle states supported by the QCOM SoC are defined as -
18 hierarchy to enter standby states, when all cpus are idle. An interrupt brings
34 between the time it enters idle and the next known wake up. SPC mode is used
37 sequence for this idle state is programmed to power down the supply to the
58 The idle-state for QCOM SoCs are distinguished by the compatible property of
59 the idle-states device node.
[all …]
|
| /Documentation/driver-api/pm/ |
| D | cpuidle.rst | 5 CPU Idle Time Management
13 CPU Idle Time Management Subsystem
18 cores) is idle after an interrupt or equivalent wakeup event, which means that
19 there are no tasks to run on it except for the special "idle" task associated
21 belongs to. That can be done by making the idle logical CPU stop fetching
23 depended on by it into an idle state in which they will draw less power.
25 However, there may be multiple different idle states that can be used in such a
28 particular idle state. That is the role of the CPU idle time management
35 units: *governors* responsible for selecting idle states to ask the processor
40 CPU Idle Time Governors
[all …]
|
| /Documentation/devicetree/bindings/thermal/ |
| D | thermal-idle.yaml | 5 $id: http://devicetree.org/schemas/thermal/thermal-idle.yaml#
8 title: Thermal idle cooling device binding
14 The thermal idle cooling device allows the system to passively
15 mitigate the temperature on the device by injecting idle cycles,
18 This binding describes the thermal idle node.
22 const: thermal-idle
24 A thermal-idle node describes the idle cooling device properties to
36 The idle duration in microsecond the device should cool down.
40 The exit latency constraint in microsecond for the injected idle state
42 idle state from among all the present ones.
[all …]
|
| /Documentation/admin-guide/mm/ |
| D | idle_page_tracking.rst | 4 Idle Page Tracking
10 The idle page tracking feature allows to track which memory pages are being
11 accessed by a workload and which are idle. This information can be useful for
23 The idle page tracking API is located at ``/sys/kernel/mm/page_idle``.
30 set, the corresponding page is idle.
32 A page is considered idle if it has not been accessed since it was marked idle
35 To mark a page idle one has to set the bit corresponding to
41 page types (e.g. SLAB pages) an attempt to mark a page idle is silently ignored,
42 and hence such pages are never reported idle.
44 For huge pages the idle flag is set only on the head page, so one has to read
[all …]
|
| /Documentation/timers/ |
| D | no_hz.rst | 19 2. Omit scheduling-clock ticks on idle CPUs (CONFIG_NO_HZ_IDLE=y or
23 3. Omit scheduling-clock ticks on CPUs that are either idle or that
40 that use short bursts of CPU, where there are very frequent idle
41 periods, but where these idle periods are also quite short (tens or
46 other than increasing the overhead of switching to and from idle and
52 However, if you are instead running a light workload with long idle
65 Omit Scheduling-Clock Ticks For Idle CPUs
68 If a CPU is idle, there is little point in sending it a scheduling-clock
71 and an idle CPU has no duties to shift its attention among.
74 scheduling-clock interrupts to idle CPUs, which is critically important
[all …]
|
| /Documentation/scheduler/ |
| D | sched-stats.rst | 50 4) # of times schedule() left the processor idle
76 of idleness (idle, busy, and newly idle):
79 cpu was idle
81 the load did not require balancing when the cpu was idle
83 more tasks and failed, when the cpu was idle
85 load_balance() in this domain when the cpu was idle
87 was idle
89 the target task was cache-hot when idle
91 not find a busier queue while the cpu was idle
93 cpu was idle but no busier group was found
[all …]
|
| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-mux-pinctrl.txt | 39 The only exception is that no bus will be created for a state named "idle". If
43 pinctrl-names = "ddc", "pta", "idle" -> ddc = bus 0, pta = bus 1
44 pinctrl-names = "ddc", "idle", "pta" -> Invalid ("idle" not last)
45 pinctrl-names = "idle", "ddc", "pta" -> Invalid ("idle" not last)
50 If an idle state is defined, whenever an access is not being made to a device
51 on a child bus, the idle pinctrl state will be programmed into hardware.
53 If an idle state is not defined, the most recently used pinctrl state will be
66 pinctrl-names = "ddc", "pta", "idle";
|
| D | i2c-mux-reg.txt | 23 - idle-state: value to set the muxer to when idle. When no value is
29 If an idle state is defined, using the idle-state (optional) property,
31 register will be set according to the idle value.
33 If an idle state is not defined, the most recently used value will be
|
| /Documentation/devicetree/bindings/mfd/ |
| D | twl4030-power.txt | 11 "ti,twl4030-power-idle"
12 "ti,twl4030-power-idle-osc-off"
17 When using ti,twl4030-power-idle, the TI recommended configuration
18 for idle modes is loaded to the tlw4030 PMIC.
20 When using ti,twl4030-power-idle-osc-off, the TI recommended
22 down during off-idle. Note that this does not work on all boards
|
| /Documentation/devicetree/bindings/watchdog/ |
| D | atmel-sama5d4-wdt.txt | 15 - atmel,idle-halt: present if you want to stop the watchdog when the CPU is
16 in idle state.
18 watchdog not counting when the CPU is in idle state, therefore the
20 if the CPU stop working while it is in idle state, which is probably
33 atmel,idle-halt;
|
| D | atmel-wdt.txt | 28 - atmel,idle-halt : Should be present if you want to stop the watchdog when
29 entering idle state.
31 watchdog not counting when the CPU is in idle state, therefore the
33 if the CPU stop working while it is in idle state, which is probably
48 atmel,idle-halt;
|
| /Documentation/devicetree/bindings/mux/ |
| D | mux-controller.txt | 127 have when it is idle. The idle-state property is used for this. If the
128 idle-state is not present, the mux controller is typically left as is when
129 it is idle. For multiplexer chips that expose several mux controllers, the
130 idle-state property is an array with one idle state for each mux controller.
133 as is when it is idle. This is the default, but can still be useful for
135 there is a need to "step past" a mux controller and set some other idle
139 multiplexer. Using this disconnected high-impedance state as the idle state
140 is indicated with idle state (-2).
156 idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 2>;
|
| D | adi,adg792a.txt | 18 - idle-state : if present, array of states that the mux controllers will have
19 when idle. The special state MUX_IDLE_AS_IS is the default and
28 * Mux 0 is disconnected when idle, mux 1 idles in the previously
37 idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 1>;
63 idle-state = <1>;
|
| D | adi,adgs1408.txt | 18 - idle-state : if present, the state that the mux controller will have
19 when idle. The special state MUX_IDLE_AS_IS is the default and
29 * Mux state set to idle as is (no idle-state declared)
|
| /Documentation/trace/ |
| D | events-nmi.rst | 41 …<idle>-0 [000] d.h3 505.397558: nmi_handler: perf_event_nmi_handler() delta_ns: 3236765 hand…
42 …<idle>-0 [000] d.h3 505.805893: nmi_handler: perf_event_nmi_handler() delta_ns: 3174234 hand…
43 …<idle>-0 [000] d.h3 506.158206: nmi_handler: perf_event_nmi_handler() delta_ns: 3084642 hand…
44 …<idle>-0 [000] d.h3 506.334346: nmi_handler: perf_event_nmi_handler() delta_ns: 3080351 hand…
|