Searched +full:max +full:- +full:link +full:- +full:speed (Results 1 – 25 of 34) sorted by relevance
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| /Documentation/devicetree/bindings/pci/ |
| D | ti,j721e-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-ep.yaml#"
19 - ti,j721e-pcie-ep
24 reg-names:
26 - const: intd_cfg
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| D | ti,j721e-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-host.yaml#"
19 - ti,j721e-pcie-host
24 reg-names:
26 - const: intd_cfg
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| D | intel-gw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
16 const: intel,lgm-pcie
18 - compatible
23 - const: intel,lgm-pcie
24 - const: snps,dw-pcie
29 "#address-cells":
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| D | pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/pci-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 - Kishon Vijay Abraham I <kishon@ti.com>
17 pattern: "^pcie-ep@"
19 max-functions:
26 max-link-speed:
30 num-lanes:
38 - compatible
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| D | pci.txt | 3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
21 - max-link-speed:
22 If present this property specifies PCI gen for link capability. Host
24 unsupported link speed, for instance, trying to do training for
25 unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
27 - reset-gpios:
30 - supports-clkreq:
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| D | aardvark-pci.txt | 8 - compatible: Should be "marvell,armada-3700-pcie"
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
11 - #address-cells: set to <3>
12 - #size-cells: set to <2>
13 - device_type: set to "pci"
14 - ranges: ranges for the PCI memory and I/O regions
15 - #interrupt-cells: set to <1>
16 - msi-controller: indicates that the PCIe controller can itself
18 - msi-parent: pointer to the MSI controller to be used
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| D | fsl,imx6q-pcie.txt | 4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible:
8 - "fsl,imx6q-pcie"
9 - "fsl,imx6sx-pcie",
10 - "fsl,imx6qp-pcie"
11 - "fsl,imx7d-pcie"
12 - "fsl,imx8mq-pcie"
13 - reg: base address and length of the PCIe controller
14 - interrupts: A list of interrupt outputs of the controller. Must contain an
15 entry for each entry in the interrupt-names property.
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| D | nvidia,tegra194-pcie.txt | 4 and thus inherits all the common properties defined in designware-pcie.txt.
9 - power-domains: A phandle to the node that controls power to the respective
19 "include/dt-bindings/power/tegra194-powergate.h" file.
20 - reg: A list of physical base address and length pairs for each set of
21 controller registers. Must contain an entry for each entry in the reg-names
23 - reg-names: Must include the following entries:
25 "config": As per the definition in designware-pcie.txt
31 - interrupts: A list of interrupt outputs of the controller. Must contain an
32 entry for each entry in the interrupt-names property.
33 - interrupt-names: Must include the following entries:
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | ksz.txt | 6 - compatible: For external switch chips, compatible string must be exactly one
8 - "microchip,ksz8765"
9 - "microchip,ksz8794"
10 - "microchip,ksz8795"
11 - "microchip,ksz9477"
12 - "microchip,ksz9897"
13 - "microchip,ksz9896"
14 - "microchip,ksz9567"
15 - "microchip,ksz8565"
16 - "microchip,ksz9893"
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| D | vitesse,vsc73xx.txt | 9 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
10 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
11 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
12 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
17 reside inside a SPI bus device tree node, see spi/spi-bus.txt
19 When the chip is connected to a parallel memory bus and work in memory-mapped
25 - compatible: must be exactly one of:
30 - gpio-controller: indicates that this switch is also a GPIO controller,
32 - #gpio-cells: this must be set to <2> and indicates that we are a twocell
37 - reset-gpios: a handle to a GPIO line that can issue reset of the chip.
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| D | sja1105.txt | 6 - compatible:
8 - "nxp,sja1105e"
9 - "nxp,sja1105t"
10 - "nxp,sja1105p"
11 - "nxp,sja1105q"
12 - "nxp,sja1105r"
13 - "nxp,sja1105s"
18 and the non-SGMII devices, while pin-compatible, are not equal in terms
24 - sja1105,role-mac:
25 - sja1105,role-phy:
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| /Documentation/devicetree/bindings/net/ |
| D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
16 local-mac-address:
19 $ref: /schemas/types.yaml#definitions/uint8-array
21 - minItems: 6
24 mac-address:
29 local-mac-address property.
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| D | brcm,bcmgenet.txt | 4 - compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2",
5 "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5", "brcm,bcm2711-genet-v5".
6 - reg: address and length of the register set for the device
7 - interrupts and/or interrupts-extended: must be two cells, the first cell
10 optional third interrupt cell for Wake-on-LAN can be specified.
11 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
13 - phy-mode: see ethernet.txt file in the same directory
14 - #address-cells: should be 1
15 - #size-cells: should be 1
18 - clocks: When provided, must be two phandles to the functional clocks nodes
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| D | fsl-fec.txt | 4 - compatible : Should be "fsl,<soc>-fec"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain fec interrupt
7 - phy-mode : See ethernet.txt file in the same directory
10 - phy-supply : regulator that powers the Ethernet PHY.
11 - phy-handle : phandle to the PHY device connected to this device.
12 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
13 Use instead of phy-handle.
14 - fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
17 - fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
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| /Documentation/networking/device_drivers/ethernet/intel/ |
| D | i40e.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
47 ----------------------
49 …intel.com/content/dam/www/public/us/en/documents/release-notes/xl710-ethernet-controller-feature-m…
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| D | iavf.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2013-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Additional Configurations
16 - Known Issues/Troubleshooting
17 - Support
30 The guest OS loading the iavf driver must support MSI-X interrupts.
52 Viewing Link Messages
53 ---------------------
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| /Documentation/filesystems/ |
| D | squashfs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Squashfs is a compressed read-only filesystem for Linux.
14 Squashfs is intended for general read-only filesystem use, for archival
19 Mailing list: squashfs-devel@lists.sourceforge.net
23 ----------------------
30 Max filesystem size 2^64 256 MiB
31 Max file size ~ 2 TiB 16 MiB
32 Max files unlimited unlimited
33 Max directories unlimited unlimited
34 Max entries per directory unlimited unlimited
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| /Documentation/devicetree/bindings/usb/ |
| D | snps,dwc3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
48 clock-names:
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| /Documentation/core-api/ |
| D | rbtree.rst | 2 Red-black Trees (rbtree) in Linux
9 What are red-black trees, and what are they for?
10 ------------------------------------------------
12 Red-black trees are a type of self-balancing binary search tree, used for
19 Red-black trees are similar to AVL trees, but provide faster real-time bounded
26 There are a number of red-black trees in use in the kernel.
29 The high-resolution timer code uses an rbtree to organize outstanding
31 red-black tree. Virtual memory areas (VMAs) are tracked with red-black
38 Linux Weekly News article on red-black trees
41 Wikipedia entry on red-black trees
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| /Documentation/networking/ |
| D | ethtool-netlink.rst | 27 wake-on-lan password) omitted.
37 number 1 but any non-zero value should be understood as "true" by recipient.
86 representing bit values and mask of affected bits) and bit-by-bit (list of
89 Verbose (bit-by-bit) bitsets allow sending symbolic names for bits together
114 rounded up to a multiple of 32 bits. They consist of 32-bit words in host byte
129 Bit-by-bit form: nested (bitset) attribute contents:
131 +------------------------------------+--------+-----------------------------+
133 +------------------------------------+--------+-----------------------------+
135 +------------------------------------+--------+-----------------------------+
137 +-+----------------------------------+--------+-----------------------------+
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| D | eql.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Simon "Guru Aleph-Null" Janes, simon@ncm.com
12 that lets you load-balance IP serial links (SLIP or uncompressed PPP)
15 your link, in which it will help them out. This driver has been tested
27 together to work as one point-to-point link to increase your
32 The eql driver has only been tested with the Livingston PortMaster-2e
33 terminal server. I do not know if other terminal servers support load-
35 almost as well as the eql driver seems to do it (-- Unfortunately, in
36 my testing so far, the Livingston PortMaster 2e's load-balancing is a
40 TCP implementation is pretty fast though.--)
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| /Documentation/networking/device_drivers/ethernet/aquantia/ |
| D | atlantic.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 For the aQuantia Multi-Gigabit PCI Express Family of Ethernet Adapters
12 - Identifying Your Adapter
13 - Configuration
14 - Supported ethtool options
15 - Command Line Parameters
16 - Config file parameters
17 - Support
18 - License
23 The driver in this release is compatible with AQC-100, AQC-107, AQC-108
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| /Documentation/usb/ |
| D | gadget-testing.rst | 37 Function-specific configfs interface
38 ------------------------------------
45 The attribute is read-only.
51 ------------------------
76 Function-specific configfs interface
77 ------------------------------------
85 qmult queue length multiplier for high and super speed
87 Ethernet over USB link
89 Ethernet over USB link
99 ------------------------
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| /Documentation/networking/device_drivers/ethernet/stmicro/ |
| D | stmmac.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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| /Documentation/ABI/testing/ |
| D | sysfs-devices-system-cpu | 2 Date: pre-git history
3 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
18 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
37 See Documentation/admin-guide/cputopology.rst for more information.
43 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
58 Contact: Linux memory management mailing list <linux-mm@kvack.org>
61 When CONFIG_NUMA is enabled, a symbolic link that points
67 /sys/devices/system/cpu/cpu42/node2 -> ../../node/node2
77 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
93 core_siblings_list: human-readable list of the logical CPU
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