Searched +full:memory +full:- +full:region (Results 1 – 25 of 387) sorted by relevance
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| /Documentation/devicetree/bindings/reserved-memory/ |
| D | reserved-memory.txt | 1 *** Reserved memory regions ***
3 Reserved memory is specified as a node under the /reserved-memory node.
4 The operating system shall exclude reserved memory from normal usage
6 normal use) memory regions. Such memory regions are usually designed for
9 Parameters for each memory region can be encoded into the device tree
12 /reserved-memory node
13 ---------------------
14 #address-cells, #size-cells (required) - standard definition
15 - Should use the same values as the root node
16 ranges (required) - standard definition
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| D | xen,shared-memory.txt | 1 * Xen hypervisor reserved-memory binding
3 Expose one or more memory regions as reserved-memory to the guest
4 virtual machine. Typically, a region is configured at VM creation time
5 to be a shared memory area across multiple virtual machines for
8 For each of these pre-shared memory regions, a range is exposed under
9 the /reserved-memory node as a child node. Each range sub-node is named
10 xen-shmem@<address> and has the following properties:
12 - compatible:
13 compatible = "xen,shared-memory-v1"
15 - reg:
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| D | qcom,rmtfs-mem.txt | 1 Qualcomm Remote File System Memory binding
3 This binding describes the Qualcomm remote filesystem memory, which serves the
4 purpose of describing the shared memory region used for remote processors to
7 - compatible:
11 "qcom,rmtfs-mem"
13 - reg:
15 Value type: <prop-encoded-array>
16 Definition: must specify base address and size of the memory region,
17 as described in reserved-memory.txt
19 - size:
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| /Documentation/devicetree/bindings/pmem/ |
| D | pmem-region.txt | 1 Device-tree bindings for persistent memory regions
2 -----------------------------------------------------
4 Persistent memory refers to a class of memory devices that are:
6 a) Usable as main system memory (i.e. cacheable), and
9 Given b) it is best to think of persistent memory as a kind of memory mapped
11 persistent regions separately to the normal memory pool. To aid with that this
13 memory regions exist inside the physical address space.
15 Bindings for the region nodes:
16 -----------------------------
19 - compatible = "pmem-region"
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| /Documentation/devicetree/bindings/media/ |
| D | s5p-mfc.txt | 10 - compatible : value should be either one among the following
11 (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
12 (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
13 (c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
14 (d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
15 (e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
16 (f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC
18 - reg : Physical base address of the IP registers and length of memory
19 mapped region.
21 - interrupts : MFC interrupt number to the CPU.
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| D | aspeed-video.txt | 7 - compatible: "aspeed,ast2400-video-engine" or
8 "aspeed,ast2500-video-engine" or
9 "aspeed,ast2600-video-engine"
10 - reg: contains the offset and length of the VE memory region
11 - clocks: clock specifiers for the syscon clocks associated with
12 the VE (ordering must match the clock-names property)
13 - clock-names: "vclk" and "eclk"
14 - resets: reset specifier for the syscon reset associated with
16 - interrupts: the interrupt associated with the VE on this platform
19 - memory-region:
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| D | ti,vpe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benoit Parrot <bparrot@ti.com>
12 description: |-
14 processing applications. VPE consist of a single memory to memory
20 const: ti,dra7-vpe
24 - description: The VPE main register region
25 - description: Scaler (SC) register region
26 - description: Color Space Conversion (CSC) register region
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,smem.txt | 1 Qualcomm Shared Memory Manager binding
3 This binding describes the Qualcomm Shared Memory Manager, used to share data
6 - compatible:
12 - memory-region:
14 Value type: <prop-encoded-array>
15 Definition: handle to memory reservation for main SMEM memory region.
17 - qcom,rpm-msg-ram:
19 Value type: <prop-encoded-array>
20 Definition: handle to RPM message memory resource
22 - hwlocks:
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,k3-dsp-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
18 L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
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| D | ti,davinci-rproc.txt | 4 Binding status: Unstable - Subject to changes for DT representation of clocks
7 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
8 is used to offload some of the processor-intensive tasks or algorithms, for
11 The processor cores in the sub-system usually contain additional sub-modules
12 like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
18 Each DSP Core sub-system is represented as a single DT node.
21 --------------------
24 - compatible: Should be one of the following,
25 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
27 - reg: Should contain an entry for each value in 'reg-names'.
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| D | ti,keystone-rproc.txt | 5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
9 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller,
15 Each DSP Core sub-system is represented as a single DT node, and should also
22 --------------------
25 - compatible: Should be one of the following,
26 "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
27 "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
28 "ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs
29 "ti,k2g-dsp" for DSPs on Keystone 2 66AK2G SoCs
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| D | imx-rproc.txt | 1 NXP iMX6SX/iMX7D Co-Processor Bindings
2 ----------------------------------------
4 This binding provides support for ARM Cortex M4 Co-processor found on some
8 - compatible Should be one of:
9 "fsl,imx7d-cm4"
10 "fsl,imx6sx-cm4"
11 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
12 - syscon Phandle to syscon block which provide access to
16 - memory-region list of phandels to the reserved memory regions.
17 (See: ../reserved-memory/reserved-memory.txt)
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| D | ti,omap-remoteproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
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| /Documentation/devicetree/bindings/gpu/ |
| D | aspeed-gfx.txt | 4 - compatible
6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
11 - reg: Physical base address and length of the GFX registers
13 - interrupts: interrupt number for the GFX device
15 - clocks: clock number used to generate the pixel clock
17 - resets: reset line that must be released to use the GFX device
19 - memory-region:
20 Phandle to a memory region to allocate from, as defined in
21 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
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| /Documentation/devicetree/bindings/sound/ |
| D | google,cros-ec-codec.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/sound/google,cros-ec-codec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cheng-Yi Chiang <cychiang@chromium.org>
14 Embedded Controller (EC) and is controlled via a host-command
16 subnode of a cros-ec node.
17 (see Documentation/devicetree/bindings/mfd/google,cros-ec.yaml).
21 const: google,cros-ec-codec
23 "#sound-dai-cells":
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra210-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
15 sent from the memory controller.
19 const: nvidia,tegra210-emc
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| D | pl353-smc.txt | 1 Device tree bindings for ARM PL353 static memory controller
3 PL353 static memory controller supports two kinds of memory
8 - compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell".
9 - reg : Controller registers map and length.
10 - clock-names : List of input clock names - "memclk", "apb_pclk"
12 - clocks : Clock phandles (see clock bindings for details).
13 - address-cells : Must be 2.
14 - size-cells : Must be 1.
17 For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are
24 smcc: memory-controller@e000e000
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| /Documentation/ia64/ |
| D | aliasing.rst | 2 Memory Attribute Aliasing on IA-64
10 Memory Attributes
13 Itanium supports several attributes for virtual memory references.
19 WB Write-back (cacheable)
21 WC Write-coalescing
24 System memory typically uses the WB attribute. The UC attribute is
25 used for memory-mapped I/O devices. The WC attribute is uncacheable
34 support either WB or UC access to main memory, while others support
37 Memory Map
40 Platform firmware describes the physical memory map and the
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-qmss.txt | 5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
10 reading descriptor address to a particular memory mapped location. The PDSPs
13 descriptor RAM. Descriptor RAM is configurable as internal or external memory.
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
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| /Documentation/devicetree/bindings/riscv/ |
| D | sifive-l2-cache.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Yash Shah <yash.shah@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
17 of memory for masters in a Core Complex. The Level 2 Cache Controller also
18 acts as directory-based coherency manager.
22 - $ref: /schemas/cache-controller.yaml#
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| /Documentation/devicetree/bindings/dsp/ |
| D | fsl,dsp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Baluta <daniel.baluta@nxp.com>
14 advanced pre- and post- audio processing.
19 - fsl,imx8qxp-dsp
20 - fsl,imx8qm-dsp
21 - fsl,imx8mp-dsp
28 - description: ipg clock
29 - description: ocram clock
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| /Documentation/devicetree/bindings/mfd/ |
| D | aspeed-lpc.txt | 5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
11 The LPC controller is represented as a multi-function device to account for the
24 APB-to-LPC bridging amonst other functions.
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
39 [1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c888374547021…
40 …el.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev…
46 - compatible: One of:
47 "aspeed,ast2400-lpc", "simple-mfd"
48 "aspeed,ast2500-lpc", "simple-mfd"
50 - reg: contains the physical address and length values of the Aspeed
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| /Documentation/devicetree/bindings/misc/ |
| D | aspeed-p2a-ctrl.txt | 2 Device tree bindings for Aspeed AST2400/AST2500 PCI-to-AHB Bridge Control Driver
7 memory. The BMC can disable this bridge. If the bridge is enabled, the host
8 has read access to all the regions of memory, however the host only has read
14 - compatible: must be one of:
15 - "aspeed,ast2400-p2a-ctrl"
16 - "aspeed,ast2500-p2a-ctrl"
21 - reg: A hint for the memory regions associated with the P2A controller
22 - memory-region: A phandle to a reserved_memory region to be used for the PCI
25 The p2a-control node should be the child of a syscon node with the required
28 - compatible : Should be one of the following:
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| /Documentation/x86/ |
| D | resctrl_ui.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
10 - Tony Luck <tony.luck@intel.com>
11 - Vikas Shivappa <vikas.shivappa@intel.com>
25 MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local"
26 MBA (Memory Bandwidth Allocation) "mba"
31 # mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps]] /sys/fs/resctrl
47 pseudo-locking is a unique way of using cache control to "pin" or
49 "Cache Pseudo-Locking".
86 own settings for cache use which can over-ride
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| /Documentation/driver-api/ |
| D | ntb.rst | 5 NTB (Non-Transparent Bridge) is a type of PCI-Express bridge chip that connects
6 the separate memory systems of two or more computers to the same PCI-Express
8 registers and memory translation windows, as well as non common features like
9 scratchpad and message registers. Scratchpad registers are read-and-writable
15 Memory windows allow translated read and write access to the peer memory.
36 ----------------------------------------
38 Primary purpose of NTB is to share some peace of memory between at least two
40 mainly used to perform the proper memory window initialization. Typically
41 there are two types of memory window interfaces supported by the NTB API:
48 Memory: Local NTB Port: Peer NTB Port: Peer MMIO:
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