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| /Documentation/ABI/testing/ |
| D | sysfs-class-remoteproc | 4 Description: Remote processor firmware
7 remote processor.
9 To change the running firmware, ensure the remote processor is
15 Description: Remote processor state
17 Reports the state of the remote processor, which will be one of:
25 "offline" means the remote processor is powered off.
27 "suspended" means that the remote processor is suspended and
30 "running" is the normal state of an available remote processor
33 the remote processor.
35 "invalid" is returned if the remote processor is in an
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| D | sysfs-bus-rpmsg | 7 processor. Channels are identified with a (textual) name,
19 processor. Channels have a local ("source") rpmsg address,
37 processor. Channels have a local ("source") rpmsg address,
48 remote processor. This make it a local rpmsg server,
59 processor. Channels are identified by a textual name (see
69 to the other processor, in order to let it know about the
83 processor. Channels are identified by a textual name (see
89 remote processor is referred as rpmsg driver. The rpmsg device
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,smsm.txt | 4 information between the processors in a Qualcomm SoC. Each processor is
5 assigned 32 bits of state that can be modified. A processor can through a
7 certain bit owned by a certain remote processor.
19 signaling the N:th remote processor
27 Definition: identifier of the local processor in the list of hosts, or
29 matrix representing the local processor
43 Each processor's state bits are described by a subnode of the smsm device node.
45 processor's state bits or the local processors bits. The node names are not
63 to belong to a remote processor
73 Definition: one entry specifying remote IRQ used by the remote processor
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| D | qcom,smd.txt | 15 processor of some sort - or in SMD language an "edge". The name of the edges
22 Definition: should specify the IRQ used by the remote processor to
23 signal this processor about communication related updates
35 signaling the remote processor:
43 Definition: the identifier of the remote processor in the smd channel
49 Definition: the identifier for the remote processor as known by the rest
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,omap-remoteproc.yaml | 13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
22 sub-system. The DSP processor sub-system can contain any of the TI's C64x,
23 C66x or C67x family of DSP cores as the main execution unit. The IPU processor
27 Each remote processor sub-system is represented as a single DT node. Each node
29 the host processor (MPU) to perform the device management of the remote
30 processor and to communicate with the remote processor. The various properties
54 for this remote processor to access any external RAM memory or
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| D | st-rproc.txt | 1 STMicroelectronics Co-Processor Bindings
7 the bootloader starts a co-processor, the primary OS must detect its state
17 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
18 - clock-frequency Clock frequency to set co-processor at if the bootloader
21 for the co-processor
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| D | ti,keystone-rproc.txt | 5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
10 a dedicated local power/sleep controller etc. The DSP processor core in
11 Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
17 or optional properties that enable the OS running on the host processor (ARM
18 CorePac) to perform the device management of the remote processor and to
19 communicate with the remote processor.
56 the remote processor to the host processor. The values should
67 stack. This will be used to interrupt the remote processor.
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| D | ti,k3-dsp-rproc.yaml | 14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
19 controller, a dedicated local power/sleep controller etc. The DSP processor
20 cores in the K3 SoCs are usually either a TMS320C66x CorePac processor or a
21 TMS320C71x CorePac processor.
25 host processor (Arm CorePac) to perform the device management of the remote
26 processor and to communicate with the remote processor.
54 communication with the remote processor. This property should match
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| /Documentation/admin-guide/pm/ |
| D | intel_idle.rst | 20 a particular processor model in it depends on whether or not it recognizes that
21 processor model and may also depend on information coming from the platform
26 ``intel_idle`` uses the ``MWAIT`` instruction to inform the processor that the
28 processor's functional blocks into low-power states. That instruction takes two
30 first of which, referred to as a *hint*, can be used by the processor to
47 Each ``MWAIT`` hint value is interpreted by the processor as a license to
48 reconfigure itself in a certain way in order to save energy. The processor
52 processor) corresponding to them depends on the processor model and it may also
58 for different processor models included in the driver itself and the ACPI tables
59 of the system. The former are always used if the processor model at hand is
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| D | intel_pstate.rst | 63 the processor.
90 enabled in the processor and possibly on the processor model.
100 If the processor supports the HWP feature, it will be enabled during the
101 processor initialization and cannot be disabled after that. It is possible
105 If the HWP feature has been enabled, ``intel_pstate`` relies on the processor to
106 select P-states by itself, but still it can give hints to the processor's
111 Even though the P-state selection is carried out by the processor automatically,
120 In this configuration ``intel_pstate`` will write 0 to the processor's
122 Energy-Performance Bias (EPB) knob (otherwise), which means that the processor's
130 Also, in this configuration the range of P-states available to the processor's
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| /Documentation/admin-guide/acpi/ |
| D | cppc_sysfs.rst | 4 Collaborative Processor Performance Control (CPPC)
11 performance of a logical processor on a contigious and abstract performance
38 * highest_perf : Highest performance of this processor (abstract scale).
39 * nominal_perf : Highest sustained performance of this processor
41 * lowest_nonlinear_perf : Lowest performance of this processor with nonlinear
43 * lowest_perf : Lowest performance of this processor (abstract scale).
47 The above frequencies should only be used to report processor performance in
52 Reference counter ticks up proportional to processor's reference performance.
53 Delivered counter ticks up proportional to processor's delivered performance.
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| /Documentation/hwmon/ |
| D | fam15h_power.rst | 25 1) Processor TDP (Thermal design power)
28 processor varies based on the workload being executed. Derated power
36 be calculated using different processor northbridge function
41 consumed by the processor for NB and logic external to the core.
45 the processor can support.
48 consumed by the processor.
57 attributes only for internal node0 of a multi-node processor.
62 calculate the average power consumed by a processor during a
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| D | asc7621.rst | 117 - Monitors VCCP, 2.5V, 3.3V, 5.0V, and 12V motherboard/processor supplies
137 peci_legacy = 1, PECI Processor Temperature 0
141 4 PECI Processor Temperature 0
142 5 PECI Processor Temperature 1
143 6 PECI Processor Temperature 2
144 7 PECI Processor Temperature 3
153 4 PECI Processor Temperature 0
154 5 PECI Processor Temperature 1
155 6 PECI Processor Temperature 2
156 7 PECI Processor Temperature 3
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| D | k10temp.rst | 73 AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks:
77 AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet:
81 AMD Family 10h Desktop Processor Power and Thermal Data Sheet:
99 socket type, not the processor's actual capabilities. Therefore, if you
100 are using an AM3 processor on an AM2+ mainboard, you can safely use the
108 Tctl is the processor temperature control value, used by the platform to
112 the processor temperature relative to the point at which the system must
113 supply the maximum cooling for the processor's specified maximum case
119 which the processor will throttle itself to avoid damage is available in
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| /Documentation/core-api/ |
| D | this_cpu_ops.rst | 9 variables associated with the *currently* executing processor. This is
12 specific processor).
14 this_cpu operations add a per cpu variable offset to the processor
21 processor is not changed between the calculation of the address and
33 data specific to the currently executing processor. Only the current
34 processor should be accessing that variable and therefore there are no
71 the processor. So the relocation to the per cpu base is encoded in the
88 prevent the kernel from moving the thread to a different processor
111 reserved for a specific processor. Without disabling preemption in the
116 the value of the individual counters for each processor are
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| /Documentation/staging/ |
| D | rpmsg.rst | 2 Remote Processor Messaging (rpmsg) Framework
14 Modern SoCs typically employ heterogeneous remote processor devices in
26 multimedia tasks from the main application processor.
34 hardware accessible only by the remote processor, reserving kernel-controlled
35 resources on behalf of the remote processor, etc..).
48 to the processor. To minimize the risks of rogue (or buggy) userland code
54 Every rpmsg device is a communication channel with a remote processor (thus
73 sends a message across to the remote processor on a given channel.
80 one becomes available (i.e. until the remote processor consumes
92 sends a message across to the remote processor on a given channel,
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| D | remoteproc.rst | 2 Remote Processor Framework
8 Modern SoCs typically have heterogeneous remote processor devices in asymmetric
29 existing virtio drivers with remote processor backends at a minimal development
39 Boot a remote processor (i.e. load its firmware, power it on, ...).
41 If the remote processor is already powered on, this function immediately
54 Power off a remote processor (previously booted with rproc_boot()).
75 the remote processor's refcount, so always use rproc_put() to
90 /* let's power on and boot our remote processor */
99 * our remote processor is now powered on... give it some work
115 Allocate a new remote processor handle, but don't register
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| /Documentation/devicetree/bindings/arm/keystone/ |
| D | ti,k3-sci-common.yaml | 13 The TI K3 family of SoCs usually have a central System Controller Processor
15 resets, interrupts etc. The communication with that processor is performed
42 - description: TI-SCI processor id for the remote processor device
43 - description: TI-SCI host id to which processor control ownership
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| /Documentation/admin-guide/hw-vuln/ |
| D | gather_data_sampling.rst | 54 IA32_ARCH_CAPABILITIES[GDS_NO] R/O Processor is not vulnerable.
67 However, the processor will still enumerate AVX support. Userspace that
89 Not affected Processor not vulnerable.
90 Vulnerable Processor vulnerable and mitigation disabled.
91 Vulnerable: No microcode Processor vulnerable and microcode is missing
94 no microcode Processor is vulnerable and microcode is missing
96 Mitigation: Microcode Processor is vulnerable and mitigation is in
98 Mitigation: Microcode (locked) Processor is vulnerable and mitigation is in
101 hypervisor status Running on a virtual guest processor that is
103 processor is mitigated or vulnerable.
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| D | special-register-buffer-data-sampling.rst | 21 A processor is affected by SRBDS if its Family_Model and stepping is
66 processor.
101 Setting IA32_MCU_OPT_CTRL[0] (RNGDS_MITG_DIS) to 1 for a logical processor
103 enclave on that logical processor. Opting out of the mitigation for a
104 particular logical processor does not affect the RDRAND and RDSEED mitigations
129 Not affected Processor not vulnerable
130 Vulnerable Processor vulnerable and mitigation disabled
131 Vulnerable: No microcode Processor vulnerable and microcode is missing
133 Mitigation: Microcode Processor is vulnerable and mitigation is in
135 Mitigation: TSX disabled Processor is only vulnerable when TSX is
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| D | processor_mmio_stale_data.rst | 2 Processor MMIO Stale Data Vulnerabilities
5 Processor MMIO Stale Data Vulnerabilities are a class of memory-mapped I/O
22 one microarchitectural buffer or register to another. Processor MMIO Stale Data
108 If a CPU is in the affected processor list, but not affected by a variant, it
117 specific variants of Processor MMIO Stale Data vulnerabilities and mitigation
122 Bit 13 - SBDR_SSDP_NO - When set, processor is not affected by either the
125 Bit 14 - FBSDP_NO - When set, processor is not affected by the Fill Buffer
127 Bit 15 - PSDP_NO - When set, processor is not affected by Primary Stale Data
134 Bit 18 - FB_CLEAR_CTRL - Processor supports read and write to MSR
152 Like MDS, all variants of Processor MMIO Stale Data vulnerabilities have the
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| /Documentation/powerpc/ |
| D | vcpudispatch_stats.rst | 7 For Shared Processor LPARs, the POWER Hypervisor maintains a relatively
8 static mapping of the LPAR processors (vcpus) to physical processor
10 on their associated physical processor chip. However, under certain
11 scenarios, vcpus may be dispatched on a different processor chip (away
31 2. number of times this vcpu was dispatched on the same processor as last
33 3. number of times this vcpu was dispatched on a different processor core
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| /Documentation/driver-api/pm/ |
| D | cpuidle.rst | 17 fetch and execute instructions: hardware threads, if present, or processor
20 with it, there is an opportunity to save energy for the processor that it
22 instructions from memory and putting some of the processor's functional units
27 (from the kernel perspective) and ask the processor to use (or "enter") that
35 units: *governors* responsible for selecting idle states to ask the processor
45 select an idle state to ask the processor to enter in order to save some energy.
86 processor holding the given CPU can be asked to enter).
113 Called to select an idle state for the processor holding the (logical)
125 the scheduler tick before asking the processor to enter the selected
128 processor will be asked to enter the selected idle state without
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| /Documentation/devicetree/bindings/mailbox/ |
| D | omap-mailbox.txt | 6 various processor subsystems and is connected on an interconnect bus. The
12 within a processor subsystem, and there can be more than one line going to a
13 specific processor's interrupt controller. The interrupt line connections are
25 routed to different processor sub-systems on DRA7xx as they are routed through
29 all these clusters are multiplexed and routed to different processor subsystems
53 - ti,mbox-num-users: Number of targets (processor devices) that the mailbox
77 used for the communication between the host processor and a remote processor.
95 multiple interrupt lines connected to the MPU processor.
105 processor on AM33xx/AM43xx SoCs.
109 A device needing to communicate with a target processor device should specify
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| /Documentation/devicetree/bindings/powerpc/nintendo/ |
| D | gamecube.txt | 16 Represents the interface between the graphics processor and a external
25 1.b) The Processor Interface (PI) node
27 Represents the data and control interface between the main processor
28 and graphics and audio processor.
47 Represents the digital signal processor interface, designed to offload
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