Searched +full:tx +full:- +full:queues +full:- +full:to +full:- +full:use (Results 1 – 25 of 32) sorted by relevance
12
| /Documentation/networking/device_drivers/ethernet/huawei/ |
| D | hinic.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 The driver supports a range of link-speed devices (10GbE, 25GbE, 40GbE, etc.).
14 Some HiNIC devices support SR-IOV. This driver is used for Physical Function
17 HiNIC devices support MSI-X interrupt vector for each Tx/Rx queue and
21 TCP Transmit Segmentation Offload(TSO), Receive-Side Scaling(RSS) and
28 19e5:1822 - HiNIC PF
34 hinic_dev - Implement a Logical Network device that is independent from
37 hinic_hwdev - Implement the HW details of the device and include the components
55 Asynchronous Event Queues(AEQs) - The event queues for receiving messages from
58 Application Programmable Interface commands(API CMD) - Interface for sending
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| /Documentation/devicetree/bindings/net/ |
| D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
15 # will be able to report a warning when we have that compatible, since
16 # we will validate the node thanks to the select, but won't report it
23 - snps,dwmac
24 - snps,dwmac-3.50a
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| D | intel,dwmac-plat.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: "snps,dwmac.yaml#"
27 - items:
28 - enum:
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| D | fsl-fec.txt | 4 - compatible : Should be "fsl,<soc>-fec"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain fec interrupt
7 - phy-mode : See ethernet.txt file in the same directory
10 - phy-supply : regulator that powers the Ethernet PHY.
11 - phy-handle : phandle to the PHY device connected to this device.
12 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
13 Use instead of phy-handle.
14 - fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
15 hw multi queues. Should specify the tx queue number, otherwise set tx queue
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| D | keystone-netcp.txt | 6 switch sub-module to send and receive packets. NetCP also includes a packet
7 accelerator (PA) module to perform packet classification operations such as
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
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| /Documentation/networking/device_drivers/ethernet/freescale/ |
| D | dpaa.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 - Madalin Bucur <madalin.bucur@nxp.com>
9 - Camelia Groza <camelia.groza@nxp.com>
13 - DPAA Ethernet Overview
14 - DPAA Ethernet Supported SoCs
15 - Configuring DPAA Ethernet in your kernel
16 - DPAA Ethernet Frame Processing
17 - DPAA Ethernet Features
18 - DPAA IRQ Affinity and Receive Side Scaling
19 - Debugging
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| /Documentation/networking/device_drivers/ethernet/intel/ |
| D | i40e.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
25 For questions related to hardware requirements, refer to the documentation
26 supplied with your Intel adapter. All hardware requirements listed apply to use
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| D | iavf.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2013-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Additional Configurations
16 - Known Issues/Troubleshooting
17 - Support
28 CONFIG_PCI_MSI to be enabled.
30 The guest OS loading the iavf driver must support MSI-X interrupts.
44 For information on how to identify your adapter, and for the latest NVM/FW
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| /Documentation/devicetree/bindings/mailbox/ |
| D | omap-mailbox.txt | 5 using a queued mailbox interrupt mechanism. The IP block is external to the
10 Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
11 interrupt lines. An output interrupt line is routed to an interrupt controller
12 within a processor subsystem, and there can be more than one line going to a
17 and tx interrupt source per h/w fifo. Communication between different processors
18 is achieved through the appropriate programming of the rx and tx interrupt
21 The number of h/w fifo queues and interrupt lines dictate the usable registers.
23 instance. DRA7xx has multiple instances with different number of h/w fifo queues
25 routed to different processor sub-systems on DRA7xx as they are routed through
29 all these clusters are multiplexed and routed to different processor subsystems
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| /Documentation/networking/ |
| D | multiqueue.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 ---------------------------------------------------------
15 Base drivers are required to use the new alloc_etherdev_mq() or
16 alloc_netdev_mq() functions to allocate the subqueues for the device. The
18 the subqueue memory, as well as netdev configuration of where the queues
21 The base driver will also need to manage the queues as it does the global
22 netdev->queue_lock today. Therefore base drivers should use the
23 netif_{start|stop|wake}_subqueue() functions to manage each queue while the
24 device is still operational. netdev->queue_lock is still used when the device
33 A new round-robin qdisc, sch_multiq also supports multiple hardware queues. The
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| D | scaling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 networking stack to increase parallelism and improve performance for
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
27 Contemporary NICs support multiple receive and transmit descriptor queues
28 (multi-queue). On reception, a NIC can send different packets to different
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| D | af_xdp.rst | 1 .. SPDX-License-Identifier: GPL-2.0
18 redirect ingress frames to other XDP enabled netdevs, using the
20 XDP programs to redirect frames to a memory buffer in a user-space
25 TX ring. A socket can receive packets on the RX ring and it can send
26 packets on the TX ring. These rings are registered and sized with the
28 to have at least one of these rings for each socket. An RX or TX
29 descriptor ring points to a data buffer in a memory area called a
30 UMEM. RX and TX can share the same UMEM so that a packet does not have
31 to be copied between RX and TX. Moreover, if a packet needs to be kept
32 for a while due to a possible retransmit, the descriptor that points
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| D | netdevices.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 Network device structures need to persist even after module is unloaded and
17 If device has registered successfully, it will be freed on last use
18 by free_netdev(). This is required to handle the pathological case cleanly
23 separately allocated data is attached to the network device
24 (netdev_priv()) then it is up to the module exit handler to free that.
33 --------------
41 .. code-block:: c
50 return -ENOMEM;
60 /* net_device is visible to the user! */
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| D | net_dim.rst | 2 Net DIM - Generic Network Dynamic Interrupt Moderation
19 Dynamic Interrupt Moderation (DIM) (in networking) refers to changing the
20 interrupt moderation configuration of a channel in order to optimize packet
21 processing. The mechanism includes an algorithm which decides if and how to
25 to the previous sample and if required, it can decide to change some of the
30 the algorithm might decide not to change anything. The configuration fields are
32 number of wanted packets per event. The Net DIM algorithm ascribes importance to
42 #. Compares it to previous sample.
43 #. Makes a decision - suggests interrupt moderation configuration fields.
47 supplied by the driver registered to Net DIM. The previous data is the new data
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| /Documentation/networking/device_drivers/ethernet/ti/ |
| D | cpsw.rst | 1 .. SPDX-License-Identifier: GPL-2.0
26 - TX queues must be rated starting from txq0 that has highest priority
27 - Traffic classes are used starting from 0, that has highest priority
28 - CBS shapers should be used with rated queues
29 - The bandwidth for CBS shapers has to be set a little bit more then
30 potential incoming rate, thus, rate of all incoming tx queues has
31 to be a little less
32 - Real rates can differ, due to discreetness
33 - Map skb-priority to txq is not enough, also skb-priority to l2 prio
34 map has to be created with ip or vconfig tool
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| /Documentation/networking/device_drivers/ethernet/stmicro/ |
| D | stmmac.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-qmss.txt | 5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
10 reading descriptor address to a particular memory mapped location. The PDSPs
12 Linking RAM registers are used to link the descriptors which are stored in
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
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| D | keystone-navigator-dma.txt | 6 the actual data movements across clients using destination queues. Every
13 ------------------
15 ------------------
17 |-> DMA instance #0
19 |-> DMA instance #1
23 |-> DMA instance #n
27 - compatible: Should be "ti,keystone-navigator-dma"
28 - clocks: phandle to dma instances clocks. The clock handles can be as
31 - ti,navigator-cloud-address: Should contain base address for the multi-core
33 configuration.. Navigator cloud global address needs to be programmed
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| /Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ |
| D | overview.rst | 16 DPAA2 is a hardware architecture designed for high-speeed network
23 DPAA2 hardware resources. The MC provides an object-based abstraction for
24 software drivers to use the DPAA2 hardware.
25 The MC uses DPAA2 hardware resources such as queues, buffer pools, and
26 network ports to create functional objects/devices such as network
28 The MC provides memory-mapped I/O command interfaces (MC portals)
29 which DPAA2 software drivers use to operate on DPAA2 objects.
34 +--------------------------------------+
38 +-----------------------------|--------+
41 | config,use,destroy)
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| /Documentation/networking/device_drivers/ethernet/aquantia/ |
| D | atlantic.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 For the aQuantia Multi-Gigabit PCI Express Family of Ethernet Adapters
12 - Identifying Your Adapter
13 - Configuration
14 - Supported ethtool options
15 - Command Line Parameters
16 - Config file parameters
17 - Support
18 - License
23 The driver in this release is compatible with AQC-100, AQC-107, AQC-108
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| /Documentation/networking/device_drivers/ethernet/amazon/ |
| D | ena.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 ENA is a networking interface designed to make good use of modern CPU
17 The driver supports a range of ENA devices, is link-speed independent
21 Some ENA devices support SR-IOV. This driver is used for both the
22 SR-IOV Physical Function (PF) and Virtual Function (VF) devices.
25 processing by providing multiple Tx/Rx queue pairs (the maximum number
26 is advertised by the device via the Admin Queue), a dedicated MSI-X
27 interrupt vector per Tx/Rx queue pair, adaptive interrupt moderation,
32 Receive-side scaling (RSS) is supported for multi-core scaling.
36 to recover in a manner transparent to the application, as well as
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| /Documentation/userspace-api/media/cec/ |
| D | cec-ioc-receive.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
14 CEC_RECEIVE, CEC_TRANSMIT - Receive or transmit a CEC message
34 Pointer to struct cec_msg.
39 To receive a CEC message the application has to fill in the
40 ``timeout`` field of struct :c:type:`cec_msg` and pass it to
42 If the file descriptor is in non-blocking mode and there are no received
43 messages pending, then it will return -1 and set errno to the ``EAGAIN``
45 is non-zero and no message arrived within ``timeout`` milliseconds, then
46 it will return -1 and set errno to the ``ETIMEDOUT`` error code.
52 2. the result of an earlier non-blocking transmit (the ``sequence`` field will
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| /Documentation/networking/device_drivers/ethernet/microsoft/ |
| D | netvsc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Hyper-V network driver
17 ----------------
19 Hyper-V host version does. Windows Server 2016 and Azure
24 --------------------
25 Hyper-V supports receive side scaling. For TCP & UDP, packets can
26 be distributed among available queues based on IP address and port
31 hash level is L4. We currently only allow switching TX hash level
39 To include UDP port numbers in hashing::
41 ethtool -N eth0 rx-flow-hash udp4 sdfn
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | ocelot.txt | 5 -----
9 - VSC9959 (Felix)
10 - VSC9953 (Seville)
13 larger ENETC root complex. As a result, the ethernet-switch node is a sub-node
14 of the PCIe root complex node and its "reg" property conforms to the parent
22 The interrupt line is used to signal availability of PTP TX timestamps and for
25 For the external switch ports, depending on board configuration, "phy-mode" and
26 "phy-handle" are populated by board specific device tree instances. Ports 4 and
30 the Ocelot hardware core. The CPU port in Ocelot is a set of queues, which are
31 connected, in the Node Processor Interface (NPI) mode, to an Ethernet port.
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| /Documentation/networking/dsa/ |
| D | sja1105.rst | 10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
17 These are SPI-managed automotive switches, with all ports being gigabit
21 set-and-forget use, with minimal dynamic interaction at runtime. They
22 require a static configuration to be composed by software and packed
56 Also the configuration is write-only (software cannot read it back from the
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