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Searched refs:L3 (Results 1 – 24 of 24) sorted by relevance

/arch/m68k/lib/
Ddivsi3.S117 jpl L3
120 L3: movel sp@+, d2 label
Dudivsi3.S95 jcc L3 /* then try next algorithm */
107 L3: movel d1, d2 /* use d2 as divisor backup */ label
/arch/riscv/lib/
Dtishift.S33 beqz a2, .L3
44 .L3: label
/arch/sparc/net/
Dbpf_jit_64.h23 #define L3 0x13 macro
Dbpf_jit_comp_64.c223 [BPF_REG_9] = L3,
/arch/alpha/kernel/
Dsetup.c1294 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1305 L3 = -1; in determine_cpu_caches()
1326 L3 = -1; in determine_cpu_caches()
1357 L3 = external_cache_probe(1024*1024, width); in determine_cpu_caches()
1371 L3 = -1; in determine_cpu_caches()
1394 L3 = -1; in determine_cpu_caches()
1401 L3 = -1; in determine_cpu_caches()
1406 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1413 alpha_l3_cacheshape = L3; in determine_cpu_caches()
/arch/x86/events/intel/
Dds.c63 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
67 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
68 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
69 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
70 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
71 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
72 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
74 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
84 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in intel_pmu_pebs_data_source_nhm()
85 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
[all …]
/arch/xtensa/lib/
Dmemset.S83 bbci.l a4, 2, .L3
87 .L3: label
Dusercopy.S170 bbci.l a4, 2, .L3
176 .L3: label
Dmemcopy.S161 bbsi.l a4, 2, .L3
165 .L3: label
/arch/arm/boot/dts/
Dgemini-wbd111.dts45 label = "wbd111:red:L3";
63 label = "wbd111:green:L3";
Dgemini-wbd222.dts44 label = "wbd111:red:L3";
62 label = "wbd111:green:L3";
Domap5-l4-abe.dtsi53 /* L3 to L4 ABE mapping */
110 <0x49022000 0xff>; /* L3 Interconnect */
143 <0x49024000 0xff>; /* L3 Interconnect */
176 <0x49026000 0xff>; /* L3 Interconnect */
228 <0x4902e000 0x7f>; /* L3 Interconnect */
271 <0x49032000 0x7f>; /* L3 Interconnect */
Domap4-l4-abe.dtsi53 /* L3 to L4 ABE mapping */
110 <0x49022000 0xff>; /* L3 Interconnect */
143 <0x49024000 0xff>; /* L3 Interconnect */
176 <0x49026000 0xff>; /* L3 Interconnect */
244 <0x4902e000 0x7f>; /* L3 Interconnect */
306 <0x49032000 0x7f>; /* L3 Interconnect */
Dlogicpd-torpedo-37xx-devkit.dts62 /* The DM3730 has a faster L3 than OMAP35, so increase pixel clock */
Ddra7-l4.dtsi2289 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2290 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2291 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2292 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2293 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2294 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2295 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2296 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2365 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2366 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
[all …]
Domap3-n900.dts14 * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
19 * There is "unofficial" version of bootloader which enables AES in L3 firewall
21 * There is also no runtime detection code if AES is disabled in L3 firewall...
Domap4.dtsi247 <0x4902c000 0x4902c000 0x1000>; /* L3 */
Domap4-l4.dtsi1533 /* Unused DSS L4 access, see L3 instead */
/arch/hexagon/lib/
Dmemset.S164 if (p0.new) jump:nt .L3
176 .L3: label
/arch/arm/mach-omap2/
Dsram243x.S86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
296 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
Dsram242x.S86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
296 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
/arch/powerpc/perf/
Disa207-common.c184 ret = PH(LVL, L3); in isa207_find_source()
/arch/sparc/lib/
DM7memcpy.S436 ! Gives existing cache lines time to be moved out of L1/L2/L3 cache.