1// SPDX-License-Identifier: GPL-2.0 2&l4_cfg { /* 0x4a000000 */ 3 compatible = "ti,omap4-l4-cfg", "simple-bus"; 4 reg = <0x4a000000 0x800>, 5 <0x4a000800 0x800>, 6 <0x4a001000 0x1000>; 7 reg-names = "ap", "la", "ia0"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ 11 <0x00080000 0x4a080000 0x080000>, /* segment 1 */ 12 <0x00100000 0x4a100000 0x080000>, /* segment 2 */ 13 <0x00180000 0x4a180000 0x080000>, /* segment 3 */ 14 <0x00200000 0x4a200000 0x080000>, /* segment 4 */ 15 <0x00280000 0x4a280000 0x080000>, /* segment 5 */ 16 <0x00300000 0x4a300000 0x080000>; /* segment 6 */ 17 18 segment@0 { /* 0x4a000000 */ 19 compatible = "simple-bus"; 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 23 <0x00001000 0x00001000 0x001000>, /* ap 1 */ 24 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 25 <0x00002000 0x00002000 0x001000>, /* ap 3 */ 26 <0x00003000 0x00003000 0x001000>, /* ap 4 */ 27 <0x00004000 0x00004000 0x001000>, /* ap 5 */ 28 <0x00005000 0x00005000 0x001000>, /* ap 6 */ 29 <0x00056000 0x00056000 0x001000>, /* ap 7 */ 30 <0x00057000 0x00057000 0x001000>, /* ap 8 */ 31 <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ 32 <0x00058000 0x00058000 0x004000>, /* ap 10 */ 33 <0x00062000 0x00062000 0x001000>, /* ap 11 */ 34 <0x00063000 0x00063000 0x001000>, /* ap 12 */ 35 <0x00008000 0x00008000 0x002000>, /* ap 23 */ 36 <0x0000a000 0x0000a000 0x001000>, /* ap 24 */ 37 <0x00066000 0x00066000 0x001000>, /* ap 25 */ 38 <0x00067000 0x00067000 0x001000>, /* ap 26 */ 39 <0x0005e000 0x0005e000 0x002000>, /* ap 80 */ 40 <0x00060000 0x00060000 0x001000>, /* ap 81 */ 41 <0x00064000 0x00064000 0x001000>, /* ap 86 */ 42 <0x00065000 0x00065000 0x001000>; /* ap 87 */ 43 44 target-module@2000 { /* 0x4a002000, ap 3 06.0 */ 45 compatible = "ti,sysc-omap4", "ti,sysc"; 46 ti,hwmods = "ctrl_module_core"; 47 reg = <0x2000 0x4>, 48 <0x2010 0x4>; 49 reg-names = "rev", "sysc"; 50 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 51 <SYSC_IDLE_NO>, 52 <SYSC_IDLE_SMART>, 53 <SYSC_IDLE_SMART_WKUP>; 54 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ 55 #address-cells = <1>; 56 #size-cells = <1>; 57 ranges = <0x0 0x2000 0x1000>; 58 59 omap4_scm_core: scm@0 { 60 compatible = "ti,omap4-scm-core", "simple-bus"; 61 reg = <0x0 0x1000>; 62 #address-cells = <1>; 63 #size-cells = <1>; 64 ranges = <0 0 0x1000>; 65 66 scm_conf: scm_conf@0 { 67 compatible = "syscon"; 68 reg = <0x0 0x800>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 }; 72 73 omap_control_usb2phy: control-phy@300 { 74 compatible = "ti,control-phy-usb2"; 75 reg = <0x300 0x4>; 76 reg-names = "power"; 77 }; 78 79 omap_control_usbotg: control-phy@33c { 80 compatible = "ti,control-phy-otghs"; 81 reg = <0x33c 0x4>; 82 reg-names = "otghs_control"; 83 }; 84 }; 85 }; 86 87 target-module@4000 { /* 0x4a004000, ap 5 02.0 */ 88 compatible = "ti,sysc-omap4", "ti,sysc"; 89 reg = <0x4000 0x4>; 90 reg-names = "rev"; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 ranges = <0x0 0x4000 0x1000>; 94 95 cm1: cm1@0 { 96 compatible = "ti,omap4-cm1", "simple-bus"; 97 reg = <0x0 0x2000>; 98 #address-cells = <1>; 99 #size-cells = <1>; 100 ranges = <0 0 0x2000>; 101 102 cm1_clocks: clocks { 103 #address-cells = <1>; 104 #size-cells = <0>; 105 }; 106 107 cm1_clockdomains: clockdomains { 108 }; 109 }; 110 }; 111 112 target-module@8000 { /* 0x4a008000, ap 23 32.0 */ 113 compatible = "ti,sysc-omap4", "ti,sysc"; 114 reg = <0x8000 0x4>; 115 reg-names = "rev"; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges = <0x0 0x8000 0x2000>; 119 120 cm2: cm2@0 { 121 compatible = "ti,omap4-cm2", "simple-bus"; 122 reg = <0x0 0x2000>; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 ranges = <0 0 0x2000>; 126 127 cm2_clocks: clocks { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 }; 131 132 cm2_clockdomains: clockdomains { 133 }; 134 }; 135 }; 136 137 target-module@56000 { /* 0x4a056000, ap 7 0a.0 */ 138 compatible = "ti,sysc-omap2", "ti,sysc"; 139 reg = <0x56000 0x4>, 140 <0x5602c 0x4>, 141 <0x56028 0x4>; 142 reg-names = "rev", "sysc", "syss"; 143 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 144 SYSC_OMAP2_EMUFREE | 145 SYSC_OMAP2_SOFTRESET | 146 SYSC_OMAP2_AUTOIDLE)>; 147 ti,sysc-midle = <SYSC_IDLE_FORCE>, 148 <SYSC_IDLE_NO>, 149 <SYSC_IDLE_SMART>; 150 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 151 <SYSC_IDLE_NO>, 152 <SYSC_IDLE_SMART>; 153 ti,syss-mask = <1>; 154 /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */ 155 clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>; 156 clock-names = "fck"; 157 #address-cells = <1>; 158 #size-cells = <1>; 159 ranges = <0x0 0x56000 0x1000>; 160 161 sdma: dma-controller@0 { 162 compatible = "ti,omap4430-sdma", "ti,omap-sdma"; 163 reg = <0x0 0x1000>; 164 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 168 #dma-cells = <1>; 169 dma-channels = <32>; 170 dma-requests = <127>; 171 }; 172 }; 173 174 target-module@58000 { /* 0x4a058000, ap 10 0e.0 */ 175 compatible = "ti,sysc-omap2", "ti,sysc"; 176 reg = <0x58000 0x4>, 177 <0x58010 0x4>, 178 <0x58014 0x4>; 179 reg-names = "rev", "sysc", "syss"; 180 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 181 SYSC_OMAP2_SOFTRESET | 182 SYSC_OMAP2_AUTOIDLE)>; 183 ti,sysc-midle = <SYSC_IDLE_FORCE>, 184 <SYSC_IDLE_NO>, 185 <SYSC_IDLE_SMART>, 186 <SYSC_IDLE_SMART_WKUP>; 187 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 188 <SYSC_IDLE_NO>, 189 <SYSC_IDLE_SMART>, 190 <SYSC_IDLE_SMART_WKUP>; 191 ti,syss-mask = <1>; 192 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 193 clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; 194 clock-names = "fck"; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 ranges = <0x0 0x58000 0x5000>; 198 199 hsi: hsi@0 { 200 compatible = "ti,omap4-hsi"; 201 reg = <0x0 0x4000>, 202 <0x5000 0x1000>; 203 reg-names = "sys", "gdd"; 204 205 clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; 206 clock-names = "hsi_fck"; 207 208 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 209 interrupt-names = "gdd_mpu"; 210 211 #address-cells = <1>; 212 #size-cells = <1>; 213 ranges = <0 0 0x4000>; 214 215 hsi_port1: hsi-port@2000 { 216 compatible = "ti,omap4-hsi-port"; 217 reg = <0x2000 0x800>, 218 <0x2800 0x800>; 219 reg-names = "tx", "rx"; 220 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 221 }; 222 223 hsi_port2: hsi-port@3000 { 224 compatible = "ti,omap4-hsi-port"; 225 reg = <0x3000 0x800>, 226 <0x3800 0x800>; 227 reg-names = "tx", "rx"; 228 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 229 }; 230 }; 231 }; 232 233 target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */ 234 compatible = "ti,sysc"; 235 status = "disabled"; 236 #address-cells = <1>; 237 #size-cells = <1>; 238 ranges = <0x0 0x5e000 0x2000>; 239 }; 240 241 target-module@62000 { /* 0x4a062000, ap 11 16.0 */ 242 compatible = "ti,sysc-omap2", "ti,sysc"; 243 reg = <0x62000 0x4>, 244 <0x62010 0x4>, 245 <0x62014 0x4>; 246 reg-names = "rev", "sysc", "syss"; 247 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 248 SYSC_OMAP2_ENAWAKEUP | 249 SYSC_OMAP2_SOFTRESET | 250 SYSC_OMAP2_AUTOIDLE)>; 251 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 252 <SYSC_IDLE_NO>, 253 <SYSC_IDLE_SMART>; 254 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 255 clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>; 256 clock-names = "fck"; 257 #address-cells = <1>; 258 #size-cells = <1>; 259 ranges = <0x0 0x62000 0x1000>; 260 261 usbhstll: usbhstll@0 { 262 compatible = "ti,usbhs-tll"; 263 reg = <0x0 0x1000>; 264 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 265 }; 266 }; 267 268 target-module@64000 { /* 0x4a064000, ap 86 1e.0 */ 269 compatible = "ti,sysc-omap4", "ti,sysc"; 270 reg = <0x64000 0x4>, 271 <0x64010 0x4>, 272 <0x64014 0x4>; 273 reg-names = "rev", "sysc", "syss"; 274 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 275 ti,sysc-midle = <SYSC_IDLE_FORCE>, 276 <SYSC_IDLE_NO>, 277 <SYSC_IDLE_SMART>, 278 <SYSC_IDLE_SMART_WKUP>; 279 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 280 <SYSC_IDLE_NO>, 281 <SYSC_IDLE_SMART>, 282 <SYSC_IDLE_SMART_WKUP>; 283 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 284 clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>; 285 clock-names = "fck"; 286 #address-cells = <1>; 287 #size-cells = <1>; 288 ranges = <0x0 0x64000 0x1000>; 289 290 usbhshost: usbhshost@0 { 291 compatible = "ti,usbhs-host"; 292 reg = <0x0 0x800>; 293 #address-cells = <1>; 294 #size-cells = <1>; 295 ranges = <0 0 0x1000>; 296 clocks = <&init_60m_fclk>, 297 <&xclk60mhsp1_ck>, 298 <&xclk60mhsp2_ck>; 299 clock-names = "refclk_60m_int", 300 "refclk_60m_ext_p1", 301 "refclk_60m_ext_p2"; 302 303 usbhsohci: ohci@800 { 304 compatible = "ti,ohci-omap3"; 305 reg = <0x800 0x400>; 306 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 307 remote-wakeup-connected; 308 }; 309 310 usbhsehci: ehci@c00 { 311 compatible = "ti,ehci-omap"; 312 reg = <0xc00 0x400>; 313 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 314 }; 315 }; 316 }; 317 318 target-module@66000 { /* 0x4a066000, ap 25 26.0 */ 319 compatible = "ti,sysc-omap2", "ti,sysc"; 320 reg = <0x66000 0x4>, 321 <0x66010 0x4>, 322 <0x66014 0x4>; 323 reg-names = "rev", "sysc", "syss"; 324 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 325 SYSC_OMAP2_SOFTRESET | 326 SYSC_OMAP2_AUTOIDLE)>; 327 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 328 <SYSC_IDLE_NO>, 329 <SYSC_IDLE_SMART>; 330 /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */ 331 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; 332 clock-names = "fck"; 333 resets = <&prm_tesla 1>; 334 reset-names = "rstctrl"; 335 #address-cells = <1>; 336 #size-cells = <1>; 337 ranges = <0x0 0x66000 0x1000>; 338 339 mmu_dsp: mmu@0 { 340 compatible = "ti,omap4-iommu"; 341 reg = <0x0 0x100>; 342 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 343 #iommu-cells = <0>; 344 }; 345 }; 346 }; 347 348 segment@80000 { /* 0x4a080000 */ 349 compatible = "simple-bus"; 350 #address-cells = <1>; 351 #size-cells = <1>; 352 ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ 353 <0x0005a000 0x000da000 0x001000>, /* ap 14 */ 354 <0x0005b000 0x000db000 0x001000>, /* ap 15 */ 355 <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ 356 <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ 357 <0x0005e000 0x000de000 0x001000>, /* ap 18 */ 358 <0x00060000 0x000e0000 0x001000>, /* ap 19 */ 359 <0x00061000 0x000e1000 0x001000>, /* ap 20 */ 360 <0x00074000 0x000f4000 0x001000>, /* ap 27 */ 361 <0x00075000 0x000f5000 0x001000>, /* ap 28 */ 362 <0x00076000 0x000f6000 0x001000>, /* ap 29 */ 363 <0x00077000 0x000f7000 0x001000>, /* ap 30 */ 364 <0x00036000 0x000b6000 0x001000>, /* ap 69 */ 365 <0x00037000 0x000b7000 0x001000>, /* ap 70 */ 366 <0x0004d000 0x000cd000 0x001000>, /* ap 78 */ 367 <0x0004e000 0x000ce000 0x001000>, /* ap 79 */ 368 <0x00029000 0x000a9000 0x001000>, /* ap 82 */ 369 <0x0002a000 0x000aa000 0x001000>, /* ap 83 */ 370 <0x0002b000 0x000ab000 0x001000>, /* ap 84 */ 371 <0x0002c000 0x000ac000 0x001000>, /* ap 85 */ 372 <0x0002d000 0x000ad000 0x001000>, /* ap 88 */ 373 <0x0002e000 0x000ae000 0x001000>; /* ap 89 */ 374 375 target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */ 376 compatible = "ti,sysc"; 377 status = "disabled"; 378 #address-cells = <1>; 379 #size-cells = <1>; 380 ranges = <0x0 0x29000 0x1000>; 381 }; 382 383 target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ 384 compatible = "ti,sysc-omap2", "ti,sysc"; 385 reg = <0x2b400 0x4>, 386 <0x2b404 0x4>, 387 <0x2b408 0x4>; 388 reg-names = "rev", "sysc", "syss"; 389 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 390 SYSC_OMAP2_SOFTRESET | 391 SYSC_OMAP2_AUTOIDLE)>; 392 ti,sysc-midle = <SYSC_IDLE_FORCE>, 393 <SYSC_IDLE_NO>, 394 <SYSC_IDLE_SMART>; 395 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 396 <SYSC_IDLE_NO>, 397 <SYSC_IDLE_SMART>, 398 <SYSC_IDLE_SMART_WKUP>; 399 ti,syss-mask = <1>; 400 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 401 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; 402 clock-names = "fck"; 403 #address-cells = <1>; 404 #size-cells = <1>; 405 ranges = <0x0 0x2b000 0x1000>; 406 407 usb_otg_hs: usb_otg_hs@0 { 408 compatible = "ti,omap4-musb"; 409 reg = <0x0 0x7ff>; 410 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 411 interrupt-names = "mc", "dma"; 412 usb-phy = <&usb2_phy>; 413 phys = <&usb2_phy>; 414 phy-names = "usb2-phy"; 415 multipoint = <1>; 416 num-eps = <16>; 417 ram-bits = <12>; 418 ctrl-module = <&omap_control_usbotg>; 419 }; 420 }; 421 422 target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */ 423 compatible = "ti,sysc-omap2", "ti,sysc"; 424 reg = <0x2d000 0x4>, 425 <0x2d010 0x4>, 426 <0x2d014 0x4>; 427 reg-names = "rev", "sysc", "syss"; 428 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 429 SYSC_OMAP2_AUTOIDLE)>; 430 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 431 <SYSC_IDLE_NO>, 432 <SYSC_IDLE_SMART>; 433 ti,syss-mask = <1>; 434 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 435 clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>; 436 clock-names = "fck"; 437 #address-cells = <1>; 438 #size-cells = <1>; 439 ranges = <0x0 0x2d000 0x1000>; 440 441 ocp2scp@0 { 442 compatible = "ti,omap-ocp2scp"; 443 reg = <0x0 0x1f>; 444 #address-cells = <1>; 445 #size-cells = <1>; 446 ranges = <0 0 0x1000>; 447 usb2_phy: usb2phy@80 { 448 compatible = "ti,omap-usb2"; 449 reg = <0x80 0x58>; 450 ctrl-module = <&omap_control_usb2phy>; 451 clocks = <&usb_phy_cm_clk32k>; 452 clock-names = "wkupclk"; 453 #phy-cells = <0>; 454 }; 455 }; 456 }; 457 458 /* d2d mdm */ 459 target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */ 460 compatible = "ti,sysc-omap2", "ti,sysc"; 461 reg = <0x36000 0x4>, 462 <0x36010 0x4>, 463 <0x36014 0x4>; 464 reg-names = "rev", "sysc", "syss"; 465 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; 466 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 467 <SYSC_IDLE_NO>, 468 <SYSC_IDLE_SMART>, 469 <SYSC_IDLE_SMART_WKUP>; 470 ti,syss-mask = <1>; 471 /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ 472 clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>; 473 clock-names = "fck"; 474 #address-cells = <1>; 475 #size-cells = <1>; 476 ranges = <0x0 0x36000 0x1000>; 477 }; 478 479 /* d2d mpu */ 480 target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */ 481 compatible = "ti,sysc-omap2", "ti,sysc"; 482 reg = <0x4d000 0x4>, 483 <0x4d010 0x4>, 484 <0x4d014 0x4>; 485 reg-names = "rev", "sysc", "syss"; 486 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; 487 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 488 <SYSC_IDLE_NO>, 489 <SYSC_IDLE_SMART>, 490 <SYSC_IDLE_SMART_WKUP>; 491 ti,syss-mask = <1>; 492 /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ 493 clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>; 494 clock-names = "fck"; 495 #address-cells = <1>; 496 #size-cells = <1>; 497 ranges = <0x0 0x4d000 0x1000>; 498 }; 499 500 target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */ 501 compatible = "ti,sysc-omap4-sr", "ti,sysc"; 502 reg = <0x59038 0x4>; 503 reg-names = "sysc"; 504 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 505 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 506 <SYSC_IDLE_NO>, 507 <SYSC_IDLE_SMART>, 508 <SYSC_IDLE_SMART_WKUP>; 509 /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ 510 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>; 511 clock-names = "fck"; 512 #address-cells = <1>; 513 #size-cells = <1>; 514 ranges = <0x0 0x59000 0x1000>; 515 516 smartreflex_mpu: smartreflex@0 { 517 compatible = "ti,omap4-smartreflex-mpu"; 518 reg = <0x0 0x80>; 519 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 520 }; 521 }; 522 523 target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */ 524 compatible = "ti,sysc-omap4-sr", "ti,sysc"; 525 reg = <0x5b038 0x4>; 526 reg-names = "sysc"; 527 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 528 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 529 <SYSC_IDLE_NO>, 530 <SYSC_IDLE_SMART>, 531 <SYSC_IDLE_SMART_WKUP>; 532 /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ 533 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>; 534 clock-names = "fck"; 535 #address-cells = <1>; 536 #size-cells = <1>; 537 ranges = <0x0 0x5b000 0x1000>; 538 539 smartreflex_iva: smartreflex@0 { 540 compatible = "ti,omap4-smartreflex-iva"; 541 reg = <0x0 0x80>; 542 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 543 }; 544 }; 545 546 target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */ 547 compatible = "ti,sysc-omap4-sr", "ti,sysc"; 548 reg = <0x5d038 0x4>; 549 reg-names = "sysc"; 550 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 551 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 552 <SYSC_IDLE_NO>, 553 <SYSC_IDLE_SMART>, 554 <SYSC_IDLE_SMART_WKUP>; 555 /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ 556 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>; 557 clock-names = "fck"; 558 #address-cells = <1>; 559 #size-cells = <1>; 560 ranges = <0x0 0x5d000 0x1000>; 561 562 smartreflex_core: smartreflex@0 { 563 compatible = "ti,omap4-smartreflex-core"; 564 reg = <0x0 0x80>; 565 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 566 }; 567 }; 568 569 target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */ 570 compatible = "ti,sysc"; 571 status = "disabled"; 572 #address-cells = <1>; 573 #size-cells = <1>; 574 ranges = <0x0 0x60000 0x1000>; 575 }; 576 577 target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */ 578 compatible = "ti,sysc-omap4", "ti,sysc"; 579 reg = <0x74000 0x4>, 580 <0x74010 0x4>; 581 reg-names = "rev", "sysc"; 582 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 583 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 584 <SYSC_IDLE_NO>, 585 <SYSC_IDLE_SMART>; 586 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ 587 clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>; 588 clock-names = "fck"; 589 #address-cells = <1>; 590 #size-cells = <1>; 591 ranges = <0x0 0x74000 0x1000>; 592 593 mailbox: mailbox@0 { 594 compatible = "ti,omap4-mailbox"; 595 reg = <0x0 0x200>; 596 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 597 #mbox-cells = <1>; 598 ti,mbox-num-users = <3>; 599 ti,mbox-num-fifos = <8>; 600 mbox_ipu: mbox-ipu { 601 ti,mbox-tx = <0 0 0>; 602 ti,mbox-rx = <1 0 0>; 603 }; 604 mbox_dsp: mbox-dsp { 605 ti,mbox-tx = <3 0 0>; 606 ti,mbox-rx = <2 0 0>; 607 }; 608 }; 609 }; 610 611 target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */ 612 compatible = "ti,sysc-omap2", "ti,sysc"; 613 reg = <0x76000 0x4>, 614 <0x76010 0x4>, 615 <0x76014 0x4>; 616 reg-names = "rev", "sysc", "syss"; 617 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 618 SYSC_OMAP2_ENAWAKEUP | 619 SYSC_OMAP2_SOFTRESET | 620 SYSC_OMAP2_AUTOIDLE)>; 621 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 622 <SYSC_IDLE_NO>, 623 <SYSC_IDLE_SMART>; 624 ti,syss-mask = <1>; 625 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ 626 clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>; 627 clock-names = "fck"; 628 #address-cells = <1>; 629 #size-cells = <1>; 630 ranges = <0x0 0x76000 0x1000>; 631 632 hwspinlock: spinlock@0 { 633 compatible = "ti,omap4-hwspinlock"; 634 reg = <0x0 0x1000>; 635 #hwlock-cells = <1>; 636 }; 637 }; 638 }; 639 640 segment@100000 { /* 0x4a100000 */ 641 compatible = "simple-bus"; 642 #address-cells = <1>; 643 #size-cells = <1>; 644 ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */ 645 <0x00001000 0x00101000 0x001000>, /* ap 22 */ 646 <0x00002000 0x00102000 0x001000>, /* ap 61 */ 647 <0x00003000 0x00103000 0x001000>, /* ap 62 */ 648 <0x00008000 0x00108000 0x001000>, /* ap 63 */ 649 <0x00009000 0x00109000 0x001000>, /* ap 64 */ 650 <0x0000a000 0x0010a000 0x001000>, /* ap 65 */ 651 <0x0000b000 0x0010b000 0x001000>; /* ap 66 */ 652 653 target-module@0 { /* 0x4a100000, ap 21 2a.0 */ 654 compatible = "ti,sysc-omap4", "ti,sysc"; 655 ti,hwmods = "ctrl_module_pad_core"; 656 reg = <0x0 0x4>, 657 <0x10 0x4>; 658 reg-names = "rev", "sysc"; 659 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 660 <SYSC_IDLE_NO>, 661 <SYSC_IDLE_SMART>, 662 <SYSC_IDLE_SMART_WKUP>; 663 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ 664 #address-cells = <1>; 665 #size-cells = <1>; 666 ranges = <0x0 0x0 0x1000>; 667 668 omap4_pmx_core: pinmux@40 { 669 compatible = "ti,omap4-padconf", 670 "pinctrl-single"; 671 reg = <0x40 0x0196>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 #pinctrl-cells = <1>; 675 #interrupt-cells = <1>; 676 interrupt-controller; 677 pinctrl-single,register-width = <16>; 678 pinctrl-single,function-mask = <0x7fff>; 679 }; 680 681 omap4_padconf_global: omap4_padconf_global@5a0 { 682 compatible = "syscon", 683 "simple-bus"; 684 reg = <0x5a0 0x170>; 685 #address-cells = <1>; 686 #size-cells = <1>; 687 ranges = <0 0x5a0 0x170>; 688 689 pbias_regulator: pbias_regulator@60 { 690 compatible = "ti,pbias-omap4", "ti,pbias-omap"; 691 reg = <0x60 0x4>; 692 syscon = <&omap4_padconf_global>; 693 pbias_mmc_reg: pbias_mmc_omap4 { 694 regulator-name = "pbias_mmc_omap4"; 695 regulator-min-microvolt = <1800000>; 696 regulator-max-microvolt = <3000000>; 697 }; 698 }; 699 }; 700 }; 701 702 target-module@2000 { /* 0x4a102000, ap 61 3c.0 */ 703 compatible = "ti,sysc"; 704 status = "disabled"; 705 #address-cells = <1>; 706 #size-cells = <1>; 707 ranges = <0x0 0x2000 0x1000>; 708 }; 709 710 target-module@8000 { /* 0x4a108000, ap 63 62.0 */ 711 compatible = "ti,sysc"; 712 status = "disabled"; 713 #address-cells = <1>; 714 #size-cells = <1>; 715 ranges = <0x0 0x8000 0x1000>; 716 }; 717 718 target-module@a000 { /* 0x4a10a000, ap 65 50.0 */ 719 compatible = "ti,sysc-omap4", "ti,sysc"; 720 reg = <0xa000 0x4>, 721 <0xa010 0x4>; 722 reg-names = "rev", "sysc"; 723 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 724 ti,sysc-midle = <SYSC_IDLE_FORCE>, 725 <SYSC_IDLE_NO>, 726 <SYSC_IDLE_SMART>; 727 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 728 <SYSC_IDLE_NO>, 729 <SYSC_IDLE_SMART>; 730 ti,sysc-delay-us = <2>; 731 /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */ 732 clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>; 733 clock-names = "fck"; 734 #address-cells = <1>; 735 #size-cells = <1>; 736 ranges = <0x0 0xa000 0x1000>; 737 738 /* No child device binding or driver in mainline */ 739 }; 740 }; 741 742 segment@180000 { /* 0x4a180000 */ 743 compatible = "simple-bus"; 744 #address-cells = <1>; 745 #size-cells = <1>; 746 }; 747 748 segment@200000 { /* 0x4a200000 */ 749 compatible = "simple-bus"; 750 #address-cells = <1>; 751 #size-cells = <1>; 752 ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */ 753 <0x0001f000 0x0021f000 0x001000>, /* ap 32 */ 754 <0x0000a000 0x0020a000 0x001000>, /* ap 33 */ 755 <0x0000b000 0x0020b000 0x001000>, /* ap 34 */ 756 <0x00004000 0x00204000 0x001000>, /* ap 35 */ 757 <0x00005000 0x00205000 0x001000>, /* ap 36 */ 758 <0x00006000 0x00206000 0x001000>, /* ap 37 */ 759 <0x00007000 0x00207000 0x001000>, /* ap 38 */ 760 <0x00012000 0x00212000 0x001000>, /* ap 39 */ 761 <0x00013000 0x00213000 0x001000>, /* ap 40 */ 762 <0x0000c000 0x0020c000 0x001000>, /* ap 41 */ 763 <0x0000d000 0x0020d000 0x001000>, /* ap 42 */ 764 <0x00010000 0x00210000 0x001000>, /* ap 43 */ 765 <0x00011000 0x00211000 0x001000>, /* ap 44 */ 766 <0x00016000 0x00216000 0x001000>, /* ap 45 */ 767 <0x00017000 0x00217000 0x001000>, /* ap 46 */ 768 <0x00014000 0x00214000 0x001000>, /* ap 47 */ 769 <0x00015000 0x00215000 0x001000>, /* ap 48 */ 770 <0x00018000 0x00218000 0x001000>, /* ap 49 */ 771 <0x00019000 0x00219000 0x001000>, /* ap 50 */ 772 <0x00020000 0x00220000 0x001000>, /* ap 51 */ 773 <0x00021000 0x00221000 0x001000>, /* ap 52 */ 774 <0x00026000 0x00226000 0x001000>, /* ap 53 */ 775 <0x00027000 0x00227000 0x001000>, /* ap 54 */ 776 <0x00028000 0x00228000 0x001000>, /* ap 55 */ 777 <0x00029000 0x00229000 0x001000>, /* ap 56 */ 778 <0x0002a000 0x0022a000 0x001000>, /* ap 57 */ 779 <0x0002b000 0x0022b000 0x001000>, /* ap 58 */ 780 <0x0001c000 0x0021c000 0x001000>, /* ap 59 */ 781 <0x0001d000 0x0021d000 0x001000>; /* ap 60 */ 782 783 target-module@4000 { /* 0x4a204000, ap 35 42.0 */ 784 compatible = "ti,sysc"; 785 status = "disabled"; 786 #address-cells = <1>; 787 #size-cells = <1>; 788 ranges = <0x0 0x4000 0x1000>; 789 }; 790 791 target-module@6000 { /* 0x4a206000, ap 37 4a.0 */ 792 compatible = "ti,sysc"; 793 status = "disabled"; 794 #address-cells = <1>; 795 #size-cells = <1>; 796 ranges = <0x0 0x6000 0x1000>; 797 }; 798 799 target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */ 800 compatible = "ti,sysc"; 801 status = "disabled"; 802 #address-cells = <1>; 803 #size-cells = <1>; 804 ranges = <0x0 0xa000 0x1000>; 805 }; 806 807 target-module@c000 { /* 0x4a20c000, ap 41 20.0 */ 808 compatible = "ti,sysc"; 809 status = "disabled"; 810 #address-cells = <1>; 811 #size-cells = <1>; 812 ranges = <0x0 0xc000 0x1000>; 813 }; 814 815 target-module@10000 { /* 0x4a210000, ap 43 52.0 */ 816 compatible = "ti,sysc"; 817 status = "disabled"; 818 #address-cells = <1>; 819 #size-cells = <1>; 820 ranges = <0x0 0x10000 0x1000>; 821 }; 822 823 target-module@12000 { /* 0x4a212000, ap 39 18.0 */ 824 compatible = "ti,sysc"; 825 status = "disabled"; 826 #address-cells = <1>; 827 #size-cells = <1>; 828 ranges = <0x0 0x12000 0x1000>; 829 }; 830 831 target-module@14000 { /* 0x4a214000, ap 47 30.0 */ 832 compatible = "ti,sysc"; 833 status = "disabled"; 834 #address-cells = <1>; 835 #size-cells = <1>; 836 ranges = <0x0 0x14000 0x1000>; 837 }; 838 839 target-module@16000 { /* 0x4a216000, ap 45 28.0 */ 840 compatible = "ti,sysc"; 841 status = "disabled"; 842 #address-cells = <1>; 843 #size-cells = <1>; 844 ranges = <0x0 0x16000 0x1000>; 845 }; 846 847 target-module@18000 { /* 0x4a218000, ap 49 38.0 */ 848 compatible = "ti,sysc"; 849 status = "disabled"; 850 #address-cells = <1>; 851 #size-cells = <1>; 852 ranges = <0x0 0x18000 0x1000>; 853 }; 854 855 target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */ 856 compatible = "ti,sysc"; 857 status = "disabled"; 858 #address-cells = <1>; 859 #size-cells = <1>; 860 ranges = <0x0 0x1c000 0x1000>; 861 }; 862 863 target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */ 864 compatible = "ti,sysc"; 865 status = "disabled"; 866 #address-cells = <1>; 867 #size-cells = <1>; 868 ranges = <0x0 0x1e000 0x1000>; 869 }; 870 871 target-module@20000 { /* 0x4a220000, ap 51 40.0 */ 872 compatible = "ti,sysc"; 873 status = "disabled"; 874 #address-cells = <1>; 875 #size-cells = <1>; 876 ranges = <0x0 0x20000 0x1000>; 877 }; 878 879 target-module@26000 { /* 0x4a226000, ap 53 34.0 */ 880 compatible = "ti,sysc"; 881 status = "disabled"; 882 #address-cells = <1>; 883 #size-cells = <1>; 884 ranges = <0x0 0x26000 0x1000>; 885 }; 886 887 target-module@28000 { /* 0x4a228000, ap 55 2e.0 */ 888 compatible = "ti,sysc"; 889 status = "disabled"; 890 #address-cells = <1>; 891 #size-cells = <1>; 892 ranges = <0x0 0x28000 0x1000>; 893 }; 894 895 target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */ 896 compatible = "ti,sysc"; 897 status = "disabled"; 898 #address-cells = <1>; 899 #size-cells = <1>; 900 ranges = <0x0 0x2a000 0x1000>; 901 }; 902 }; 903 904 segment@280000 { /* 0x4a280000 */ 905 compatible = "simple-bus"; 906 #address-cells = <1>; 907 #size-cells = <1>; 908 }; 909 910 l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */ 911 compatible = "simple-bus"; 912 #address-cells = <1>; 913 #size-cells = <1>; 914 ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ 915 <0x00040000 0x00340000 0x001000>, /* ap 68 */ 916 <0x00020000 0x00320000 0x004000>, /* ap 71 */ 917 <0x00024000 0x00324000 0x002000>, /* ap 72 */ 918 <0x00026000 0x00326000 0x001000>, /* ap 73 */ 919 <0x00027000 0x00327000 0x001000>, /* ap 74 */ 920 <0x00028000 0x00328000 0x001000>, /* ap 75 */ 921 <0x00029000 0x00329000 0x001000>, /* ap 76 */ 922 <0x00030000 0x00330000 0x010000>, /* ap 77 */ 923 <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ 924 <0x0002c000 0x0032c000 0x004000>; /* ap 91 */ 925 926 l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */ 927 compatible = "ti,sysc"; 928 status = "disabled"; 929 #address-cells = <1>; 930 #size-cells = <1>; 931 ranges = <0x00000000 0x00000000 0x00020000>, 932 <0x00020000 0x00020000 0x00004000>, 933 <0x00024000 0x00024000 0x00002000>, 934 <0x00026000 0x00026000 0x00001000>, 935 <0x00027000 0x00027000 0x00001000>, 936 <0x00028000 0x00028000 0x00001000>, 937 <0x00029000 0x00029000 0x00001000>, 938 <0x0002a000 0x0002a000 0x00002000>, 939 <0x0002c000 0x0002c000 0x00004000>, 940 <0x00030000 0x00030000 0x00010000>; 941 }; 942 }; 943}; 944 945&l4_wkup { /* 0x4a300000 */ 946 compatible = "ti,omap4-l4-wkup", "simple-bus"; 947 reg = <0x4a300000 0x800>, 948 <0x4a300800 0x800>, 949 <0x4a301000 0x1000>; 950 reg-names = "ap", "la", "ia0"; 951 #address-cells = <1>; 952 #size-cells = <1>; 953 ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */ 954 <0x00010000 0x4a310000 0x010000>, /* segment 1 */ 955 <0x00020000 0x4a320000 0x010000>; /* segment 2 */ 956 957 segment@0 { /* 0x4a300000 */ 958 compatible = "simple-bus"; 959 #address-cells = <1>; 960 #size-cells = <1>; 961 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 962 <0x00001000 0x00001000 0x001000>, /* ap 1 */ 963 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 964 <0x00006000 0x00006000 0x002000>, /* ap 3 */ 965 <0x00008000 0x00008000 0x001000>, /* ap 4 */ 966 <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ 967 <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ 968 <0x00004000 0x00004000 0x001000>, /* ap 17 */ 969 <0x00005000 0x00005000 0x001000>, /* ap 18 */ 970 <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ 971 <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ 972 973 target-module@4000 { /* 0x4a304000, ap 17 24.0 */ 974 compatible = "ti,sysc-omap2", "ti,sysc"; 975 reg = <0x4000 0x4>, 976 <0x4004 0x4>; 977 reg-names = "rev", "sysc"; 978 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 979 <SYSC_IDLE_NO>; 980 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ 981 clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>; 982 clock-names = "fck"; 983 #address-cells = <1>; 984 #size-cells = <1>; 985 ranges = <0x0 0x4000 0x1000>; 986 987 counter32k: counter@0 { 988 compatible = "ti,omap-counter32k"; 989 reg = <0x0 0x20>; 990 }; 991 }; 992 993 target-module@6000 { /* 0x4a306000, ap 3 08.0 */ 994 compatible = "ti,sysc-omap4", "ti,sysc"; 995 reg = <0x6000 0x4>; 996 reg-names = "rev"; 997 #address-cells = <1>; 998 #size-cells = <1>; 999 ranges = <0x0 0x6000 0x2000>; 1000 1001 prm: prm@0 { 1002 compatible = "ti,omap4-prm", "simple-bus"; 1003 reg = <0x0 0x2000>; 1004 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1005 #address-cells = <1>; 1006 #size-cells = <1>; 1007 ranges = <0 0 0x2000>; 1008 1009 prm_clocks: clocks { 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 }; 1013 1014 prm_clockdomains: clockdomains { 1015 }; 1016 }; 1017 }; 1018 1019 target-module@a000 { /* 0x4a30a000, ap 15 34.0 */ 1020 compatible = "ti,sysc-omap4", "ti,sysc"; 1021 reg = <0xa000 0x4>; 1022 reg-names = "rev"; 1023 #address-cells = <1>; 1024 #size-cells = <1>; 1025 ranges = <0x0 0xa000 0x1000>; 1026 1027 scrm: scrm@0 { 1028 compatible = "ti,omap4-scrm"; 1029 reg = <0x0 0x2000>; 1030 1031 scrm_clocks: clocks { 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 }; 1035 1036 scrm_clockdomains: clockdomains { 1037 }; 1038 }; 1039 }; 1040 1041 target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */ 1042 compatible = "ti,sysc-omap4", "ti,sysc"; 1043 ti,hwmods = "ctrl_module_wkup"; 1044 reg = <0xc000 0x4>, 1045 <0xc010 0x4>; 1046 reg-names = "rev", "sysc"; 1047 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1048 <SYSC_IDLE_NO>, 1049 <SYSC_IDLE_SMART>, 1050 <SYSC_IDLE_SMART_WKUP>; 1051 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ 1052 #address-cells = <1>; 1053 #size-cells = <1>; 1054 ranges = <0x0 0xc000 0x1000>; 1055 1056 omap4_scm_wkup: scm@c000 { 1057 compatible = "ti,omap4-scm-wkup"; 1058 reg = <0xc000 0x1000>; 1059 }; 1060 }; 1061 }; 1062 1063 segment@10000 { /* 0x4a310000 */ 1064 compatible = "simple-bus"; 1065 #address-cells = <1>; 1066 #size-cells = <1>; 1067 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ 1068 <0x00001000 0x00011000 0x001000>, /* ap 6 */ 1069 <0x00004000 0x00014000 0x001000>, /* ap 7 */ 1070 <0x00005000 0x00015000 0x001000>, /* ap 8 */ 1071 <0x00008000 0x00018000 0x001000>, /* ap 9 */ 1072 <0x00009000 0x00019000 0x001000>, /* ap 10 */ 1073 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ 1074 <0x0000d000 0x0001d000 0x001000>, /* ap 12 */ 1075 <0x0000e000 0x0001e000 0x001000>, /* ap 21 */ 1076 <0x0000f000 0x0001f000 0x001000>; /* ap 22 */ 1077 1078 gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */ 1079 compatible = "ti,sysc-omap2", "ti,sysc"; 1080 reg = <0x0 0x4>, 1081 <0x10 0x4>, 1082 <0x114 0x4>; 1083 reg-names = "rev", "sysc", "syss"; 1084 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1085 SYSC_OMAP2_SOFTRESET | 1086 SYSC_OMAP2_AUTOIDLE)>; 1087 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1088 <SYSC_IDLE_NO>, 1089 <SYSC_IDLE_SMART>, 1090 <SYSC_IDLE_SMART_WKUP>; 1091 ti,syss-mask = <1>; 1092 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ 1093 clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>, 1094 <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 8>; 1095 clock-names = "fck", "dbclk"; 1096 #address-cells = <1>; 1097 #size-cells = <1>; 1098 ranges = <0x0 0x0 0x1000>; 1099 1100 gpio1: gpio@0 { 1101 compatible = "ti,omap4-gpio"; 1102 reg = <0x0 0x200>; 1103 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1104 ti,gpio-always-on; 1105 gpio-controller; 1106 #gpio-cells = <2>; 1107 interrupt-controller; 1108 #interrupt-cells = <2>; 1109 }; 1110 }; 1111 1112 target-module@4000 { /* 0x4a314000, ap 7 18.0 */ 1113 compatible = "ti,sysc-omap2", "ti,sysc"; 1114 reg = <0x4000 0x4>, 1115 <0x4010 0x4>, 1116 <0x4014 0x4>; 1117 reg-names = "rev", "sysc", "syss"; 1118 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 1119 SYSC_OMAP2_SOFTRESET)>; 1120 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1121 <SYSC_IDLE_NO>, 1122 <SYSC_IDLE_SMART>, 1123 <SYSC_IDLE_SMART_WKUP>; 1124 ti,syss-mask = <1>; 1125 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ 1126 clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>; 1127 clock-names = "fck"; 1128 #address-cells = <1>; 1129 #size-cells = <1>; 1130 ranges = <0x0 0x4000 0x1000>; 1131 1132 wdt2: wdt@0 { 1133 compatible = "ti,omap4-wdt", "ti,omap3-wdt"; 1134 reg = <0x0 0x80>; 1135 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1136 }; 1137 }; 1138 1139 timer1_target: target-module@8000 { /* 0x4a318000, ap 9 1c.0 */ 1140 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 1141 reg = <0x8000 0x4>, 1142 <0x8010 0x4>, 1143 <0x8014 0x4>; 1144 reg-names = "rev", "sysc", "syss"; 1145 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1146 SYSC_OMAP2_EMUFREE | 1147 SYSC_OMAP2_ENAWAKEUP | 1148 SYSC_OMAP2_SOFTRESET | 1149 SYSC_OMAP2_AUTOIDLE)>; 1150 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1151 <SYSC_IDLE_NO>, 1152 <SYSC_IDLE_SMART>; 1153 ti,syss-mask = <1>; 1154 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ 1155 clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>; 1156 clock-names = "fck"; 1157 #address-cells = <1>; 1158 #size-cells = <1>; 1159 ranges = <0x0 0x8000 0x1000>; 1160 1161 timer1: timer@0 { 1162 compatible = "ti,omap3430-timer"; 1163 reg = <0x0 0x80>; 1164 clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>, 1165 <&sys_clkin_ck>; 1166 clock-names = "fck", "timer_sys_ck"; 1167 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1168 ti,timer-alwon; 1169 }; 1170 }; 1171 1172 target-module@c000 { /* 0x4a31c000, ap 11 20.0 */ 1173 compatible = "ti,sysc-omap2", "ti,sysc"; 1174 reg = <0xc000 0x4>, 1175 <0xc010 0x4>, 1176 <0xc014 0x4>; 1177 reg-names = "rev", "sysc", "syss"; 1178 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1179 SYSC_OMAP2_EMUFREE | 1180 SYSC_OMAP2_ENAWAKEUP | 1181 SYSC_OMAP2_SOFTRESET | 1182 SYSC_OMAP2_AUTOIDLE)>; 1183 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1184 <SYSC_IDLE_NO>, 1185 <SYSC_IDLE_SMART>; 1186 ti,syss-mask = <1>; 1187 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ 1188 clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>; 1189 clock-names = "fck"; 1190 #address-cells = <1>; 1191 #size-cells = <1>; 1192 ranges = <0x0 0xc000 0x1000>; 1193 1194 keypad: keypad@0 { 1195 compatible = "ti,omap4-keypad"; 1196 reg = <0x0 0x80>; 1197 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1198 reg-names = "mpu"; 1199 }; 1200 }; 1201 1202 target-module@e000 { /* 0x4a31e000, ap 21 30.0 */ 1203 compatible = "ti,sysc-omap4", "ti,sysc"; 1204 ti,hwmods = "ctrl_module_pad_wkup"; 1205 reg = <0xe000 0x4>, 1206 <0xe010 0x4>; 1207 reg-names = "rev", "sysc"; 1208 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1209 <SYSC_IDLE_NO>, 1210 <SYSC_IDLE_SMART>, 1211 <SYSC_IDLE_SMART_WKUP>; 1212 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ 1213 #address-cells = <1>; 1214 #size-cells = <1>; 1215 ranges = <0x0 0xe000 0x1000>; 1216 1217 omap4_pmx_wkup: pinmux@40 { 1218 compatible = "ti,omap4-padconf", 1219 "pinctrl-single"; 1220 reg = <0x40 0x0038>; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 #pinctrl-cells = <1>; 1224 #interrupt-cells = <1>; 1225 interrupt-controller; 1226 pinctrl-single,register-width = <16>; 1227 pinctrl-single,function-mask = <0x7fff>; 1228 }; 1229 }; 1230 }; 1231 1232 segment@20000 { /* 0x4a320000 */ 1233 compatible = "simple-bus"; 1234 #address-cells = <1>; 1235 #size-cells = <1>; 1236 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ 1237 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ 1238 <0x00000000 0x00020000 0x001000>, /* ap 23 */ 1239 <0x00001000 0x00021000 0x001000>, /* ap 24 */ 1240 <0x00002000 0x00022000 0x001000>, /* ap 25 */ 1241 <0x00003000 0x00023000 0x001000>, /* ap 26 */ 1242 <0x00004000 0x00024000 0x001000>, /* ap 27 */ 1243 <0x00005000 0x00025000 0x001000>, /* ap 28 */ 1244 <0x00007000 0x00027000 0x000400>, /* ap 29 */ 1245 <0x00008000 0x00028000 0x000800>, /* ap 30 */ 1246 <0x00009000 0x00029000 0x000400>; /* ap 31 */ 1247 1248 target-module@0 { /* 0x4a320000, ap 23 04.0 */ 1249 compatible = "ti,sysc"; 1250 status = "disabled"; 1251 #address-cells = <1>; 1252 #size-cells = <1>; 1253 ranges = <0x0 0x0 0x1000>; 1254 }; 1255 1256 target-module@2000 { /* 0x4a322000, ap 25 0c.0 */ 1257 compatible = "ti,sysc"; 1258 status = "disabled"; 1259 #address-cells = <1>; 1260 #size-cells = <1>; 1261 ranges = <0x0 0x2000 0x1000>; 1262 }; 1263 1264 target-module@4000 { /* 0x4a324000, ap 27 10.0 */ 1265 compatible = "ti,sysc"; 1266 status = "disabled"; 1267 #address-cells = <1>; 1268 #size-cells = <1>; 1269 ranges = <0x0 0x4000 0x1000>; 1270 }; 1271 1272 target-module@6000 { /* 0x4a326000, ap 13 28.0 */ 1273 compatible = "ti,sysc"; 1274 status = "disabled"; 1275 #address-cells = <1>; 1276 #size-cells = <1>; 1277 ranges = <0x00000000 0x00006000 0x00001000>, 1278 <0x00001000 0x00007000 0x00000400>, 1279 <0x00002000 0x00008000 0x00000800>, 1280 <0x00003000 0x00009000 0x00000400>; 1281 }; 1282 }; 1283}; 1284 1285&l4_per { /* 0x48000000 */ 1286 compatible = "ti,omap4-l4-per", "simple-bus"; 1287 reg = <0x48000000 0x800>, 1288 <0x48000800 0x800>, 1289 <0x48001000 0x400>, 1290 <0x48001400 0x400>, 1291 <0x48001800 0x400>, 1292 <0x48001c00 0x400>; 1293 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; 1294 #address-cells = <1>; 1295 #size-cells = <1>; 1296 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ 1297 <0x00200000 0x48200000 0x200000>; /* segment 1 */ 1298 1299 segment@0 { /* 0x48000000 */ 1300 compatible = "simple-bus"; 1301 #address-cells = <1>; 1302 #size-cells = <1>; 1303 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 1304 <0x00001000 0x00001000 0x000400>, /* ap 1 */ 1305 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 1306 <0x00020000 0x00020000 0x001000>, /* ap 3 */ 1307 <0x00021000 0x00021000 0x001000>, /* ap 4 */ 1308 <0x00032000 0x00032000 0x001000>, /* ap 5 */ 1309 <0x00033000 0x00033000 0x001000>, /* ap 6 */ 1310 <0x00034000 0x00034000 0x001000>, /* ap 7 */ 1311 <0x00035000 0x00035000 0x001000>, /* ap 8 */ 1312 <0x00036000 0x00036000 0x001000>, /* ap 9 */ 1313 <0x00037000 0x00037000 0x001000>, /* ap 10 */ 1314 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ 1315 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ 1316 <0x00040000 0x00040000 0x010000>, /* ap 13 */ 1317 <0x00050000 0x00050000 0x001000>, /* ap 14 */ 1318 <0x00055000 0x00055000 0x001000>, /* ap 15 */ 1319 <0x00056000 0x00056000 0x001000>, /* ap 16 */ 1320 <0x00057000 0x00057000 0x001000>, /* ap 17 */ 1321 <0x00058000 0x00058000 0x001000>, /* ap 18 */ 1322 <0x00059000 0x00059000 0x001000>, /* ap 19 */ 1323 <0x0005a000 0x0005a000 0x001000>, /* ap 20 */ 1324 <0x0005b000 0x0005b000 0x001000>, /* ap 21 */ 1325 <0x0005c000 0x0005c000 0x001000>, /* ap 22 */ 1326 <0x0005d000 0x0005d000 0x001000>, /* ap 23 */ 1327 <0x0005e000 0x0005e000 0x001000>, /* ap 24 */ 1328 <0x00060000 0x00060000 0x001000>, /* ap 25 */ 1329 <0x0006a000 0x0006a000 0x001000>, /* ap 26 */ 1330 <0x0006b000 0x0006b000 0x001000>, /* ap 27 */ 1331 <0x0006c000 0x0006c000 0x001000>, /* ap 28 */ 1332 <0x0006d000 0x0006d000 0x001000>, /* ap 29 */ 1333 <0x0006e000 0x0006e000 0x001000>, /* ap 30 */ 1334 <0x0006f000 0x0006f000 0x001000>, /* ap 31 */ 1335 <0x00070000 0x00070000 0x001000>, /* ap 32 */ 1336 <0x00071000 0x00071000 0x001000>, /* ap 33 */ 1337 <0x00072000 0x00072000 0x001000>, /* ap 34 */ 1338 <0x00073000 0x00073000 0x001000>, /* ap 35 */ 1339 <0x00061000 0x00061000 0x001000>, /* ap 36 */ 1340 <0x00096000 0x00096000 0x001000>, /* ap 37 */ 1341 <0x00097000 0x00097000 0x001000>, /* ap 38 */ 1342 <0x00076000 0x00076000 0x001000>, /* ap 39 */ 1343 <0x00077000 0x00077000 0x001000>, /* ap 40 */ 1344 <0x00078000 0x00078000 0x001000>, /* ap 41 */ 1345 <0x00079000 0x00079000 0x001000>, /* ap 42 */ 1346 <0x00086000 0x00086000 0x001000>, /* ap 43 */ 1347 <0x00087000 0x00087000 0x001000>, /* ap 44 */ 1348 <0x00088000 0x00088000 0x001000>, /* ap 45 */ 1349 <0x00089000 0x00089000 0x001000>, /* ap 46 */ 1350 <0x000b0000 0x000b0000 0x001000>, /* ap 47 */ 1351 <0x000b1000 0x000b1000 0x001000>, /* ap 48 */ 1352 <0x00098000 0x00098000 0x001000>, /* ap 49 */ 1353 <0x00099000 0x00099000 0x001000>, /* ap 50 */ 1354 <0x0009a000 0x0009a000 0x001000>, /* ap 51 */ 1355 <0x0009b000 0x0009b000 0x001000>, /* ap 52 */ 1356 <0x0009c000 0x0009c000 0x001000>, /* ap 53 */ 1357 <0x0009d000 0x0009d000 0x001000>, /* ap 54 */ 1358 <0x0009e000 0x0009e000 0x001000>, /* ap 55 */ 1359 <0x0009f000 0x0009f000 0x001000>, /* ap 56 */ 1360 <0x00090000 0x00090000 0x002000>, /* ap 57 */ 1361 <0x00092000 0x00092000 0x001000>, /* ap 58 */ 1362 <0x000a4000 0x000a4000 0x001000>, /* ap 59 */ 1363 <0x000a6000 0x000a6000 0x001000>, /* ap 60 */ 1364 <0x000a8000 0x000a8000 0x004000>, /* ap 61 */ 1365 <0x000ac000 0x000ac000 0x001000>, /* ap 62 */ 1366 <0x000ad000 0x000ad000 0x001000>, /* ap 63 */ 1367 <0x000ae000 0x000ae000 0x001000>, /* ap 64 */ 1368 <0x000b2000 0x000b2000 0x001000>, /* ap 65 */ 1369 <0x000b3000 0x000b3000 0x001000>, /* ap 66 */ 1370 <0x000b4000 0x000b4000 0x001000>, /* ap 67 */ 1371 <0x000b5000 0x000b5000 0x001000>, /* ap 68 */ 1372 <0x000b8000 0x000b8000 0x001000>, /* ap 69 */ 1373 <0x000b9000 0x000b9000 0x001000>, /* ap 70 */ 1374 <0x000ba000 0x000ba000 0x001000>, /* ap 71 */ 1375 <0x000bb000 0x000bb000 0x001000>, /* ap 72 */ 1376 <0x000d1000 0x000d1000 0x001000>, /* ap 73 */ 1377 <0x000d2000 0x000d2000 0x001000>, /* ap 74 */ 1378 <0x000d5000 0x000d5000 0x001000>, /* ap 75 */ 1379 <0x000d6000 0x000d6000 0x001000>, /* ap 76 */ 1380 <0x000a2000 0x000a2000 0x001000>, /* ap 79 */ 1381 <0x000a3000 0x000a3000 0x001000>, /* ap 80 */ 1382 <0x00001400 0x00001400 0x000400>, /* ap 81 */ 1383 <0x00001800 0x00001800 0x000400>, /* ap 82 */ 1384 <0x00001c00 0x00001c00 0x000400>, /* ap 83 */ 1385 <0x000a5000 0x000a5000 0x001000>; /* ap 84 */ 1386 1387 target-module@20000 { /* 0x48020000, ap 3 06.0 */ 1388 compatible = "ti,sysc-omap2", "ti,sysc"; 1389 reg = <0x20050 0x4>, 1390 <0x20054 0x4>, 1391 <0x20058 0x4>; 1392 reg-names = "rev", "sysc", "syss"; 1393 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1394 SYSC_OMAP2_SOFTRESET | 1395 SYSC_OMAP2_AUTOIDLE)>; 1396 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1397 <SYSC_IDLE_NO>, 1398 <SYSC_IDLE_SMART>, 1399 <SYSC_IDLE_SMART_WKUP>; 1400 ti,syss-mask = <1>; 1401 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1402 clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>; 1403 clock-names = "fck"; 1404 #address-cells = <1>; 1405 #size-cells = <1>; 1406 ranges = <0x0 0x20000 0x1000>; 1407 1408 uart3: serial@0 { 1409 compatible = "ti,omap4-uart"; 1410 reg = <0x0 0x100>; 1411 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1412 clock-frequency = <48000000>; 1413 }; 1414 }; 1415 1416 target-module@32000 { /* 0x48032000, ap 5 02.0 */ 1417 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 1418 reg = <0x32000 0x4>, 1419 <0x32010 0x4>, 1420 <0x32014 0x4>; 1421 reg-names = "rev", "sysc", "syss"; 1422 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1423 SYSC_OMAP2_EMUFREE | 1424 SYSC_OMAP2_ENAWAKEUP | 1425 SYSC_OMAP2_SOFTRESET | 1426 SYSC_OMAP2_AUTOIDLE)>; 1427 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1428 <SYSC_IDLE_NO>, 1429 <SYSC_IDLE_SMART>; 1430 ti,syss-mask = <1>; 1431 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1432 clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>; 1433 clock-names = "fck"; 1434 #address-cells = <1>; 1435 #size-cells = <1>; 1436 ranges = <0x0 0x32000 0x1000>; 1437 1438 timer2: timer@0 { 1439 compatible = "ti,omap3430-timer"; 1440 reg = <0x0 0x80>; 1441 clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>, 1442 <&sys_clkin_ck>; 1443 clock-names = "fck", "timer_sys_ck"; 1444 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1445 }; 1446 }; 1447 1448 target-module@34000 { /* 0x48034000, ap 7 04.0 */ 1449 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1450 reg = <0x34000 0x4>, 1451 <0x34010 0x4>; 1452 reg-names = "rev", "sysc"; 1453 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1454 SYSC_OMAP4_SOFTRESET)>; 1455 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1456 <SYSC_IDLE_NO>, 1457 <SYSC_IDLE_SMART>, 1458 <SYSC_IDLE_SMART_WKUP>; 1459 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1460 clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>; 1461 clock-names = "fck"; 1462 #address-cells = <1>; 1463 #size-cells = <1>; 1464 ranges = <0x0 0x34000 0x1000>; 1465 1466 timer3: timer@0 { 1467 compatible = "ti,omap4430-timer"; 1468 reg = <0x0 0x80>; 1469 clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>, 1470 <&sys_clkin_ck>; 1471 clock-names = "fck", "timer_sys_ck"; 1472 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1473 }; 1474 }; 1475 1476 target-module@36000 { /* 0x48036000, ap 9 0e.0 */ 1477 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1478 reg = <0x36000 0x4>, 1479 <0x36010 0x4>; 1480 reg-names = "rev", "sysc"; 1481 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1482 SYSC_OMAP4_SOFTRESET)>; 1483 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1484 <SYSC_IDLE_NO>, 1485 <SYSC_IDLE_SMART>, 1486 <SYSC_IDLE_SMART_WKUP>; 1487 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1488 clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>; 1489 clock-names = "fck"; 1490 #address-cells = <1>; 1491 #size-cells = <1>; 1492 ranges = <0x0 0x36000 0x1000>; 1493 1494 timer4: timer@0 { 1495 compatible = "ti,omap4430-timer"; 1496 reg = <0x0 0x80>; 1497 clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>, 1498 <&sys_clkin_ck>; 1499 clock-names = "fck", "timer_sys_ck"; 1500 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1501 }; 1502 }; 1503 1504 target-module@3e000 { /* 0x4803e000, ap 11 08.0 */ 1505 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1506 reg = <0x3e000 0x4>, 1507 <0x3e010 0x4>; 1508 reg-names = "rev", "sysc"; 1509 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1510 SYSC_OMAP4_SOFTRESET)>; 1511 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1512 <SYSC_IDLE_NO>, 1513 <SYSC_IDLE_SMART>, 1514 <SYSC_IDLE_SMART_WKUP>; 1515 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1516 clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>; 1517 clock-names = "fck"; 1518 #address-cells = <1>; 1519 #size-cells = <1>; 1520 ranges = <0x0 0x3e000 0x1000>; 1521 1522 timer9: timer@0 { 1523 compatible = "ti,omap4430-timer"; 1524 reg = <0x0 0x80>; 1525 clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>, 1526 <&sys_clkin_ck>; 1527 clock-names = "fck", "timer_sys_ck"; 1528 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1529 ti,timer-pwm; 1530 }; 1531 }; 1532 1533 /* Unused DSS L4 access, see L3 instead */ 1534 target-module@40000 { /* 0x48040000, ap 13 0a.0 */ 1535 compatible = "ti,sysc"; 1536 status = "disabled"; 1537 #address-cells = <1>; 1538 #size-cells = <1>; 1539 ranges = <0x0 0x40000 0x10000>; 1540 }; 1541 1542 target-module@55000 { /* 0x48055000, ap 15 0c.0 */ 1543 compatible = "ti,sysc-omap2", "ti,sysc"; 1544 reg = <0x55000 0x4>, 1545 <0x55010 0x4>, 1546 <0x55114 0x4>; 1547 reg-names = "rev", "sysc", "syss"; 1548 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1549 SYSC_OMAP2_SOFTRESET | 1550 SYSC_OMAP2_AUTOIDLE)>; 1551 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1552 <SYSC_IDLE_NO>, 1553 <SYSC_IDLE_SMART>, 1554 <SYSC_IDLE_SMART_WKUP>; 1555 ti,syss-mask = <1>; 1556 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1557 clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>, 1558 <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; 1559 clock-names = "fck", "dbclk"; 1560 #address-cells = <1>; 1561 #size-cells = <1>; 1562 ranges = <0x0 0x55000 0x1000>; 1563 1564 gpio2: gpio@0 { 1565 compatible = "ti,omap4-gpio"; 1566 reg = <0x0 0x200>; 1567 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1568 gpio-controller; 1569 #gpio-cells = <2>; 1570 interrupt-controller; 1571 #interrupt-cells = <2>; 1572 }; 1573 }; 1574 1575 target-module@57000 { /* 0x48057000, ap 17 16.0 */ 1576 compatible = "ti,sysc-omap2", "ti,sysc"; 1577 reg = <0x57000 0x4>, 1578 <0x57010 0x4>, 1579 <0x57114 0x4>; 1580 reg-names = "rev", "sysc", "syss"; 1581 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1582 SYSC_OMAP2_SOFTRESET | 1583 SYSC_OMAP2_AUTOIDLE)>; 1584 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1585 <SYSC_IDLE_NO>, 1586 <SYSC_IDLE_SMART>, 1587 <SYSC_IDLE_SMART_WKUP>; 1588 ti,syss-mask = <1>; 1589 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1590 clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>, 1591 <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 8>; 1592 clock-names = "fck", "dbclk"; 1593 #address-cells = <1>; 1594 #size-cells = <1>; 1595 ranges = <0x0 0x57000 0x1000>; 1596 1597 gpio3: gpio@0 { 1598 compatible = "ti,omap4-gpio"; 1599 reg = <0x0 0x200>; 1600 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1601 gpio-controller; 1602 #gpio-cells = <2>; 1603 interrupt-controller; 1604 #interrupt-cells = <2>; 1605 }; 1606 }; 1607 1608 target-module@59000 { /* 0x48059000, ap 19 10.0 */ 1609 compatible = "ti,sysc-omap2", "ti,sysc"; 1610 reg = <0x59000 0x4>, 1611 <0x59010 0x4>, 1612 <0x59114 0x4>; 1613 reg-names = "rev", "sysc", "syss"; 1614 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1615 SYSC_OMAP2_SOFTRESET | 1616 SYSC_OMAP2_AUTOIDLE)>; 1617 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1618 <SYSC_IDLE_NO>, 1619 <SYSC_IDLE_SMART>, 1620 <SYSC_IDLE_SMART_WKUP>; 1621 ti,syss-mask = <1>; 1622 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1623 clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>, 1624 <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 8>; 1625 clock-names = "fck", "dbclk"; 1626 #address-cells = <1>; 1627 #size-cells = <1>; 1628 ranges = <0x0 0x59000 0x1000>; 1629 1630 gpio4: gpio@0 { 1631 compatible = "ti,omap4-gpio"; 1632 reg = <0x0 0x200>; 1633 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1634 gpio-controller; 1635 #gpio-cells = <2>; 1636 interrupt-controller; 1637 #interrupt-cells = <2>; 1638 }; 1639 }; 1640 1641 target-module@5b000 { /* 0x4805b000, ap 21 12.0 */ 1642 compatible = "ti,sysc-omap2", "ti,sysc"; 1643 reg = <0x5b000 0x4>, 1644 <0x5b010 0x4>, 1645 <0x5b114 0x4>; 1646 reg-names = "rev", "sysc", "syss"; 1647 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1648 SYSC_OMAP2_SOFTRESET | 1649 SYSC_OMAP2_AUTOIDLE)>; 1650 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1651 <SYSC_IDLE_NO>, 1652 <SYSC_IDLE_SMART>, 1653 <SYSC_IDLE_SMART_WKUP>; 1654 ti,syss-mask = <1>; 1655 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1656 clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>, 1657 <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 8>; 1658 clock-names = "fck", "dbclk"; 1659 #address-cells = <1>; 1660 #size-cells = <1>; 1661 ranges = <0x0 0x5b000 0x1000>; 1662 1663 gpio5: gpio@0 { 1664 compatible = "ti,omap4-gpio"; 1665 reg = <0x0 0x200>; 1666 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1667 gpio-controller; 1668 #gpio-cells = <2>; 1669 interrupt-controller; 1670 #interrupt-cells = <2>; 1671 }; 1672 }; 1673 1674 target-module@5d000 { /* 0x4805d000, ap 23 14.0 */ 1675 compatible = "ti,sysc-omap2", "ti,sysc"; 1676 reg = <0x5d000 0x4>, 1677 <0x5d010 0x4>, 1678 <0x5d114 0x4>; 1679 reg-names = "rev", "sysc", "syss"; 1680 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1681 SYSC_OMAP2_SOFTRESET | 1682 SYSC_OMAP2_AUTOIDLE)>; 1683 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1684 <SYSC_IDLE_NO>, 1685 <SYSC_IDLE_SMART>, 1686 <SYSC_IDLE_SMART_WKUP>; 1687 ti,syss-mask = <1>; 1688 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1689 clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>, 1690 <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 8>; 1691 clock-names = "fck", "dbclk"; 1692 #address-cells = <1>; 1693 #size-cells = <1>; 1694 ranges = <0x0 0x5d000 0x1000>; 1695 1696 gpio6: gpio@0 { 1697 compatible = "ti,omap4-gpio"; 1698 reg = <0x0 0x200>; 1699 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1700 gpio-controller; 1701 #gpio-cells = <2>; 1702 interrupt-controller; 1703 #interrupt-cells = <2>; 1704 }; 1705 }; 1706 1707 target-module@60000 { /* 0x48060000, ap 25 1e.0 */ 1708 compatible = "ti,sysc-omap2", "ti,sysc"; 1709 reg = <0x60000 0x8>, 1710 <0x60010 0x8>, 1711 <0x60090 0x8>; 1712 reg-names = "rev", "sysc", "syss"; 1713 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1714 SYSC_OMAP2_ENAWAKEUP | 1715 SYSC_OMAP2_SOFTRESET | 1716 SYSC_OMAP2_AUTOIDLE)>; 1717 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1718 <SYSC_IDLE_NO>, 1719 <SYSC_IDLE_SMART>, 1720 <SYSC_IDLE_SMART_WKUP>; 1721 ti,syss-mask = <1>; 1722 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1723 clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>; 1724 clock-names = "fck"; 1725 #address-cells = <1>; 1726 #size-cells = <1>; 1727 ranges = <0x0 0x60000 0x1000>; 1728 1729 i2c3: i2c@0 { 1730 compatible = "ti,omap4-i2c"; 1731 reg = <0x0 0x100>; 1732 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 }; 1736 }; 1737 1738 target-module@6a000 { /* 0x4806a000, ap 26 18.0 */ 1739 compatible = "ti,sysc-omap2", "ti,sysc"; 1740 reg = <0x6a050 0x4>, 1741 <0x6a054 0x4>, 1742 <0x6a058 0x4>; 1743 reg-names = "rev", "sysc", "syss"; 1744 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1745 SYSC_OMAP2_SOFTRESET | 1746 SYSC_OMAP2_AUTOIDLE)>; 1747 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1748 <SYSC_IDLE_NO>, 1749 <SYSC_IDLE_SMART>, 1750 <SYSC_IDLE_SMART_WKUP>; 1751 ti,syss-mask = <1>; 1752 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1753 clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>; 1754 clock-names = "fck"; 1755 #address-cells = <1>; 1756 #size-cells = <1>; 1757 ranges = <0x0 0x6a000 0x1000>; 1758 1759 uart1: serial@0 { 1760 compatible = "ti,omap4-uart"; 1761 reg = <0x0 0x100>; 1762 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1763 clock-frequency = <48000000>; 1764 }; 1765 }; 1766 1767 target-module@6c000 { /* 0x4806c000, ap 28 20.0 */ 1768 compatible = "ti,sysc-omap2", "ti,sysc"; 1769 reg = <0x6c050 0x4>, 1770 <0x6c054 0x4>, 1771 <0x6c058 0x4>; 1772 reg-names = "rev", "sysc", "syss"; 1773 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1774 SYSC_OMAP2_SOFTRESET | 1775 SYSC_OMAP2_AUTOIDLE)>; 1776 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1777 <SYSC_IDLE_NO>, 1778 <SYSC_IDLE_SMART>, 1779 <SYSC_IDLE_SMART_WKUP>; 1780 ti,syss-mask = <1>; 1781 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1782 clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>; 1783 clock-names = "fck"; 1784 #address-cells = <1>; 1785 #size-cells = <1>; 1786 ranges = <0x0 0x6c000 0x1000>; 1787 1788 uart2: serial@0 { 1789 compatible = "ti,omap4-uart"; 1790 reg = <0x0 0x100>; 1791 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1792 clock-frequency = <48000000>; 1793 }; 1794 }; 1795 1796 target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */ 1797 compatible = "ti,sysc-omap2", "ti,sysc"; 1798 reg = <0x6e050 0x4>, 1799 <0x6e054 0x4>, 1800 <0x6e058 0x4>; 1801 reg-names = "rev", "sysc", "syss"; 1802 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1803 SYSC_OMAP2_SOFTRESET | 1804 SYSC_OMAP2_AUTOIDLE)>; 1805 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1806 <SYSC_IDLE_NO>, 1807 <SYSC_IDLE_SMART>, 1808 <SYSC_IDLE_SMART_WKUP>; 1809 ti,syss-mask = <1>; 1810 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1811 clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>; 1812 clock-names = "fck"; 1813 #address-cells = <1>; 1814 #size-cells = <1>; 1815 ranges = <0x0 0x6e000 0x1000>; 1816 1817 uart4: serial@0 { 1818 compatible = "ti,omap4-uart"; 1819 reg = <0x0 0x100>; 1820 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1821 clock-frequency = <48000000>; 1822 }; 1823 }; 1824 1825 target-module@70000 { /* 0x48070000, ap 32 28.0 */ 1826 compatible = "ti,sysc-omap2", "ti,sysc"; 1827 reg = <0x70000 0x8>, 1828 <0x70010 0x8>, 1829 <0x70090 0x8>; 1830 reg-names = "rev", "sysc", "syss"; 1831 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1832 SYSC_OMAP2_ENAWAKEUP | 1833 SYSC_OMAP2_SOFTRESET | 1834 SYSC_OMAP2_AUTOIDLE)>; 1835 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1836 <SYSC_IDLE_NO>, 1837 <SYSC_IDLE_SMART>, 1838 <SYSC_IDLE_SMART_WKUP>; 1839 ti,syss-mask = <1>; 1840 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1841 clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>; 1842 clock-names = "fck"; 1843 #address-cells = <1>; 1844 #size-cells = <1>; 1845 ranges = <0x0 0x70000 0x1000>; 1846 1847 i2c1: i2c@0 { 1848 compatible = "ti,omap4-i2c"; 1849 reg = <0x0 0x100>; 1850 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1851 #address-cells = <1>; 1852 #size-cells = <0>; 1853 }; 1854 }; 1855 1856 target-module@72000 { /* 0x48072000, ap 34 30.0 */ 1857 compatible = "ti,sysc-omap2", "ti,sysc"; 1858 reg = <0x72000 0x8>, 1859 <0x72010 0x8>, 1860 <0x72090 0x8>; 1861 reg-names = "rev", "sysc", "syss"; 1862 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1863 SYSC_OMAP2_ENAWAKEUP | 1864 SYSC_OMAP2_SOFTRESET | 1865 SYSC_OMAP2_AUTOIDLE)>; 1866 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1867 <SYSC_IDLE_NO>, 1868 <SYSC_IDLE_SMART>, 1869 <SYSC_IDLE_SMART_WKUP>; 1870 ti,syss-mask = <1>; 1871 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1872 clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>; 1873 clock-names = "fck"; 1874 #address-cells = <1>; 1875 #size-cells = <1>; 1876 ranges = <0x0 0x72000 0x1000>; 1877 1878 i2c2: i2c@0 { 1879 compatible = "ti,omap4-i2c"; 1880 reg = <0x0 0x100>; 1881 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1882 #address-cells = <1>; 1883 #size-cells = <0>; 1884 }; 1885 }; 1886 1887 target-module@76000 { /* 0x48076000, ap 39 38.0 */ 1888 compatible = "ti,sysc-omap4", "ti,sysc"; 1889 reg = <0x76000 0x4>, 1890 <0x76010 0x4>; 1891 reg-names = "rev", "sysc"; 1892 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1893 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1894 <SYSC_IDLE_NO>, 1895 <SYSC_IDLE_SMART>, 1896 <SYSC_IDLE_SMART_WKUP>; 1897 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1898 clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>; 1899 clock-names = "fck"; 1900 #address-cells = <1>; 1901 #size-cells = <1>; 1902 ranges = <0x0 0x76000 0x1000>; 1903 1904 /* No child device binding or driver in mainline */ 1905 }; 1906 1907 target-module@78000 { /* 0x48078000, ap 41 1a.0 */ 1908 compatible = "ti,sysc-omap2", "ti,sysc"; 1909 reg = <0x78000 0x4>, 1910 <0x78010 0x4>, 1911 <0x78014 0x4>; 1912 reg-names = "rev", "sysc", "syss"; 1913 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1914 SYSC_OMAP2_SOFTRESET | 1915 SYSC_OMAP2_AUTOIDLE)>; 1916 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1917 <SYSC_IDLE_NO>, 1918 <SYSC_IDLE_SMART>; 1919 ti,syss-mask = <1>; 1920 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1921 clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>; 1922 clock-names = "fck"; 1923 #address-cells = <1>; 1924 #size-cells = <1>; 1925 ranges = <0x0 0x78000 0x1000>; 1926 1927 elm: elm@0 { 1928 compatible = "ti,am3352-elm"; 1929 reg = <0x0 0x2000>; 1930 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1931 status = "disabled"; 1932 }; 1933 }; 1934 1935 target-module@86000 { /* 0x48086000, ap 43 24.0 */ 1936 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 1937 reg = <0x86000 0x4>, 1938 <0x86010 0x4>, 1939 <0x86014 0x4>; 1940 reg-names = "rev", "sysc", "syss"; 1941 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1942 SYSC_OMAP2_EMUFREE | 1943 SYSC_OMAP2_ENAWAKEUP | 1944 SYSC_OMAP2_SOFTRESET | 1945 SYSC_OMAP2_AUTOIDLE)>; 1946 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1947 <SYSC_IDLE_NO>, 1948 <SYSC_IDLE_SMART>; 1949 ti,syss-mask = <1>; 1950 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1951 clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>; 1952 clock-names = "fck"; 1953 #address-cells = <1>; 1954 #size-cells = <1>; 1955 ranges = <0x0 0x86000 0x1000>; 1956 1957 timer10: timer@0 { 1958 compatible = "ti,omap3430-timer"; 1959 reg = <0x0 0x80>; 1960 clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>, 1961 <&sys_clkin_ck>; 1962 clock-names = "fck", "timer_sys_ck"; 1963 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1964 ti,timer-pwm; 1965 }; 1966 }; 1967 1968 target-module@88000 { /* 0x48088000, ap 45 2e.0 */ 1969 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1970 reg = <0x88000 0x4>, 1971 <0x88010 0x4>; 1972 reg-names = "rev", "sysc"; 1973 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1974 SYSC_OMAP4_SOFTRESET)>; 1975 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1976 <SYSC_IDLE_NO>, 1977 <SYSC_IDLE_SMART>, 1978 <SYSC_IDLE_SMART_WKUP>; 1979 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1980 clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>; 1981 clock-names = "fck"; 1982 #address-cells = <1>; 1983 #size-cells = <1>; 1984 ranges = <0x0 0x88000 0x1000>; 1985 1986 timer11: timer@0 { 1987 compatible = "ti,omap4430-timer"; 1988 reg = <0x0 0x80>; 1989 clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>, 1990 <&sys_clkin_ck>; 1991 clock-names = "fck", "timer_sys_ck"; 1992 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1993 ti,timer-pwm; 1994 }; 1995 }; 1996 1997 rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */ 1998 compatible = "ti,sysc-omap2", "ti,sysc"; 1999 reg = <0x91fe0 0x4>, 2000 <0x91fe4 0x4>; 2001 reg-names = "rev", "sysc"; 2002 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; 2003 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2004 <SYSC_IDLE_NO>; 2005 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ 2006 clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>; 2007 clock-names = "fck"; 2008 #address-cells = <1>; 2009 #size-cells = <1>; 2010 ranges = <0x0 0x90000 0x2000>; 2011 2012 rng: rng@0 { 2013 compatible = "ti,omap4-rng"; 2014 reg = <0x0 0x2000>; 2015 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 2016 }; 2017 }; 2018 2019 target-module@96000 { /* 0x48096000, ap 37 26.0 */ 2020 compatible = "ti,sysc-omap2", "ti,sysc"; 2021 reg = <0x9608c 0x4>; 2022 reg-names = "sysc"; 2023 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 2024 SYSC_OMAP2_ENAWAKEUP | 2025 SYSC_OMAP2_SOFTRESET)>; 2026 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2027 <SYSC_IDLE_NO>, 2028 <SYSC_IDLE_SMART>; 2029 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2030 clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>; 2031 clock-names = "fck"; 2032 #address-cells = <1>; 2033 #size-cells = <1>; 2034 ranges = <0x0 0x96000 0x1000>; 2035 2036 mcbsp4: mcbsp@0 { 2037 compatible = "ti,omap4-mcbsp"; 2038 reg = <0x0 0xff>; /* L4 Interconnect */ 2039 reg-names = "mpu"; 2040 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2041 interrupt-names = "common"; 2042 ti,buffer-size = <128>; 2043 dmas = <&sdma 31>, 2044 <&sdma 32>; 2045 dma-names = "tx", "rx"; 2046 status = "disabled"; 2047 }; 2048 }; 2049 2050 target-module@98000 { /* 0x48098000, ap 49 22.0 */ 2051 compatible = "ti,sysc-omap4", "ti,sysc"; 2052 reg = <0x98000 0x4>, 2053 <0x98010 0x4>; 2054 reg-names = "rev", "sysc"; 2055 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2056 SYSC_OMAP4_SOFTRESET)>; 2057 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2058 <SYSC_IDLE_NO>, 2059 <SYSC_IDLE_SMART>, 2060 <SYSC_IDLE_SMART_WKUP>; 2061 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2062 clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>; 2063 clock-names = "fck"; 2064 #address-cells = <1>; 2065 #size-cells = <1>; 2066 ranges = <0x0 0x98000 0x1000>; 2067 2068 mcspi1: spi@0 { 2069 compatible = "ti,omap4-mcspi"; 2070 reg = <0x0 0x200>; 2071 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 2072 #address-cells = <1>; 2073 #size-cells = <0>; 2074 ti,spi-num-cs = <4>; 2075 dmas = <&sdma 35>, 2076 <&sdma 36>, 2077 <&sdma 37>, 2078 <&sdma 38>, 2079 <&sdma 39>, 2080 <&sdma 40>, 2081 <&sdma 41>, 2082 <&sdma 42>; 2083 dma-names = "tx0", "rx0", "tx1", "rx1", 2084 "tx2", "rx2", "tx3", "rx3"; 2085 }; 2086 }; 2087 2088 target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */ 2089 compatible = "ti,sysc-omap4", "ti,sysc"; 2090 reg = <0x9a000 0x4>, 2091 <0x9a010 0x4>; 2092 reg-names = "rev", "sysc"; 2093 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2094 SYSC_OMAP4_SOFTRESET)>; 2095 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2096 <SYSC_IDLE_NO>, 2097 <SYSC_IDLE_SMART>, 2098 <SYSC_IDLE_SMART_WKUP>; 2099 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2100 clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>; 2101 clock-names = "fck"; 2102 #address-cells = <1>; 2103 #size-cells = <1>; 2104 ranges = <0x0 0x9a000 0x1000>; 2105 2106 mcspi2: spi@0 { 2107 compatible = "ti,omap4-mcspi"; 2108 reg = <0x0 0x200>; 2109 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 2110 #address-cells = <1>; 2111 #size-cells = <0>; 2112 ti,spi-num-cs = <2>; 2113 dmas = <&sdma 43>, 2114 <&sdma 44>, 2115 <&sdma 45>, 2116 <&sdma 46>; 2117 dma-names = "tx0", "rx0", "tx1", "rx1"; 2118 }; 2119 }; 2120 2121 target-module@9c000 { /* 0x4809c000, ap 53 36.0 */ 2122 compatible = "ti,sysc-omap4", "ti,sysc"; 2123 reg = <0x9c000 0x4>, 2124 <0x9c010 0x4>; 2125 reg-names = "rev", "sysc"; 2126 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2127 SYSC_OMAP4_SOFTRESET)>; 2128 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2129 <SYSC_IDLE_NO>, 2130 <SYSC_IDLE_SMART>, 2131 <SYSC_IDLE_SMART_WKUP>; 2132 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2133 <SYSC_IDLE_NO>, 2134 <SYSC_IDLE_SMART>, 2135 <SYSC_IDLE_SMART_WKUP>; 2136 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 2137 clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>; 2138 clock-names = "fck"; 2139 #address-cells = <1>; 2140 #size-cells = <1>; 2141 ranges = <0x0 0x9c000 0x1000>; 2142 2143 mmc1: mmc@0 { 2144 compatible = "ti,omap4-hsmmc"; 2145 reg = <0x0 0x400>; 2146 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2147 ti,dual-volt; 2148 ti,needs-special-reset; 2149 dmas = <&sdma 61>, <&sdma 62>; 2150 dma-names = "tx", "rx"; 2151 pbias-supply = <&pbias_mmc_reg>; 2152 }; 2153 }; 2154 2155 target-module@9e000 { /* 0x4809e000, ap 55 48.0 */ 2156 compatible = "ti,sysc"; 2157 status = "disabled"; 2158 #address-cells = <1>; 2159 #size-cells = <1>; 2160 ranges = <0x0 0x9e000 0x1000>; 2161 }; 2162 2163 target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */ 2164 compatible = "ti,sysc"; 2165 status = "disabled"; 2166 #address-cells = <1>; 2167 #size-cells = <1>; 2168 ranges = <0x0 0xa2000 0x1000>; 2169 }; 2170 2171 target-module@a4000 { /* 0x480a4000, ap 59 34.0 */ 2172 compatible = "ti,sysc"; 2173 status = "disabled"; 2174 #address-cells = <1>; 2175 #size-cells = <1>; 2176 ranges = <0x00000000 0x000a4000 0x00001000>, 2177 <0x00001000 0x000a5000 0x00001000>; 2178 }; 2179 2180 des_target: target-module@a5000 { /* 0x480a5000 */ 2181 compatible = "ti,sysc-omap2", "ti,sysc"; 2182 reg = <0xa5030 0x4>, 2183 <0xa5034 0x4>, 2184 <0xa5038 0x4>; 2185 reg-names = "rev", "sysc", "syss"; 2186 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 2187 SYSC_OMAP2_AUTOIDLE)>; 2188 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2189 <SYSC_IDLE_NO>, 2190 <SYSC_IDLE_SMART>, 2191 <SYSC_IDLE_SMART_WKUP>; 2192 ti,syss-mask = <1>; 2193 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ 2194 clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>; 2195 clock-names = "fck"; 2196 #address-cells = <1>; 2197 #size-cells = <1>; 2198 ranges = <0 0xa5000 0x00001000>; 2199 2200 des: des@0 { 2201 compatible = "ti,omap4-des"; 2202 reg = <0 0xa0>; 2203 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2204 dmas = <&sdma 117>, <&sdma 116>; 2205 dma-names = "tx", "rx"; 2206 }; 2207 }; 2208 2209 target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */ 2210 compatible = "ti,sysc"; 2211 status = "disabled"; 2212 #address-cells = <1>; 2213 #size-cells = <1>; 2214 ranges = <0x0 0xa8000 0x4000>; 2215 }; 2216 2217 target-module@ad000 { /* 0x480ad000, ap 63 50.0 */ 2218 compatible = "ti,sysc-omap4", "ti,sysc"; 2219 reg = <0xad000 0x4>, 2220 <0xad010 0x4>; 2221 reg-names = "rev", "sysc"; 2222 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2223 SYSC_OMAP4_SOFTRESET)>; 2224 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2225 <SYSC_IDLE_NO>, 2226 <SYSC_IDLE_SMART>, 2227 <SYSC_IDLE_SMART_WKUP>; 2228 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2229 <SYSC_IDLE_NO>, 2230 <SYSC_IDLE_SMART>, 2231 <SYSC_IDLE_SMART_WKUP>; 2232 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2233 clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>; 2234 clock-names = "fck"; 2235 #address-cells = <1>; 2236 #size-cells = <1>; 2237 ranges = <0x0 0xad000 0x1000>; 2238 2239 mmc3: mmc@0 { 2240 compatible = "ti,omap4-hsmmc"; 2241 reg = <0x0 0x400>; 2242 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 2243 ti,needs-special-reset; 2244 dmas = <&sdma 77>, <&sdma 78>; 2245 dma-names = "tx", "rx"; 2246 }; 2247 }; 2248 2249 target-module@b0000 { /* 0x480b0000, ap 47 40.0 */ 2250 compatible = "ti,sysc"; 2251 status = "disabled"; 2252 #address-cells = <1>; 2253 #size-cells = <1>; 2254 ranges = <0x0 0xb0000 0x1000>; 2255 }; 2256 2257 target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */ 2258 compatible = "ti,sysc-omap2", "ti,sysc"; 2259 reg = <0xb2000 0x4>, 2260 <0xb2014 0x4>, 2261 <0xb2018 0x4>; 2262 reg-names = "rev", "sysc", "syss"; 2263 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 2264 SYSC_OMAP2_AUTOIDLE)>; 2265 ti,syss-mask = <1>; 2266 ti,no-reset-on-init; 2267 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2268 clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>; 2269 clock-names = "fck"; 2270 #address-cells = <1>; 2271 #size-cells = <1>; 2272 ranges = <0x0 0xb2000 0x1000>; 2273 2274 hdqw1w: 1w@0 { 2275 compatible = "ti,omap3-1w"; 2276 reg = <0x0 0x1000>; 2277 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 2278 }; 2279 }; 2280 2281 target-module@b4000 { /* 0x480b4000, ap 67 46.0 */ 2282 compatible = "ti,sysc-omap4", "ti,sysc"; 2283 reg = <0xb4000 0x4>, 2284 <0xb4010 0x4>; 2285 reg-names = "rev", "sysc"; 2286 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2287 SYSC_OMAP4_SOFTRESET)>; 2288 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2289 <SYSC_IDLE_NO>, 2290 <SYSC_IDLE_SMART>, 2291 <SYSC_IDLE_SMART_WKUP>; 2292 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2293 <SYSC_IDLE_NO>, 2294 <SYSC_IDLE_SMART>, 2295 <SYSC_IDLE_SMART_WKUP>; 2296 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 2297 clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>; 2298 clock-names = "fck"; 2299 #address-cells = <1>; 2300 #size-cells = <1>; 2301 ranges = <0x0 0xb4000 0x1000>; 2302 2303 mmc2: mmc@0 { 2304 compatible = "ti,omap4-hsmmc"; 2305 reg = <0x0 0x400>; 2306 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2307 ti,needs-special-reset; 2308 dmas = <&sdma 47>, <&sdma 48>; 2309 dma-names = "tx", "rx"; 2310 }; 2311 }; 2312 2313 target-module@b8000 { /* 0x480b8000, ap 69 58.0 */ 2314 compatible = "ti,sysc-omap4", "ti,sysc"; 2315 reg = <0xb8000 0x4>, 2316 <0xb8010 0x4>; 2317 reg-names = "rev", "sysc"; 2318 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2319 SYSC_OMAP4_SOFTRESET)>; 2320 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2321 <SYSC_IDLE_NO>, 2322 <SYSC_IDLE_SMART>, 2323 <SYSC_IDLE_SMART_WKUP>; 2324 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2325 clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>; 2326 clock-names = "fck"; 2327 #address-cells = <1>; 2328 #size-cells = <1>; 2329 ranges = <0x0 0xb8000 0x1000>; 2330 2331 mcspi3: spi@0 { 2332 compatible = "ti,omap4-mcspi"; 2333 reg = <0x0 0x200>; 2334 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2335 #address-cells = <1>; 2336 #size-cells = <0>; 2337 ti,spi-num-cs = <2>; 2338 dmas = <&sdma 15>, <&sdma 16>; 2339 dma-names = "tx0", "rx0"; 2340 }; 2341 }; 2342 2343 target-module@ba000 { /* 0x480ba000, ap 71 32.0 */ 2344 compatible = "ti,sysc-omap4", "ti,sysc"; 2345 reg = <0xba000 0x4>, 2346 <0xba010 0x4>; 2347 reg-names = "rev", "sysc"; 2348 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2349 SYSC_OMAP4_SOFTRESET)>; 2350 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2351 <SYSC_IDLE_NO>, 2352 <SYSC_IDLE_SMART>, 2353 <SYSC_IDLE_SMART_WKUP>; 2354 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2355 clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>; 2356 clock-names = "fck"; 2357 #address-cells = <1>; 2358 #size-cells = <1>; 2359 ranges = <0x0 0xba000 0x1000>; 2360 2361 mcspi4: spi@0 { 2362 compatible = "ti,omap4-mcspi"; 2363 reg = <0x0 0x200>; 2364 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 2365 #address-cells = <1>; 2366 #size-cells = <0>; 2367 ti,spi-num-cs = <1>; 2368 dmas = <&sdma 70>, <&sdma 71>; 2369 dma-names = "tx0", "rx0"; 2370 }; 2371 }; 2372 2373 target-module@d1000 { /* 0x480d1000, ap 73 44.0 */ 2374 compatible = "ti,sysc-omap4", "ti,sysc"; 2375 reg = <0xd1000 0x4>, 2376 <0xd1010 0x4>; 2377 reg-names = "rev", "sysc"; 2378 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2379 SYSC_OMAP4_SOFTRESET)>; 2380 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2381 <SYSC_IDLE_NO>, 2382 <SYSC_IDLE_SMART>, 2383 <SYSC_IDLE_SMART_WKUP>; 2384 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2385 <SYSC_IDLE_NO>, 2386 <SYSC_IDLE_SMART>, 2387 <SYSC_IDLE_SMART_WKUP>; 2388 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2389 clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>; 2390 clock-names = "fck"; 2391 #address-cells = <1>; 2392 #size-cells = <1>; 2393 ranges = <0x0 0xd1000 0x1000>; 2394 2395 mmc4: mmc@0 { 2396 compatible = "ti,omap4-hsmmc"; 2397 reg = <0x0 0x400>; 2398 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2399 ti,needs-special-reset; 2400 dmas = <&sdma 57>, <&sdma 58>; 2401 dma-names = "tx", "rx"; 2402 }; 2403 }; 2404 2405 target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */ 2406 compatible = "ti,sysc-omap4", "ti,sysc"; 2407 reg = <0xd5000 0x4>, 2408 <0xd5010 0x4>; 2409 reg-names = "rev", "sysc"; 2410 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2411 SYSC_OMAP4_SOFTRESET)>; 2412 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2413 <SYSC_IDLE_NO>, 2414 <SYSC_IDLE_SMART>, 2415 <SYSC_IDLE_SMART_WKUP>; 2416 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2417 <SYSC_IDLE_NO>, 2418 <SYSC_IDLE_SMART>, 2419 <SYSC_IDLE_SMART_WKUP>; 2420 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2421 clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>; 2422 clock-names = "fck"; 2423 #address-cells = <1>; 2424 #size-cells = <1>; 2425 ranges = <0x0 0xd5000 0x1000>; 2426 2427 mmc5: mmc@0 { 2428 compatible = "ti,omap4-hsmmc"; 2429 reg = <0x0 0x400>; 2430 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 2431 ti,needs-special-reset; 2432 dmas = <&sdma 59>, <&sdma 60>; 2433 dma-names = "tx", "rx"; 2434 }; 2435 }; 2436 }; 2437 2438 segment@200000 { /* 0x48200000 */ 2439 compatible = "simple-bus"; 2440 #address-cells = <1>; 2441 #size-cells = <1>; 2442 ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */ 2443 <0x00151000 0x00351000 0x001000>; /* ap 78 */ 2444 2445 target-module@150000 { /* 0x48350000, ap 77 4c.0 */ 2446 compatible = "ti,sysc-omap2", "ti,sysc"; 2447 reg = <0x150000 0x8>, 2448 <0x150010 0x8>, 2449 <0x150090 0x8>; 2450 reg-names = "rev", "sysc", "syss"; 2451 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 2452 SYSC_OMAP2_ENAWAKEUP | 2453 SYSC_OMAP2_SOFTRESET | 2454 SYSC_OMAP2_AUTOIDLE)>; 2455 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2456 <SYSC_IDLE_NO>, 2457 <SYSC_IDLE_SMART>, 2458 <SYSC_IDLE_SMART_WKUP>; 2459 ti,syss-mask = <1>; 2460 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2461 clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>; 2462 clock-names = "fck"; 2463 #address-cells = <1>; 2464 #size-cells = <1>; 2465 ranges = <0x0 0x150000 0x1000>; 2466 2467 i2c4: i2c@0 { 2468 compatible = "ti,omap4-i2c"; 2469 reg = <0x0 0x100>; 2470 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 2471 #address-cells = <1>; 2472 #size-cells = <0>; 2473 }; 2474 }; 2475 }; 2476}; 2477 2478