Searched refs:controls (Results 1 – 25 of 42) sorted by relevance
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| /arch/x86/oprofile/ |
| D | op_model_ppro.c | 58 msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i; in ppro_fill_in_addresses()
97 if (!msrs->controls[i].addr) in ppro_setup_ctrs()
99 rdmsrl(msrs->controls[i].addr, val); in ppro_setup_ctrs()
103 wrmsrl(msrs->controls[i].addr, val); in ppro_setup_ctrs()
116 rdmsrl(msrs->controls[i].addr, val); in ppro_setup_ctrs()
119 wrmsrl(msrs->controls[i].addr, val); in ppro_setup_ctrs()
165 rdmsrl(msrs->controls[i].addr, val); in ppro_start()
167 wrmsrl(msrs->controls[i].addr, val); in ppro_start()
181 rdmsrl(msrs->controls[i].addr, val); in ppro_stop()
183 wrmsrl(msrs->controls[i].addr, val); in ppro_stop()
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| D | op_model_p4.c | 402 if (msrs->controls[i].addr) in p4_shutdown()
403 release_evntsel_nmi(msrs->controls[i].addr); in p4_shutdown()
421 msrs->controls[i].addr = cccraddr; in p4_fill_in_addresses()
429 msrs->controls[i].addr = addr; in p4_fill_in_addresses()
438 msrs->controls[i].addr = addr; in p4_fill_in_addresses()
444 msrs->controls[i].addr = addr; in p4_fill_in_addresses()
451 msrs->controls[i].addr = addr; in p4_fill_in_addresses()
457 msrs->controls[i].addr = addr; in p4_fill_in_addresses()
463 msrs->controls[i].addr = addr; in p4_fill_in_addresses()
471 msrs->controls[i++].addr = MSR_P4_CRU_ESCR5; in p4_fill_in_addresses()
[all …]
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| D | nmi_int.c | 78 struct op_msr *controls = msrs->controls; in nmi_cpu_save_registers() local
87 if (controls[i].addr) in nmi_cpu_save_registers()
88 rdmsrl(controls[i].addr, controls[i].saved); in nmi_cpu_save_registers()
95 if (!msrs->controls) in nmi_cpu_start()
115 if (!msrs->controls) in nmi_cpu_stop()
309 kfree(per_cpu(cpu_msrs, i).controls); in free_msrs()
310 per_cpu(cpu_msrs, i).controls = NULL; in free_msrs()
326 per_cpu(cpu_msrs, i).controls = kzalloc(controls_size, in allocate_msrs()
328 if (!per_cpu(cpu_msrs, i).controls) in allocate_msrs()
359 struct op_msr *controls = msrs->controls; in nmi_cpu_restore_registers() local
[all …]
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| D | op_model_amd.c | 279 rdmsrl(msrs->controls[i].addr, val); in op_mux_switch_ctrl()
282 wrmsrl(msrs->controls[i].addr, val); in op_mux_switch_ctrl()
316 msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1); in op_amd_fill_in_addresses()
318 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i; in op_amd_fill_in_addresses()
350 if (!msrs->controls[i].addr) in op_amd_setup_ctrs()
352 rdmsrl(msrs->controls[i].addr, val); in op_amd_setup_ctrs()
356 wrmsrl(msrs->controls[i].addr, val); in op_amd_setup_ctrs()
374 rdmsrl(msrs->controls[i].addr, val); in op_amd_setup_ctrs()
377 wrmsrl(msrs->controls[i].addr, val); in op_amd_setup_ctrs()
413 rdmsrl(msrs->controls[i].addr, val); in op_amd_start()
[all …]
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| D | op_x86_model.h | 25 struct op_msr *controls; member
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| /arch/arm/boot/dts/ |
| D | at91-natte.dtsi | 24 mux-controls = <&mux>;
35 mux-controls = <&mux>;
46 mux-controls = <&mux>;
57 mux-controls = <&mux>;
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| D | ste-db9500.dtsi | 8 /* cpufreq controls */
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| D | ste-db8520.dtsi | 8 /* cpufreq controls */
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| D | ste-db8500.dtsi | 8 /* cpufreq controls */
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| D | imx6dl.dtsi | 185 mux-controls = <&mux 0>;
239 mux-controls = <&mux 1>;
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| D | imx6q.dtsi | 350 mux-controls = <&mux 0>;
380 mux-controls = <&mux 1>;
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| D | stm32mp15xx-dhcom-drc02.dtsi | 33 * during TX anyway and that it only controls drive enable DE
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| D | sun8i-a23.dtsi | 59 allwinner,codec-analog-controls = <&codec_analog>;
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| D | at91-tse850-3.dts | 95 mux-controls = <&mux>;
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| D | sun4i-a10-gemei-g9.dts | 74 /* PH15 controls power to external amplifier (ft2012q) */
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| D | sun7i-a20-i12-tvbox.dts | 90 /* This controls VCC-PI, must be always on! */
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| /arch/arm64/boot/dts/microchip/ |
| D | sparx5_pcb125.dts | 46 mux-controls = <&mux>;
58 mux-controls = <&mux 0>;
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| D | sparx5_pcb135_board.dtsi | 58 mux-controls = <&mux>;
74 mux-controls = <&mux>;
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| D | sparx5_nand.dtsi | 18 mux-controls = <&mux>;
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| D | sparx5_pcb134_board.dtsi | 45 mux-controls = <&mux>;
61 mux-controls = <&mux>;
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| /arch/arm64/boot/dts/allwinner/ |
| D | sun50i-a64-bananapi-m64.dts | 212 * which also controls two LEDs.
237 * which also controls the power LED.
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| /arch/arm/mach-omap1/ |
| D | sleep.S | 133 @ Restore EMIFF controls
361 @ Restore EMIFF controls
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| /arch/x86/xen/ |
| D | Kconfig | 60 pv-domains with more than 512 GB of RAM. This option controls the
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| /arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1028a-qds.dts | 91 mux-controls = <&mux 0>;
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| /arch/arm/mach-s3c/ |
| D | Kconfig | 245 Compile support for wakeup-mask controls found on the S3C6400
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