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Searched refs:ne (Results 1 – 25 of 64) sorted by relevance

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/arch/arm64/lib/
Dmte.S35 b.ne 1b
56 b.ne 1b
61 b.ne 2b
79 b.ne 1b
101 b.ne 1b
127 b.ne 1b
148 b.ne 2b // which is 16*16=256 bytes
153 b.ne 1b
171 b.ne 2b
174 b.ne 1b
Dstrchr.S25 ccmp w2, wzr, #4, ne
26 b.ne 1b
Dstrncmp.S60 b.ne .Lmisaligned8
62 b.ne .Lmutual_align
163 ccmp data1w, #1, #0, ne /* NZCV = 0b0000. */
192 csinv endloop, diff, xzr, ne/*if limit_wd is 0,will finish the cmp*/
195 b.ne .Lunequal_proc
226 csinv endloop, diff, xzr, ne/*if limit_wd is 0,will finish the cmp*/
252 CPU_BE( cset result, ne )
289 ccmp data1w, #1, #0, ne /* NZCV = 0b0000. */
Dmemcmp.S53 b.ne .Lmisaligned8
55 b.ne .Lmutual_align
144 ccmp data1w, data2w, #0, ne /* NZCV = 0b0000. */
171 csinv endloop, diff, xzr, ne
197 csinv endloop, diff, xzr, ne/*if limit_wd is 0,will finish the cmp*/
239 ccmp data1w, data2w, #0, ne /* NZCV = 0b0000. */
Dclear_page.S27 b.ne 1b
36 b.ne 2b
Dstrcmp.S55 b.ne .Lmisaligned8
57 b.ne .Lmutual_align
115 ccmp data1w, #1, #0, ne /* NZCV = 0b0000. */
194 CPU_BE( cset result, ne )
Dmemchr.S28 b.ne 1b
Dmemset.S131 b.ne .Ltail63
160 b.ne .Lnot_short
203 b.ne .Ltail_maybe_long
Dstrrchr.S27 b.ne 1b
Dcopy_template.S145 b.ne .Ltail63
180 b.ne .Ltail63
Dmemmove.S149 b.ne .Ltail63
184 b.ne .Ltail63
/arch/arm64/kernel/
Dhyp-stub.S50 b.ne 1f
58 b.ne 3f
95 csinv x2, x2, xzr, ne
233 b.ne 1f
238 b.ne 1f
Dsmccc-call.S20 b.ne 1f
Defi-rt-wrapper.S43 b.ne 0f
Defi-entry.S45 b.ne 1f
/arch/ia64/lib/
Dstrncpy_from_user.S37 cmp.ne p6,p7=r8,r0
39 (p6) cmp.ne.unc p8,p0=in1,r10
Dip_fast_csum.S38 cmp.ne p6,p7=5,in1 // size other than 20 byte?
42 cmp.ne.or.andcm p6,p7=r14,r0
/arch/arc/lib/
Dstrlen.S37 bmsk.ne r12,r12,r7
56 sub.ne r3,r3,4
79 sub_s.ne r1,r1,r1
/arch/arm/lib/
Dclear_user.S41 strusr r2, r0, 1, ne, rept=2
43 it ne @ explicit IT needed for the label
/arch/ia64/kernel/
Dfsys.S89 cmp.ne p8,p0=0,r9
118 cmp.ne p8,p0=0,r9
210 cmp.ne p6, p0 = 0, r2 // Fallback if work is scheduled
230 (p8) cmp.ne p13,p0 = r2,r0 // need itc_jitter compensation, set p13
252 (p7) cmp.ne p7,p0 = r25,r3 // if cmpxchg not successful
272 cmp4.ne p7,p0 = r28,r10
348 cmp.ne p6,p0=r32,r0
349 cmp.ne p7,p0=r33,r0
361 cmp.ne p8,p0=0,r2
374 cmp.ne p8,p0=0,r2
[all …]
Divt.S130 cmp.ne p8,p0=r18,r26
231 cmp.ne p6,p7=r0,r0
233 cmp.ne.or.andcm p6,p7=r26,r20 // did *pmd change
235 cmp.ne.or.andcm p6,p7=r19,r29 // did *pud change
240 (p7) cmp.ne.or.andcm p6,p7=r25,r18 // did *pte change
285 cmp.ne p7,p0=r18,r19
329 cmp.ne p7,p0=r18,r19
364 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
415 cmp.ne p8,p0=r0,r23
1204 cmp.ne.or p6,p0=IA64_ISR_CODE_LFETCH,r18
[all …]
/arch/um/kernel/
Dtime.c339 struct time_travel_event ne = { in time_travel_update_time() local
346 __time_travel_add_event(&ne, next); in time_travel_update_time()
359 if (e == &ne) { in time_travel_update_time()
372 } while (ne.pending && !finished); in time_travel_update_time()
374 time_travel_del_event(&ne); in time_travel_update_time()
/arch/arm64/mm/
Dproc.S290 b.ne do_pgd
319 b.ne do_pud
340 b.ne do_pmd
358 b.ne do_pte
/arch/arm64/kvm/hyp/nvhe/
Dhyp-init.S199 b.ne 1f
213 b.ne 1f
/arch/arm64/kvm/hyp/
Dhyp-entry.S49 ccmp x0, #ESR_ELx_EC_HVC32, #4, ne
50 b.ne el1_trap

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