• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/mm/proc.S
4 *
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * Copyright (C) 2012 ARM Ltd.
7 * Author: Catalin Marinas <catalin.marinas@arm.com>
8 */
9
10#include <linux/init.h>
11#include <linux/linkage.h>
12#include <linux/pgtable.h>
13#include <asm/assembler.h>
14#include <asm/asm-offsets.h>
15#include <asm/asm_pointer_auth.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/cpufeature.h>
19#include <asm/alternative.h>
20#include <asm/smp.h>
21#include <asm/sysreg.h>
22
23#ifdef CONFIG_ARM64_64K_PAGES
24#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
25#elif defined(CONFIG_ARM64_16K_PAGES)
26#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
27#else /* CONFIG_ARM64_4K_PAGES */
28#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
29#endif
30
31#ifdef CONFIG_RANDOMIZE_BASE
32#define TCR_KASLR_FLAGS	TCR_NFD1
33#else
34#define TCR_KASLR_FLAGS	0
35#endif
36
37#define TCR_SMP_FLAGS	TCR_SHARED
38
39/* PTWs cacheable, inner/outer WBWA */
40#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
41
42#ifdef CONFIG_KASAN_SW_TAGS
43#define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1
44#else
45#define TCR_KASAN_SW_FLAGS 0
46#endif
47
48#ifdef CONFIG_KASAN_HW_TAGS
49#define TCR_MTE_FLAGS SYS_TCR_EL1_TCMA1 | TCR_TBI1 | TCR_TBID1
50#elif defined(CONFIG_ARM64_MTE)
51/*
52 * The mte_zero_clear_page_tags() implementation uses DC GZVA, which relies on
53 * TBI being enabled at EL1.
54 */
55#define TCR_MTE_FLAGS TCR_TBI1 | TCR_TBID1
56#else
57#define TCR_MTE_FLAGS 0
58#endif
59
60/*
61 * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
62 * changed during mte_cpu_setup to Normal Tagged if the system supports MTE.
63 */
64#define MAIR_EL1_SET							\
65	(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |	\
66	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) |	\
67	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) |		\
68	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |		\
69	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |			\
70	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) |		\
71	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED) |		\
72	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_iNC_oWB, MT_NORMAL_iNC_oWB))
73
74#ifdef CONFIG_CPU_PM
75/**
76 * cpu_do_suspend - save CPU registers context
77 *
78 * x0: virtual address of context pointer
79 *
80 * This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
81 */
82SYM_FUNC_START(cpu_do_suspend)
83	mrs	x2, tpidr_el0
84	mrs	x3, tpidrro_el0
85	mrs	x4, contextidr_el1
86	mrs	x5, osdlr_el1
87	mrs	x6, cpacr_el1
88	mrs	x7, tcr_el1
89	mrs	x8, vbar_el1
90	mrs	x9, mdscr_el1
91	mrs	x10, oslsr_el1
92	mrs	x11, sctlr_el1
93alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
94	mrs	x12, tpidr_el1
95alternative_else
96	mrs	x12, tpidr_el2
97alternative_endif
98	mrs	x13, sp_el0
99	stp	x2, x3, [x0]
100	stp	x4, x5, [x0, #16]
101	stp	x6, x7, [x0, #32]
102	stp	x8, x9, [x0, #48]
103	stp	x10, x11, [x0, #64]
104	stp	x12, x13, [x0, #80]
105	/*
106	 * Save x18 as it may be used as a platform register, e.g. by shadow
107	 * call stack.
108	 */
109	str	x18, [x0, #96]
110	ret
111SYM_FUNC_END(cpu_do_suspend)
112
113/**
114 * cpu_do_resume - restore CPU register context
115 *
116 * x0: Address of context pointer
117 */
118	.pushsection ".idmap.text", "awx"
119SYM_FUNC_START(cpu_do_resume)
120	ldp	x2, x3, [x0]
121	ldp	x4, x5, [x0, #16]
122	ldp	x6, x8, [x0, #32]
123	ldp	x9, x10, [x0, #48]
124	ldp	x11, x12, [x0, #64]
125	ldp	x13, x14, [x0, #80]
126	/*
127	 * Restore x18, as it may be used as a platform register, and clear
128	 * the buffer to minimize the risk of exposure when used for shadow
129	 * call stack.
130	 */
131	ldr	x18, [x0, #96]
132	str	xzr, [x0, #96]
133	msr	tpidr_el0, x2
134	msr	tpidrro_el0, x3
135	msr	contextidr_el1, x4
136	msr	cpacr_el1, x6
137
138	/* Don't change t0sz here, mask those bits when restoring */
139	mrs	x7, tcr_el1
140	bfi	x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
141
142	msr	tcr_el1, x8
143	msr	vbar_el1, x9
144
145	/*
146	 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
147	 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
148	 * exception. Mask them until local_daif_restore() in cpu_suspend()
149	 * resets them.
150	 */
151	disable_daif
152	msr	mdscr_el1, x10
153
154	msr	sctlr_el1, x12
155alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
156	msr	tpidr_el1, x13
157alternative_else
158	msr	tpidr_el2, x13
159alternative_endif
160	msr	sp_el0, x14
161	/*
162	 * Restore oslsr_el1 by writing oslar_el1
163	 */
164	msr	osdlr_el1, x5
165	ubfx	x11, x11, #1, #1
166	msr	oslar_el1, x11
167	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
168	reset_amuserenr_el0 x0			// Disable AMU access from EL0
169
170alternative_if ARM64_HAS_RAS_EXTN
171	msr_s	SYS_DISR_EL1, xzr
172alternative_else_nop_endif
173
174	ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
175	isb
176	ret
177SYM_FUNC_END(cpu_do_resume)
178	.popsection
179#endif
180
181	.pushsection ".idmap.text", "awx"
182
183.macro	__idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
184	adrp	\tmp1, reserved_pg_dir
185	phys_to_ttbr \tmp2, \tmp1
186	offset_ttbr1 \tmp2, \tmp1
187	msr	ttbr1_el1, \tmp2
188	isb
189	tlbi	vmalle1
190	dsb	nsh
191	isb
192.endm
193
194/*
195 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
196 *
197 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
198 * called by anything else. It can only be executed from a TTBR0 mapping.
199 */
200SYM_FUNC_START(idmap_cpu_replace_ttbr1)
201	save_and_disable_daif flags=x2
202
203	__idmap_cpu_set_reserved_ttbr1 x1, x3
204
205	offset_ttbr1 x0, x3
206	msr	ttbr1_el1, x0
207	isb
208
209	restore_daif x2
210
211	ret
212SYM_FUNC_END(idmap_cpu_replace_ttbr1)
213	.popsection
214
215#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
216	.pushsection ".idmap.text", "awx"
217
218	.macro	__idmap_kpti_get_pgtable_ent, type
219	dc	cvac, cur_\()\type\()p		// Ensure any existing dirty
220	dmb	sy				// lines are written back before
221	ldr	\type, [cur_\()\type\()p]	// loading the entry
222	tbz	\type, #0, skip_\()\type	// Skip invalid and
223	tbnz	\type, #11, skip_\()\type	// non-global entries
224	.endm
225
226	.macro __idmap_kpti_put_pgtable_ent_ng, type
227	orr	\type, \type, #PTE_NG		// Same bit for blocks and pages
228	str	\type, [cur_\()\type\()p]	// Update the entry and ensure
229	dmb	sy				// that it is visible to all
230	dc	civac, cur_\()\type\()p		// CPUs.
231	.endm
232
233/*
234 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
235 *
236 * Called exactly once from stop_machine context by each CPU found during boot.
237 */
238__idmap_kpti_flag:
239	.long	1
240SYM_FUNC_START(idmap_kpti_install_ng_mappings)
241	cpu		.req	w0
242	num_cpus	.req	w1
243	swapper_pa	.req	x2
244	swapper_ttb	.req	x3
245	flag_ptr	.req	x4
246	cur_pgdp	.req	x5
247	end_pgdp	.req	x6
248	pgd		.req	x7
249	cur_pudp	.req	x8
250	end_pudp	.req	x9
251	pud		.req	x10
252	cur_pmdp	.req	x11
253	end_pmdp	.req	x12
254	pmd		.req	x13
255	cur_ptep	.req	x14
256	end_ptep	.req	x15
257	pte		.req	x16
258
259	mrs	swapper_ttb, ttbr1_el1
260	restore_ttbr1	swapper_ttb
261	adr	flag_ptr, __idmap_kpti_flag
262
263	cbnz	cpu, __idmap_kpti_secondary
264
265	/* We're the boot CPU. Wait for the others to catch up */
266	sevl
2671:	wfe
268	ldaxr	w17, [flag_ptr]
269	eor	w17, w17, num_cpus
270	cbnz	w17, 1b
271
272	/* We need to walk swapper, so turn off the MMU. */
273	pre_disable_mmu_workaround
274	mrs	x17, sctlr_el1
275	bic	x17, x17, #SCTLR_ELx_M
276	msr	sctlr_el1, x17
277	isb
278
279	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
280	/* PGD */
281	mov	cur_pgdp, swapper_pa
282	add	end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
283do_pgd:	__idmap_kpti_get_pgtable_ent	pgd
284	tbnz	pgd, #1, walk_puds
285next_pgd:
286	__idmap_kpti_put_pgtable_ent_ng	pgd
287skip_pgd:
288	add	cur_pgdp, cur_pgdp, #8
289	cmp	cur_pgdp, end_pgdp
290	b.ne	do_pgd
291
292	/* Publish the updated tables and nuke all the TLBs */
293	dsb	sy
294	tlbi	vmalle1is
295	dsb	ish
296	isb
297
298	/* We're done: fire up the MMU again */
299	mrs	x17, sctlr_el1
300	orr	x17, x17, #SCTLR_ELx_M
301	set_sctlr_el1	x17
302
303	/* Set the flag to zero to indicate that we're all done */
304	str	wzr, [flag_ptr]
305	ret
306
307	/* PUD */
308walk_puds:
309	.if CONFIG_PGTABLE_LEVELS > 3
310	pte_to_phys	cur_pudp, pgd
311	add	end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
312do_pud:	__idmap_kpti_get_pgtable_ent	pud
313	tbnz	pud, #1, walk_pmds
314next_pud:
315	__idmap_kpti_put_pgtable_ent_ng	pud
316skip_pud:
317	add	cur_pudp, cur_pudp, 8
318	cmp	cur_pudp, end_pudp
319	b.ne	do_pud
320	b	next_pgd
321	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
322	mov	pud, pgd
323	b	walk_pmds
324next_pud:
325	b	next_pgd
326	.endif
327
328	/* PMD */
329walk_pmds:
330	.if CONFIG_PGTABLE_LEVELS > 2
331	pte_to_phys	cur_pmdp, pud
332	add	end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
333do_pmd:	__idmap_kpti_get_pgtable_ent	pmd
334	tbnz	pmd, #1, walk_ptes
335next_pmd:
336	__idmap_kpti_put_pgtable_ent_ng	pmd
337skip_pmd:
338	add	cur_pmdp, cur_pmdp, #8
339	cmp	cur_pmdp, end_pmdp
340	b.ne	do_pmd
341	b	next_pud
342	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
343	mov	pmd, pud
344	b	walk_ptes
345next_pmd:
346	b	next_pud
347	.endif
348
349	/* PTE */
350walk_ptes:
351	pte_to_phys	cur_ptep, pmd
352	add	end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
353do_pte:	__idmap_kpti_get_pgtable_ent	pte
354	__idmap_kpti_put_pgtable_ent_ng	pte
355skip_pte:
356	add	cur_ptep, cur_ptep, #8
357	cmp	cur_ptep, end_ptep
358	b.ne	do_pte
359	b	next_pmd
360
361	.unreq	cpu
362	.unreq	num_cpus
363	.unreq	swapper_pa
364	.unreq	cur_pgdp
365	.unreq	end_pgdp
366	.unreq	pgd
367	.unreq	cur_pudp
368	.unreq	end_pudp
369	.unreq	pud
370	.unreq	cur_pmdp
371	.unreq	end_pmdp
372	.unreq	pmd
373	.unreq	cur_ptep
374	.unreq	end_ptep
375	.unreq	pte
376
377	/* Secondary CPUs end up here */
378__idmap_kpti_secondary:
379	/* Uninstall swapper before surgery begins */
380	__idmap_cpu_set_reserved_ttbr1 x16, x17
381
382	/* Increment the flag to let the boot CPU we're ready */
3831:	ldxr	w16, [flag_ptr]
384	add	w16, w16, #1
385	stxr	w17, w16, [flag_ptr]
386	cbnz	w17, 1b
387
388	/* Wait for the boot CPU to finish messing around with swapper */
389	sevl
3901:	wfe
391	ldxr	w16, [flag_ptr]
392	cbnz	w16, 1b
393
394	/* All done, act like nothing happened */
395	offset_ttbr1 swapper_ttb, x16
396	msr	ttbr1_el1, swapper_ttb
397	isb
398	ret
399
400	.unreq	swapper_ttb
401	.unreq	flag_ptr
402SYM_FUNC_END(idmap_kpti_install_ng_mappings)
403	.popsection
404#endif
405
406/*
407 *	__cpu_setup
408 *
409 *	Initialise the processor for turning the MMU on.
410 *
411 * Output:
412 *	Return in x0 the value of the SCTLR_EL1 register.
413 */
414	.pushsection ".idmap.text", "awx"
415SYM_FUNC_START(__cpu_setup)
416	tlbi	vmalle1				// Invalidate local TLB
417	dsb	nsh
418
419	mov	x1, #3 << 20
420	msr	cpacr_el1, x1			// Enable FP/ASIMD
421	mov	x1, #1 << 12			// Reset mdscr_el1 and disable
422	msr	mdscr_el1, x1			// access to the DCC from EL0
423	isb					// Unmask debug exceptions now,
424	enable_dbg				// since this is per-cpu
425	reset_pmuserenr_el0 x1			// Disable PMU access from EL0
426	reset_amuserenr_el0 x1			// Disable AMU access from EL0
427
428	/*
429	 * Memory region attributes
430	 */
431	mov_q	x5, MAIR_EL1_SET
432	msr	mair_el1, x5
433	/*
434	 * Set/prepare TCR and TTBR. TCR_EL1.T1SZ gets further
435	 * adjusted if the kernel is compiled with 52bit VA support.
436	 */
437	mov_q	x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
438			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
439			TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS | TCR_MTE_FLAGS
440
441	tcr_clear_errata_bits x10, x9, x5
442
443#ifdef CONFIG_ARM64_VA_BITS_52
444	ldr_l		x9, vabits_actual
445	sub		x9, xzr, x9
446	add		x9, x9, #64
447	tcr_set_t1sz	x10, x9
448#else
449	ldr_l		x9, idmap_t0sz
450#endif
451	tcr_set_t0sz	x10, x9
452
453	/*
454	 * Set the IPS bits in TCR_EL1.
455	 */
456	tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
457#ifdef CONFIG_ARM64_HW_AFDBM
458	/*
459	 * Enable hardware update of the Access Flags bit.
460	 * Hardware dirty bit management is enabled later,
461	 * via capabilities.
462	 */
463	mrs	x9, ID_AA64MMFR1_EL1
464	and	x9, x9, #0xf
465	cbz	x9, 1f
466	orr	x10, x10, #TCR_HA		// hardware Access flag update
4671:
468#endif	/* CONFIG_ARM64_HW_AFDBM */
469	msr	tcr_el1, x10
470	/*
471	 * Prepare SCTLR
472	 */
473	mov_q	x0, INIT_SCTLR_EL1_MMU_ON
474	ret					// return to head.S
475SYM_FUNC_END(__cpu_setup)
476