Home
last modified time | relevance | path

Searched refs:u32 (Results 1 – 25 of 2041) sorted by relevance

12345678910>>...82

/arch/mips/include/asm/sgi/
Dmc.h17 u32 _unused0;
18 volatile u32 cpuctrl0; /* CPU control register 0, readwrite */
38 u32 _unused1;
39 volatile u32 cpuctrl1; /* CPU control register 1, readwrite */
48 u32 _unused2;
49 volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
51 u32 _unused3;
52 volatile u32 systemid; /* MC system ID register, readonly */
56 u32 _unused4[3];
57 volatile u32 divider; /* Divider reg for RPSS */
[all …]
Dhpc3.h20 u32 pbuf; /* physical address of data buffer */
21 u32 cntinfo; /* counter and info bits */
33 u32 pnext; /* paddr of next hpc_dma_desc if any */
38 volatile u32 pbdma_bptr; /* pbus dma channel buffer ptr */
39 volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */
40 u32 _unused0[0x1000/4 - 2]; /* padding */
41 volatile u32 pbdma_ctrl; /* pbus dma channel control register has
58 u32 _unused1[0x1000/4 - 1]; /* padding */
63 volatile u32 cbptr; /* current dma buffer ptr, diagnostic use only */
64 volatile u32 ndptr; /* next dma descriptor ptr */
[all …]
/arch/arm/mach-iop32x/
Diop3xx.h50 #define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
61 #define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
66 #define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
67 #define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
68 #define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
69 #define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
70 #define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
71 #define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
74 #define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
79 #define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
[all …]
/arch/powerpc/include/asm/
Dmpc5121.h11 u32 rcwlr; /* Reset Configuration Word Low Register */
12 u32 rcwhr; /* Reset Configuration Word High Register */
13 u32 reserved1;
14 u32 reserved2;
15 u32 rsr; /* Reset Status Register */
16 u32 rmr; /* Reset Mode Register */
17 u32 rpr; /* Reset Protection Register */
18 u32 rcr; /* Reset Control Register */
19 u32 rcer; /* Reset Control Enable Register */
26 u32 spmr; /* System PLL Mode Register */
[all …]
Dimmap_cpm2.h19 u32 sc_siumcr;
20 u32 sc_sypcr;
24 u32 sc_bcr;
27 u32 sc_ppc_alrh;
28 u32 sc_ppc_alrl;
31 u32 sc_lcl_alrh;
32 u32 sc_lcl_alrl;
33 u32 sc_tescr1;
34 u32 sc_tescr2;
35 u32 sc_ltescr1;
[all …]
Dmpc52xx.h38 u32 mbar; /* MMAP_CTRL + 0x00 */
40 u32 cs0_start; /* MMAP_CTRL + 0x04 */
41 u32 cs0_stop; /* MMAP_CTRL + 0x08 */
42 u32 cs1_start; /* MMAP_CTRL + 0x0c */
43 u32 cs1_stop; /* MMAP_CTRL + 0x10 */
44 u32 cs2_start; /* MMAP_CTRL + 0x14 */
45 u32 cs2_stop; /* MMAP_CTRL + 0x18 */
46 u32 cs3_start; /* MMAP_CTRL + 0x1c */
47 u32 cs3_stop; /* MMAP_CTRL + 0x20 */
48 u32 cs4_start; /* MMAP_CTRL + 0x24 */
[all …]
Dcell-pmu.h66 extern u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
67 extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
68 extern u32 cbe_read_ctr(u32 cpu, u32 ctr);
69 extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
71 extern u32 cbe_read_pm07_control(u32 cpu, u32 ctr);
72 extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
73 extern u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg);
74 extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
76 extern u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
77 extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
[all …]
Dxive.h30 extern u32 xive_tima_offset;
45 u32 esb_shift;
47 u32 hw_irq;
76 u32 msk;
77 u32 idx;
78 u32 toggle;
80 u32 esc_irq;
84 u32 guest_qshift;
104 int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d);
107 u32 xive_native_default_eq_shift(void);
[all …]
Dpmac_pfunc.h26 u32 v;
27 u32 *p;
67 int (*write_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
68 int (*read_reg32)(PMF_STD_ARGS, u32 offset);
69 int (*write_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask);
70 int (*read_reg16)(PMF_STD_ARGS, u32 offset);
71 int (*write_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask);
72 int (*read_reg8)(PMF_STD_ARGS, u32 offset);
74 int (*delay)(PMF_STD_ARGS, u32 duration);
76 int (*wait_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
[all …]
Dkvm_fpu.h14 extern void fps_fres(u64 *fpscr, u32 *dst, u32 *src1);
15 extern void fps_frsqrte(u64 *fpscr, u32 *dst, u32 *src1);
16 extern void fps_fsqrts(u64 *fpscr, u32 *dst, u32 *src1);
18 extern void fps_fadds(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
19 extern void fps_fdivs(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
20 extern void fps_fmuls(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
21 extern void fps_fsubs(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
23 extern void fps_fmadds(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2,
24 u32 *src3);
25 extern void fps_fmsubs(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2,
[all …]
Dbootx.h26 u32 name;
28 u32 value;
29 u32 next;
33 u32 unused0;
34 u32 unused1;
35 u32 phandle; /* not really available */
36 u32 unused2;
37 u32 unused3;
38 u32 unused4;
39 u32 unused5;
[all …]
/arch/s390/include/asm/
Dstp.h16 u32 : 14;
17 u32 tsc : 1; /* Timing status change */
18 u32 lac : 1; /* Link availability change */
19 u32 tcpc : 1; /* Time control parameter change */
20 u32 : 15;
27 u32 : 32;
28 u32 tu : 1;
29 u32 lu : 1;
30 u32 : 6;
31 u32 stratum : 8;
[all …]
Dfcx.h38 u32 format:2;
39 u32 :6;
40 u32 flags:24;
41 u32 :8;
42 u32 tccbl:6;
43 u32 r:1;
44 u32 w:1;
45 u32 :16;
50 u32 output_count;
51 u32 input_count;
[all …]
/arch/arm/mach-omap2/
Domap-secure.h67 extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
68 u32 arg1, u32 arg2, u32 arg3, u32 arg4);
69 extern void omap_smccc_smc(u32 fn, u32 arg);
70 extern void omap_smc1(u32 fn, u32 arg);
71 extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
72 extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs);
75 extern u32 save_secure_ram_context(u32 args_pa);
76 extern u32 omap3_save_secure_ram(void __iomem *save_regs, int size);
78 extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
79 u32 arg1, u32 arg2, u32 arg3, u32 arg4);
[all …]
Dsram.h9 extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
10 u32 base_cs, u32 force_unlock);
11 extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
12 u32 mem_type);
13 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
18 extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
21 extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
22 u32 base_cs, u32 force_unlock);
25 extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
29 extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
[all …]
Domap-secure.c59 u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, in omap_secure_dispatcher()
60 u32 arg3, u32 arg4) in omap_secure_dispatcher()
62 u32 ret; in omap_secure_dispatcher()
63 u32 param[5]; in omap_secure_dispatcher()
82 void omap_smccc_smc(u32 fn, u32 arg) in omap_smccc_smc()
91 void omap_smc1(u32 fn, u32 arg) in omap_smc1()
106 u32 size = OMAP_SECURE_RAM_STORAGE; in omap_secure_ram_reserve_memblock()
120 u32 omap3_save_secure_ram(void __iomem *addr, int size) in omap3_save_secure_ram()
122 u32 ret; in omap3_save_secure_ram()
123 u32 param[5]; in omap3_save_secure_ram()
[all …]
/arch/microblaze/include/asm/
Dcpuinfo.h32 u32 use_instr;
33 u32 use_mult;
34 u32 use_fpu;
35 u32 use_exc;
36 u32 ver_code;
37 u32 mmu;
38 u32 mmu_privins;
39 u32 endian;
42 u32 use_icache;
43 u32 icache_tagbits;
[all …]
/arch/mips/include/asm/mach-rc32434/
Deth.h36 u32 ethintfc;
37 u32 ethfifott;
38 u32 etharc;
39 u32 ethhash0;
40 u32 ethhash1;
41 u32 ethu0[4]; /* Reserved. */
42 u32 ethpfs;
43 u32 ethmcp;
44 u32 eth_u1[10]; /* Reserved. */
45 u32 ethspare;
[all …]
/arch/mips/include/asm/txx9/
Dtx4927pcic.h16 u32 pciid;
17 u32 pcistatus;
18 u32 pciccrev;
19 u32 pcicfg1;
20 u32 p2gm0plbase; /* +10 */
21 u32 p2gm0pubase;
22 u32 p2gm1plbase;
23 u32 p2gm1pubase;
24 u32 p2gm2pbase; /* +20 */
25 u32 p2giopbase;
[all …]
/arch/x86/include/asm/
Dapicdef.h177 #define u32 unsigned int macro
181 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
183 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
186 u32 __reserved_1 : 24,
189 u32 __reserved[3];
194 u32 version : 8,
198 u32 __reserved[3];
201 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
203 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
205 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
[all …]
/arch/powerpc/sysdev/
Dfsl_85xx_cache_ctlr.h38 u32 ctl; /* 0x000 - L2 control */
40 u32 ewar0; /* 0x010 - External write address 0 */
41 u32 ewarea0; /* 0x014 - External write address extended 0 */
42 u32 ewcr0; /* 0x018 - External write ctrl */
44 u32 ewar1; /* 0x020 - External write address 1 */
45 u32 ewarea1; /* 0x024 - External write address extended 1 */
46 u32 ewcr1; /* 0x028 - External write ctrl 1 */
48 u32 ewar2; /* 0x030 - External write address 2 */
49 u32 ewarea2; /* 0x034 - External write address extended 2 */
50 u32 ewcr2; /* 0x038 - External write ctrl 2 */
[all …]
/arch/arm64/include/asm/
Dcpu.h16 u32 reg_id_dfr0;
17 u32 reg_id_dfr1;
18 u32 reg_id_isar0;
19 u32 reg_id_isar1;
20 u32 reg_id_isar2;
21 u32 reg_id_isar3;
22 u32 reg_id_isar4;
23 u32 reg_id_isar5;
24 u32 reg_id_isar6;
25 u32 reg_id_mmfr0;
[all …]
/arch/mips/include/asm/mach-au1x00/
Dau1xxx_dbdma.h41 u32 ddma_config;
42 u32 ddma_intstat;
43 u32 ddma_throttle;
44 u32 ddma_inten;
56 u32 ddma_cfg; /* See below */
57 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
58 u32 ddma_statptr; /* word aligned pointer to status word */
59 u32 ddma_dbell; /* A write activates channel operation */
60 u32 ddma_irq; /* If bit 0 set, interrupt pending */
61 u32 ddma_stat; /* See below */
[all …]
/arch/x86/kvm/
Dtss.h6 u32 prev_task_link;
7 u32 esp0;
8 u32 ss0;
9 u32 esp1;
10 u32 ss1;
11 u32 esp2;
12 u32 ss2;
13 u32 cr3;
14 u32 eip;
15 u32 eflags;
[all …]
/arch/mips/include/asm/sn/
Dioc3.h13 u32 sscr;
14 u32 stpir;
15 u32 stcir;
16 u32 srpir;
17 u32 srcir;
18 u32 srtr;
19 u32 shadow;
74 u32 emcr; /* 0x000f0 */
75 u32 eisr; /* 0x000f4 */
76 u32 eier; /* 0x000f8 */
[all …]

12345678910>>...82