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Searched refs:x86_pmu (Results 1 – 14 of 14) sorted by relevance

/arch/x86/events/intel/
Dlbr.c197 if (pmi && x86_pmu.version >= 4) in __intel_pmu_lbr_enable()
205 lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask; in __intel_pmu_lbr_enable()
249 for (i = 0; i < x86_pmu.lbr_nr; i++) in intel_pmu_lbr_reset_32()
250 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_32()
257 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_lbr_reset_64()
258 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_64()
259 wrmsrl(x86_pmu.lbr_to + i, 0); in intel_pmu_lbr_reset_64()
260 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) in intel_pmu_lbr_reset_64()
261 wrmsrl(x86_pmu.lbr_info + i, 0); in intel_pmu_lbr_reset_64()
268 wrmsrl(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr); in intel_pmu_arch_lbr_reset()
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Dcore.c1992 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); in __intel_pmu_enable_all()
2260 if (left == x86_pmu.max_period) { in icl_set_topdown_event_period()
2420 x86_pmu.update_topdown_event(event); in intel_pmu_read_topdown_event()
2428 else if (is_topdown_count(event) && x86_pmu.update_topdown_event) in intel_pmu_read_event()
2469 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) in intel_pmu_enable_fixed()
2476 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { in intel_pmu_enable_fixed()
2553 if (!x86_pmu.num_counters) in intel_pmu_reset()
2560 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in intel_pmu_reset()
2564 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) in intel_pmu_reset()
2571 if (x86_pmu.version >= 2) { in intel_pmu_reset()
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Dds.c181 if (x86_pmu.pebs_no_tlb) { in load_latency_data()
339 size_t bsiz = x86_pmu.pebs_buffer_size; in alloc_pebs_buffer()
343 if (!x86_pmu.pebs) in alloc_pebs_buffer()
354 if (x86_pmu.intel_cap.pebs_format < 2) { in alloc_pebs_buffer()
368 max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size); in alloc_pebs_buffer()
378 if (!x86_pmu.pebs) in release_pebs_buffer()
386 ds_clear_cea(cea, x86_pmu.pebs_buffer_size); in release_pebs_buffer()
387 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size); in release_pebs_buffer()
398 if (!x86_pmu.bts) in alloc_bts_buffer()
425 if (!x86_pmu.bts) in release_bts_buffer()
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Dp6.c201 static __initconst const struct x86_pmu p6_pmu = {
242 x86_pmu.attr_rdpmc_broken = 1; in p6_pmu_rdpmc_quirk()
243 x86_pmu.attr_rdpmc = 0; in p6_pmu_rdpmc_quirk()
249 x86_pmu = p6_pmu; in p6_pmu_init()
Dknc.c290 static const struct x86_pmu knc_pmu __initconst = {
316 x86_pmu = knc_pmu; in knc_pmu_init()
Dp4.c922 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in p4_pmu_disable_all()
991 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in p4_pmu_enable_all()
1010 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in p4_pmu_handle_irq()
1029 if (!overflow && (val & (1ULL << (x86_pmu.cntval_bits - 1)))) in p4_pmu_handle_irq()
1302 static __initconst const struct x86_pmu p4_pmu = {
1360 x86_pmu = p4_pmu; in p4_pmu_init()
1371 for (i = 0; i < x86_pmu.num_counters; i++) { in p4_pmu_init()
Dbts.c584 if (!boot_cpu_has(X86_FEATURE_DTES64) || !x86_pmu.bts) in bts_init()
/arch/x86/events/
Dcore.c47 struct x86_pmu x86_pmu __read_mostly;
62 DEFINE_STATIC_CALL_NULL(x86_pmu_handle_irq, *x86_pmu.handle_irq);
63 DEFINE_STATIC_CALL_NULL(x86_pmu_disable_all, *x86_pmu.disable_all);
64 DEFINE_STATIC_CALL_NULL(x86_pmu_enable_all, *x86_pmu.enable_all);
65 DEFINE_STATIC_CALL_NULL(x86_pmu_enable, *x86_pmu.enable);
66 DEFINE_STATIC_CALL_NULL(x86_pmu_disable, *x86_pmu.disable);
68 DEFINE_STATIC_CALL_NULL(x86_pmu_add, *x86_pmu.add);
69 DEFINE_STATIC_CALL_NULL(x86_pmu_del, *x86_pmu.del);
70 DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read);
72 DEFINE_STATIC_CALL_NULL(x86_pmu_schedule_events, *x86_pmu.schedule_events);
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Dperf_event.h633 struct x86_pmu { struct
862 __quirk.next = x86_pmu.quirks; \
863 x86_pmu.quirks = &__quirk; \
903 extern struct x86_pmu x86_pmu __read_mostly;
915 return x86_pmu.lbr_sel_map && in x86_pmu_has_lbr_callstack()
916 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; in x86_pmu_has_lbr_callstack()
946 return x86_pmu.eventsel + (x86_pmu.addr_offset ? in x86_pmu_config_addr()
947 x86_pmu.addr_offset(index, true) : index); in x86_pmu_config_addr()
952 return x86_pmu.perfctr + (x86_pmu.addr_offset ? in x86_pmu_event_addr()
953 x86_pmu.addr_offset(index, false) : index); in x86_pmu_event_addr()
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/arch/x86/events/zhaoxin/
Dcore.c262 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); in zhaoxin_pmu_enable_all()
370 if (x86_pmu.enabled_ack) in zhaoxin_pmu_handle_irq()
427 if (x86_pmu.event_constraints) { in zhaoxin_get_event_constraints()
428 for_each_event_constraint(c, x86_pmu.event_constraints) { in zhaoxin_get_event_constraints()
459 static const struct x86_pmu zhaoxin_pmu __initconst = {
498 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(zx_arch_events_map)) { in zhaoxin_arch_events_quirk()
529 x86_pmu = zhaoxin_pmu; in zhaoxin_pmu_init()
532 x86_pmu.version = version; in zhaoxin_pmu_init()
533 x86_pmu.num_counters = eax.split.num_counters; in zhaoxin_pmu_init()
534 x86_pmu.cntval_bits = eax.split.bit_width; in zhaoxin_pmu_init()
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/arch/x86/events/amd/
Dcore.c319 if (!(x86_pmu.flags & PMU_FL_PAIR)) in amd_is_pair_event_code()
343 if ((x86_pmu.flags & PMU_FL_PAIR) && amd_is_pair_event_code(&event->hw)) in amd_core_hw_config()
396 for (i = 0; i < x86_pmu.num_counters; i++) { in __amd_put_nb_event_constraints()
463 for_each_set_bit(idx, c->idxmsk, x86_pmu.num_counters) { in __amd_get_nb_event_constraints()
506 for (i = 0; i < x86_pmu.num_counters; i++) { in amd_alloc_nb()
519 if (!x86_pmu.amd_nb_constraints) in amd_pmu_cpu_prepare()
538 if (!x86_pmu.amd_nb_constraints) in amd_pmu_cpu_starting()
564 if (!x86_pmu.amd_nb_constraints) in amd_pmu_cpu_dead()
600 if (counter & (1ULL << (x86_pmu.cntval_bits - 1))) in amd_pmu_wait_on_overflow()
629 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in amd_pmu_disable_all()
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/arch/x86/kvm/vmx/
Dpmu_intel.c328 struct x86_pmu_capability x86_pmu; in intel_pmu_refresh() local
355 perf_get_x86_pmu_capability(&x86_pmu); in intel_pmu_refresh()
358 x86_pmu.num_counters_gp); in intel_pmu_refresh()
359 eax.split.bit_width = min_t(int, eax.split.bit_width, x86_pmu.bit_width_gp); in intel_pmu_refresh()
361 eax.split.mask_length = min_t(int, eax.split.mask_length, x86_pmu.events_mask_len); in intel_pmu_refresh()
370 x86_pmu.num_counters_fixed); in intel_pmu_refresh()
372 edx.split.bit_width_fixed, x86_pmu.bit_width_fixed); in intel_pmu_refresh()
/arch/x86/xen/
Dpmu.c501 if (x86_pmu.handle_irq(&regs)) in xen_pmu_irq_handler()
/arch/x86/kvm/
Dx86.c5946 struct x86_pmu_capability x86_pmu; in kvm_init_msr_list() local
5953 perf_get_x86_pmu_capability(&x86_pmu); in kvm_init_msr_list()
6005 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) in kvm_init_msr_list()
6010 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) in kvm_init_msr_list()