| /drivers/clocksource/ |
| D | timer-atcpit100.c | 36 #define INT_EN 0x14 macro
256 val = readl(base + INT_EN); in atcpit100_timer_init()
257 writel(val | CH0INT0EN, base + INT_EN); in atcpit100_timer_init()
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| /drivers/mmc/host/ |
| D | ushc.c | 114 #define INT_EN 1 macro
184 && test_bit(INT_EN, &ushc->flags) in int_callback()
192 if (!test_bit(INT_EN, &ushc->flags)) in int_callback()
392 set_bit(INT_EN, &ushc->flags); in ushc_enable_sdio_irq()
394 clear_bit(INT_EN, &ushc->flags); in ushc_enable_sdio_irq()
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| /drivers/net/ethernet/oki-semi/pch_gbe/ |
| D | pch_gbe_main.c | 463 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN); in pch_gbe_mac_set_wol_event()
742 iowrite32(0, &hw->reg->INT_EN); in pch_gbe_irq_disable()
747 ioread32(&hw->reg->INT_EN)); in pch_gbe_irq_disable()
759 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN); in pch_gbe_irq_enable()
762 ioread32(&hw->reg->INT_EN)); in pch_gbe_irq_enable()
1282 int_st = int_st & ioread32(&hw->reg->INT_EN); in pch_gbe_intr()
1294 int_en = ioread32(&hw->reg->INT_EN); in pch_gbe_intr()
1296 &hw->reg->INT_EN); in pch_gbe_intr()
1299 int_st = int_st & ioread32(&hw->reg->INT_EN); in pch_gbe_intr()
1313 int_en = ioread32(&hw->reg->INT_EN); in pch_gbe_intr()
[all …]
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| D | pch_gbe.h | 39 u32 INT_EN; member
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| /drivers/net/ethernet/smsc/ |
| D | smsc911x.c | 1224 temp = smsc911x_reg_read(pdata, INT_EN); in smsc911x_poll()
1226 smsc911x_reg_write(pdata, INT_EN, temp); in smsc911x_poll()
1518 smsc911x_reg_write(pdata, INT_EN, 0); in smsc911x_disable_irq_chip()
1527 u32 inten = smsc911x_reg_read(pdata, INT_EN); in smsc911x_irqhandler()
1532 temp = smsc911x_reg_read(pdata, INT_EN); in smsc911x_irqhandler()
1534 smsc911x_reg_write(pdata, INT_EN, temp); in smsc911x_irqhandler()
1569 temp = smsc911x_reg_read(pdata, INT_EN); in smsc911x_irqhandler()
1571 smsc911x_reg_write(pdata, INT_EN, temp); in smsc911x_irqhandler()
1670 temp = smsc911x_reg_read(pdata, INT_EN); in smsc911x_open()
1672 smsc911x_reg_write(pdata, INT_EN, temp); in smsc911x_open()
[all …]
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| D | smc911x.h | 376 #define INT_EN (0x5C) macro
708 #define SMC_GET_INT_EN(lp) SMC_inl( lp, INT_EN )
709 #define SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN )
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| D | smsc911x.h | 140 #define INT_EN 0x5C macro
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| /drivers/thermal/qcom/ |
| D | tsens.c | 565 ret = regmap_field_write(priv->rf[INT_EN], val); in tsens_enable_irq()
575 regmap_field_write(priv->rf[INT_EN], 0); in tsens_disable_irq()
789 priv->rf[INT_EN] = devm_regmap_field_alloc(dev, priv->tm_map, in init_common()
790 priv->fields[INT_EN]); in init_common()
791 if (IS_ERR(priv->rf[INT_EN])) { in init_common()
792 ret = PTR_ERR(priv->rf[INT_EN]); in init_common()
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| D | tsens-v2.c | 52 [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 2),
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| D | tsens-v1.c | 294 [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0),
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| D | tsens.h | 169 INT_EN, /* v2+ has separate enables for crit, upper and lower irq */ enumerator
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| D | tsens-v0_1.c | 475 [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0),
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| /drivers/gpu/drm/vc4/ |
| D | vc4_dsi.c | 1234 DSI_PORT_WRITE(INT_EN, (DSI0_INTERRUPTS_ALWAYS_ENABLED | in vc4_dsi_host_transfer()
1237 DSI_PORT_WRITE(INT_EN, in vc4_dsi_host_transfer()
1246 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED | in vc4_dsi_host_transfer()
1249 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED | in vc4_dsi_host_transfer()
1268 DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED)); in vc4_dsi_host_transfer()
1314 DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED)); in vc4_dsi_host_transfer()
1606 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED); in vc4_dsi_bind()
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| /drivers/staging/comedi/drivers/ |
| D | ni_pcidio.c | 250 #define INT_EN (COUNT_EXPIRED | WAITED | PRIMARY_TC | SECONDARY_TC) macro
252 #define INT_EN (TRANSFER_READY | COUNT_EXPIRED | WAITED \ macro
413 flags &= INT_EN; in nidio_interrupt()
712 writeb(INT_EN, dev->mmio + INTERRUPT_CONTROL); in ni_pcidio_cmd()
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| /drivers/gpu/drm/imx/dcss/ |
| D | dcss-ss.c | 59 #define INT_EN BIT(0) macro
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| /drivers/scsi/mvsas/ |
| D | mv_defs.h | 71 INT_EN = (1U << 1), /* Global int enable */ enumerator
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| D | mv_64xx.c | 426 mw32(MVS_GBL_CTL, tmp | INT_EN); in mvs_64xx_interrupt_enable()
435 mw32(MVS_GBL_CTL, tmp & ~INT_EN); in mvs_64xx_interrupt_disable()
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