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Searched refs:RCR (Results 1 – 23 of 23) sorted by relevance

/drivers/net/ethernet/smsc/
Dsmc9194.h80 #define RCR 4 macro
207 #define SMC_DELAY() { inw( ioaddr + RCR );\
208 inw( ioaddr + RCR );\
209 inw( ioaddr + RCR ); }
Dsmc9194.c324 outw( RCR_SOFTRESET, ioaddr + RCR ); in smc_reset()
331 outw( RCR_CLEAR, ioaddr + RCR ); in smc_reset()
364 outw( RCR_NORMAL, ioaddr + RCR ); in smc_enable()
393 outb( RCR_CLEAR, ioaddr + RCR ); in smc_shutdown()
1456 outw( inw(ioaddr + RCR ) | RCR_PROMISC, ioaddr + RCR ); in smc_set_multicast_list()
1468 outw( inw(ioaddr + RCR ) | RCR_ALMUL, ioaddr + RCR ); in smc_set_multicast_list()
1477 outw( inw( ioaddr + RCR ) & ~(RCR_PROMISC | RCR_ALMUL), in smc_set_multicast_list()
1478 ioaddr + RCR ); in smc_set_multicast_list()
1484 outw( inw( ioaddr + RCR ) & ~(RCR_PROMISC | RCR_ALMUL), in smc_set_multicast_list()
1485 ioaddr + RCR ); in smc_set_multicast_list()
Dsmc91c92_cs.c225 #define RCR 4 macro
1097 mask_bits(0xff00, ioaddr + RCR); in smc_close()
1576 outw(rx_cfg_setting, ioaddr + RCR); in set_rx_mode()
1648 outw(RCR_SOFTRESET, ioaddr + RCR); in smc_reset()
1652 outw(RCR_CLEAR, ioaddr + RCR); in smc_reset()
/drivers/staging/rtl8712/
Dhal_init.c335 r8712_read32(padapter, RCR)); in rtl8712_hal_init()
336 val32 = r8712_read32(padapter, RCR); in rtl8712_hal_init()
337 r8712_write32(padapter, RCR, (val32 | BIT(26))); /* Enable RX TCP in rtl8712_hal_init()
341 r8712_read32(padapter, RCR)); in rtl8712_hal_init()
342 val32 = r8712_read32(padapter, RCR); in rtl8712_hal_init()
343 r8712_write32(padapter, RCR, (val32 | BIT(25))); /* Append PHY status */ in rtl8712_hal_init()
Drtl8712_cmdctrl_regdef.h13 #define RCR (RTL8712_CMDCTRL_ + 0x0008) macro
Drtl871x_mp_ioctl.c267 r8712_write8(Adapter, RCR, 0); /* RCR : disable all pkt, 0x10250048 */ in oid_rt_pro_start_test_hdl()
269 r8712_write8(Adapter, RCR + 2, 0x57); in oid_rt_pro_start_test_hdl()
818 rcr_val32 = r8712_read32(Adapter, RCR);/*RCR = 0x10250048*/ in oid_rt_set_rx_packet_type_hdl()
842 r8712_write32(Adapter, RCR, rcr_val32); in oid_rt_set_rx_packet_type_hdl()
/drivers/rtc/
Drtc-r9701.c38 #define RCR 0x0f /* RTC Control Register */ macro
/drivers/tty/
Dsynclink_gt.c371 #define RCR 0x86 /* rx control */ macro
2650 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3); in rx_enable()
3891 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_stop()
3892 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ in rx_stop()
3893 wr_reg16(info, RCR, val); /* clear reset bit */ in rx_stop()
3916 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_start()
3917 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ in rx_start()
3918 wr_reg16(info, RCR, val); /* clear reset bit */ in rx_start()
3949 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); in rx_start()
4126 wr_reg16(info, RCR, val); in async_mode()
[all …]
/drivers/staging/rtl8192u/
Dr8192U_hw.h84 RCR = 0x044, // Receive Configuration Register enumerator
Dr8192U_core.c759 read_nic_dword(dev, RCR, &rxconf); in rtl8192_set_rxconf()
792 write_nic_dword(dev, RCR, rxconf); in rtl8192_set_rxconf()
1715 read_nic_dword(dev, RCR, &reg); in rtl8192_link_change()
1720 write_nic_dword(dev, RCR, reg); in rtl8192_link_change()
2719 write_nic_dword(dev, RCR, priv->ReceiveConfig); in rtl8192_adapter_start()
/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
Dfw.c289 tmpu4b = rtl_read_dword(rtlpriv, RCR); in _rtl92s_firmware_checkready()
290 rtl_write_dword(rtlpriv, RCR, (tmpu4b | RCR_APPFCS | in _rtl92s_firmware_checkready()
Dhw.c285 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]); in rtl92se_set_hw_reg()
765 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config); in _rtl92se_macconfig_after_fwdownload()
988 rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR); in rtl92se_hw_init()
990 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config); in rtl92se_hw_init()
Dreg.h37 #define RCR 0x0048 macro
/drivers/net/usb/
Drtl8150.c25 #define RCR 0x0130 macro
629 set_registers(dev, RCR, 1, &rcr); in enable_net_traffic()
672 async_set_registers(dev, RCR, sizeof(rx_creg), rx_creg); in rtl8150_set_multicast()
/drivers/net/ethernet/microchip/
Dencx24j600_hw.h66 #define RCR(addr) (RCRCODE | (addr & ADDR_MASK)) /* Read Control Register */ macro
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_dev.c129 RegRCR = rtl92e_readl(dev, RCR); in rtl92e_set_reg()
137 rtl92e_writel(dev, RCR, RegRCR); in rtl92e_set_reg()
763 rtl92e_writel(dev, RCR, priv->ReceiveConfig); in rtl92e_start_adapter()
990 reg = rtl92e_readl(dev, RCR); in rtl92e_link_change()
999 rtl92e_writel(dev, RCR, reg); in rtl92e_link_change()
1014 rtl92e_writel(dev, RCR, priv->ReceiveConfig); in rtl92e_set_monitor_mode()
Dr8192E_hw.h129 RCR = 0x044, enumerator
/drivers/net/wan/
Dhd64572.h105 #define RCR 0x156 /* Rx DMA Critical Request Reg */ macro
/drivers/spi/
Dspi-atmel.c881 spi_writel(as, RCR, len); in atmel_spi_pdc_next_xfer()
1370 spi_readl(as, TCR), spi_readl(as, RCR)); in atmel_spi_one_transfer()
1378 spi_writel(as, RCR, 0); in atmel_spi_one_transfer()
/drivers/net/ethernet/renesas/
Dravb.h77 RCR = 0x0090, enumerator
Dravb_main.c449 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); in ravb_dmac_init()
/drivers/net/ethernet/via/
Dvia-velocity.h970 volatile u8 RCR; member
Dvia-velocity.c1170 BYTE_REG_BITS_ON(rx_mode, &regs->RCR); in velocity_set_multi()