| /drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_cfg.c | 21 .caps = MDP_CAP_SMP |
41 .caps = MDP_PIPE_CAP_HFLIP |
50 .caps = MDP_PIPE_CAP_HFLIP |
58 .caps = MDP_PIPE_CAP_HFLIP |
67 .caps = MDP_LM_CAP_DISPLAY, },
69 .caps = MDP_LM_CAP_DISPLAY, },
71 .caps = MDP_LM_CAP_DISPLAY, },
73 .caps = MDP_LM_CAP_WB },
75 .caps = MDP_LM_CAP_WB },
105 .caps = MDP_CAP_SMP |
[all …]
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| D | mdp5_pipe.c | 10 uint32_t caps, uint32_t blkcfg, in mdp5_pipe_assign() argument
45 if (caps & ~cur->caps) in mdp5_pipe_assign()
52 if (cur->caps & MDP_PIPE_CAP_CURSOR && in mdp5_pipe_assign()
59 if (!(*hwpipe) || (hweight_long(cur->caps & ~caps) < in mdp5_pipe_assign()
60 hweight_long((*hwpipe)->caps & ~caps))) { in mdp5_pipe_assign()
70 if (r_cur->caps != cur->caps) in mdp5_pipe_assign()
110 (*hwpipe)->name, plane->name, caps); in mdp5_pipe_assign()
115 (*r_hwpipe)->name, plane->name, caps); in mdp5_pipe_assign()
160 uint32_t reg_offset, uint32_t caps) in mdp5_pipe_init() argument
171 hwpipe->caps = caps; in mdp5_pipe_init()
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| /drivers/net/wireless/ath/ath5k/ |
| D | caps.c | 35 struct ath5k_capabilities *caps = &ah->ah_capabilities; in ath5k_hw_set_capabilities() local
39 ee_header = caps->cap_eeprom.ee_header; in ath5k_hw_set_capabilities()
46 caps->cap_range.range_5ghz_min = 5120; in ath5k_hw_set_capabilities()
47 caps->cap_range.range_5ghz_max = 5430; in ath5k_hw_set_capabilities()
48 caps->cap_range.range_2ghz_min = 0; in ath5k_hw_set_capabilities()
49 caps->cap_range.range_2ghz_max = 0; in ath5k_hw_set_capabilities()
52 __set_bit(AR5K_MODE_11A, caps->cap_mode); in ath5k_hw_set_capabilities()
69 if (ath_is_49ghz_allowed(caps->cap_eeprom.ee_regdomain)) in ath5k_hw_set_capabilities()
70 caps->cap_range.range_5ghz_min = 4920; in ath5k_hw_set_capabilities()
72 caps->cap_range.range_5ghz_min = 5005; in ath5k_hw_set_capabilities()
[all …]
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| /drivers/net/ethernet/netronome/nfp/ |
| D | nfp_net_ctrl.c | 12 static void nfp_net_tlv_caps_reset(struct nfp_net_tlv_caps *caps) in nfp_net_tlv_caps_reset() argument
14 memset(caps, 0, sizeof(*caps)); in nfp_net_tlv_caps_reset()
15 caps->me_freq_mhz = 1200; in nfp_net_tlv_caps_reset()
16 caps->mbox_off = NFP_NET_CFG_MBOX_BASE; in nfp_net_tlv_caps_reset()
17 caps->mbox_len = NFP_NET_CFG_MBOX_VAL_MAX_SZ; in nfp_net_tlv_caps_reset()
21 nfp_net_tls_parse_crypto_ops(struct device *dev, struct nfp_net_tlv_caps *caps, in nfp_net_tls_parse_crypto_ops() argument
27 if (caps->tls_resync_ss && !rx_stream_scan) in nfp_net_tls_parse_crypto_ops()
37 caps->crypto_ops = readl(data); in nfp_net_tls_parse_crypto_ops()
38 caps->crypto_enable_off = data - ctrl_mem + 16; in nfp_net_tls_parse_crypto_ops()
39 caps->tls_resync_ss = rx_stream_scan; in nfp_net_tls_parse_crypto_ops()
[all …]
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| /drivers/net/ethernet/mellanox/mlx4/ |
| D | main.c | 300 dev->caps.reserved_uars = in mlx4_set_num_reserved_uars()
312 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { in mlx4_check_port_params()
313 for (i = 0; i < dev->caps.num_ports - 1; i++) { in mlx4_check_port_params()
321 for (i = 0; i < dev->caps.num_ports; i++) { in mlx4_check_port_params()
322 if (!(port_type[i] & dev->caps.supported_type[i+1])) { in mlx4_check_port_params()
335 for (i = 1; i <= dev->caps.num_ports; ++i) in mlx4_set_port_mask()
336 dev->caps.port_mask[i] = dev->caps.port_type[i]; in mlx4_set_port_mask()
348 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { in mlx4_query_func()
364 struct mlx4_caps *dev_cap = &dev->caps; in mlx4_enable_cqe_eqe_stride()
400 dev->caps.vl_cap[port] = port_cap->max_vl; in _mlx4_dev_port()
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| D | pd.c | 122 return mlx4_bitmap_init(&priv->pd_bitmap, dev->caps.num_pds, in mlx4_init_pd_table()
124 dev->caps.reserved_pds, 0); in mlx4_init_pd_table()
137 (1 << 16) - 1, dev->caps.reserved_xrcds + 1, 0); in mlx4_init_xrcd_table()
156 dev->caps.uar_page_size); in mlx4_uar_alloc()
223 bf->buf_size = dev->caps.bf_reg_size / 2; in mlx4_bf_alloc()
224 bf->reg = uar->bf_map + idx * dev->caps.bf_reg_size; in mlx4_bf_alloc()
225 if (uar->free_bf_bmap == (1 << dev->caps.bf_regs_per_page) - 1) in mlx4_bf_alloc()
255 idx = (bf->reg - bf->uar->bf_map) / dev->caps.bf_reg_size; in mlx4_bf_free()
277 mlx4_dbg(dev, "Effective reserved_uars=%d", dev->caps.reserved_uars); in mlx4_init_uar_table()
279 if (dev->caps.num_uars <= num_reserved_uar) { in mlx4_init_uar_table()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_dwb.c | 47 static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb1_get_caps() argument
49 if (caps) { in dwb1_get_caps()
50 caps->adapter_id = 0; /* we only support 1 adapter currently */ in dwb1_get_caps()
51 caps->hw_version = DCN_VERSION_1_0; in dwb1_get_caps()
52 caps->num_pipes = 2; in dwb1_get_caps()
53 memset(&caps->reserved, 0, sizeof(caps->reserved)); in dwb1_get_caps()
54 memset(&caps->reserved2, 0, sizeof(caps->reserved2)); in dwb1_get_caps()
55 caps->sw_version = dwb_ver_1_0; in dwb1_get_caps()
56 caps->caps.support_dwb = true; in dwb1_get_caps()
57 caps->caps.support_ogam = false; in dwb1_get_caps()
[all …]
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| /drivers/net/ethernet/mellanox/mlx5/core/steering/ |
| D | dr_domain.c | 9 ((dmn)->info.caps.dmn_type##_sw_owner || \
10 ((dmn)->info.caps.dmn_type##_sw_owner_v2 && \
11 (dmn)->info.caps.sw_format_ver <= MLX5_STEERING_FORMAT_CONNECTX_6DX))
18 dmn->cache.recalc_cs_ft = kcalloc(dmn->info.caps.num_vports, in dr_domain_init_cache()
31 for (i = 0; i < dmn->info.caps.num_vports; i++) { in dr_domain_uninit_cache()
129 vport_caps = &dmn->info.caps.vports_caps[vport_number]; in dr_domain_query_vport()
147 vport_caps->vhca_gvmi = dmn->info.caps.gvmi; in dr_domain_query_vport()
154 struct mlx5dr_esw_caps *esw_caps = &dmn->info.caps.esw_caps; in dr_domain_query_vports()
160 for (vport = 0; vport < dmn->info.caps.num_esw_ports - 1; vport++) { in dr_domain_query_vports()
167 wire_vport = &dmn->info.caps.vports_caps[vport]; in dr_domain_query_vports()
[all …]
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| D | dr_cmd.c | 67 struct mlx5dr_esw_caps *caps) in mlx5dr_cmd_query_esw_caps() argument
69 caps->drop_icm_address_rx = in mlx5dr_cmd_query_esw_caps()
72 caps->drop_icm_address_tx = in mlx5dr_cmd_query_esw_caps()
75 caps->uplink_icm_address_rx = in mlx5dr_cmd_query_esw_caps()
78 caps->uplink_icm_address_tx = in mlx5dr_cmd_query_esw_caps()
81 caps->sw_owner_v2 = MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, sw_owner_v2); in mlx5dr_cmd_query_esw_caps()
82 if (!caps->sw_owner_v2) in mlx5dr_cmd_query_esw_caps()
83 caps->sw_owner = MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, sw_owner); in mlx5dr_cmd_query_esw_caps()
89 struct mlx5dr_cmd_caps *caps) in mlx5dr_cmd_query_device() argument
91 caps->prio_tag_required = MLX5_CAP_GEN(mdev, prio_tag_required); in mlx5dr_cmd_query_device()
[all …]
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| /drivers/infiniband/hw/hns/ |
| D | hns_roce_main.c | 58 return gid_index * hr_dev->caps.num_ports + port; in hns_get_gid_index()
82 if (port >= hr_dev->caps.num_ports) in hns_roce_add_gid()
97 if (port >= hr_dev->caps.num_ports) in hns_roce_del_gid()
150 for (port = 0; port < hr_dev->caps.num_ports; port++) { in hns_roce_netdev_event()
167 for (i = 0; i < hr_dev->caps.num_ports; i++) { in hns_roce_setup_mtu_mac()
170 hr_dev->caps.max_mtu); in hns_roce_setup_mtu_mac()
188 props->fw_ver = hr_dev->caps.fw_ver; in hns_roce_query_device()
191 props->page_size_cap = hr_dev->caps.page_size_cap; in hns_roce_query_device()
195 props->max_qp = hr_dev->caps.num_qps; in hns_roce_query_device()
196 props->max_qp_wr = hr_dev->caps.max_wqes; in hns_roce_query_device()
[all …]
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| D | hns_roce_hw_v2.c | 1515 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); in hns_roce_query_fw_ver()
1565 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num, in hns_roce_query_pf_resource()
1568 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num, in hns_roce_query_pf_resource()
1571 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num, in hns_roce_query_pf_resource()
1574 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num, in hns_roce_query_pf_resource()
1578 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num, in hns_roce_query_pf_resource()
1581 hr_dev->caps.sccc_bt_num = roce_get_field(req_b->sccc_bt_idx_num, in hns_roce_query_pf_resource()
1603 hr_dev->caps.qpc_timer_bt_num = in hns_roce_query_pf_timer_resource()
1607 hr_dev->caps.cqc_timer_bt_num = in hns_roce_query_pf_timer_resource()
1719 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num; in hns_roce_v2_set_bt()
[all …]
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| /drivers/media/platform/qcom/venus/ |
| D | hfi_parser.c | 19 struct venus_caps *caps = core->caps, *cap; in init_codecs() local
26 cap = &caps[core->codecs_count++]; in init_codecs()
33 cap = &caps[core->codecs_count++]; in init_codecs()
40 static void for_each_codec(struct venus_caps *caps, unsigned int caps_num, in for_each_codec() argument
48 cap = &caps[i]; in for_each_codec()
80 for_each_codec(core->caps, ARRAY_SIZE(core->caps), in parse_alloc_mode()
111 for_each_codec(core->caps, ARRAY_SIZE(core->caps), codecs, domain, in parse_profile_level()
118 const struct hfi_capability *caps = data; in fill_caps() local
123 memcpy(&cap->caps[cap->num_caps], caps, num * sizeof(*caps)); in fill_caps()
130 struct hfi_capabilities *caps = data; in parse_caps() local
[all …]
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| D | hfi_parser.h | 19 struct venus_caps *caps; in get_cap() local
22 caps = venus_caps_by_codec(core, inst->hfi_codec, inst->session_type); in get_cap()
23 if (!caps) in get_cap()
26 for (i = 0; i < caps->num_caps; i++) { in get_cap()
27 if (caps->caps[i].capability_type == type) { in get_cap()
28 cap = &caps->caps[i]; in get_cap()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_dwb.c | 46 static bool dwb3_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb3_get_caps() argument
48 if (caps) { in dwb3_get_caps()
49 caps->adapter_id = 0; /* we only support 1 adapter currently */ in dwb3_get_caps()
50 caps->hw_version = DCN_VERSION_3_0; in dwb3_get_caps()
51 caps->num_pipes = 2; in dwb3_get_caps()
52 memset(&caps->reserved, 0, sizeof(caps->reserved)); in dwb3_get_caps()
53 memset(&caps->reserved2, 0, sizeof(caps->reserved2)); in dwb3_get_caps()
54 caps->sw_version = dwb_ver_2_0; in dwb3_get_caps()
55 caps->caps.support_dwb = true; in dwb3_get_caps()
56 caps->caps.support_ogam = true; in dwb3_get_caps()
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| /drivers/infiniband/hw/vmw_pvrdma/ |
| D | pvrdma_verbs.c | 74 props->fw_ver = dev->dsr->caps.fw_ver; in pvrdma_query_device()
75 props->sys_image_guid = dev->dsr->caps.sys_image_guid; in pvrdma_query_device()
76 props->max_mr_size = dev->dsr->caps.max_mr_size; in pvrdma_query_device()
77 props->page_size_cap = dev->dsr->caps.page_size_cap; in pvrdma_query_device()
78 props->vendor_id = dev->dsr->caps.vendor_id; in pvrdma_query_device()
80 props->hw_ver = dev->dsr->caps.hw_ver; in pvrdma_query_device()
81 props->max_qp = dev->dsr->caps.max_qp; in pvrdma_query_device()
82 props->max_qp_wr = dev->dsr->caps.max_qp_wr; in pvrdma_query_device()
83 props->device_cap_flags = dev->dsr->caps.device_cap_flags; in pvrdma_query_device()
84 props->max_send_sge = dev->dsr->caps.max_sge; in pvrdma_query_device()
[all …]
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| /drivers/gpu/drm/arm/display/komeda/ |
| D | komeda_format_caps.c | 16 const struct komeda_format_caps *caps; in komeda_get_format_caps() local
22 caps = &table->format_caps[id]; in komeda_get_format_caps()
24 if (fourcc != caps->fourcc) in komeda_get_format_caps()
27 if ((modifier == 0ULL) && (caps->supported_afbc_layouts == 0)) in komeda_get_format_caps()
28 return caps; in komeda_get_format_caps()
30 if (has_bits(afbc_features, caps->supported_afbc_features) && in komeda_get_format_caps()
31 has_bit(afbc_layout, caps->supported_afbc_layouts)) in komeda_get_format_caps()
32 return caps; in komeda_get_format_caps()
99 const struct komeda_format_caps *caps; in komeda_format_mod_supported() local
101 caps = komeda_get_format_caps(table, fourcc, modifier); in komeda_format_mod_supported()
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| /drivers/vfio/pci/ |
| D | vfio_pci_zdev.c | 28 struct vfio_info_cap *caps) in zpci_base_cap() argument
42 return vfio_info_add_capability(caps, &cap.header, sizeof(cap)); in zpci_base_cap()
49 struct vfio_info_cap *caps) in zpci_group_cap() argument
63 return vfio_info_add_capability(caps, &cap.header, sizeof(cap)); in zpci_group_cap()
70 struct vfio_info_cap *caps) in zpci_util_cap() argument
85 ret = vfio_info_add_capability(caps, &cap->header, cap_size); in zpci_util_cap()
96 struct vfio_info_cap *caps) in zpci_pfip_cap() argument
111 ret = vfio_info_add_capability(caps, &cap->header, cap_size); in zpci_pfip_cap()
122 struct vfio_info_cap *caps) in vfio_pci_info_zdev_add_caps() argument
130 ret = zpci_base_cap(zdev, vdev, caps); in vfio_pci_info_zdev_add_caps()
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| /drivers/mtd/nand/raw/ |
| D | mtk_ecc.c | 57 const struct mtk_ecc_caps *caps; member
139 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) in mtk_ecc_irq()
142 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); in mtk_ecc_irq()
148 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); in mtk_ecc_irq()
155 enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA]) in mtk_ecc_irq()
171 for (i = 0; i < ecc->caps->num_ecc_strength; i++) { in mtk_ecc_config()
172 if (ecc->caps->ecc_strength[i] == config->strength) in mtk_ecc_config()
176 if (i == ecc->caps->num_ecc_strength) { in mtk_ecc_config()
188 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); in mtk_ecc_config()
199 config->strength * ecc->caps->parity_bits; in mtk_ecc_config()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dwb.c | 50 static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb2_get_caps() argument
53 if (caps) { in dwb2_get_caps()
54 caps->adapter_id = 0; /* we only support 1 adapter currently */ in dwb2_get_caps()
55 caps->hw_version = DCN_VERSION_2_0; in dwb2_get_caps()
56 caps->num_pipes = 1; in dwb2_get_caps()
57 memset(&caps->reserved, 0, sizeof(caps->reserved)); in dwb2_get_caps()
58 memset(&caps->reserved2, 0, sizeof(caps->reserved2)); in dwb2_get_caps()
59 caps->sw_version = dwb_ver_1_0; in dwb2_get_caps()
60 caps->caps.support_dwb = true; in dwb2_get_caps()
61 caps->caps.support_ogam = false; in dwb2_get_caps()
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| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | capsgv100.c | 34 struct gv100_disp_caps *caps = gv100_disp_caps(object); in gv100_disp_caps_map() local
35 struct nvkm_device *device = caps->disp->base.engine.subdev.device; in gv100_disp_caps_map()
51 struct gv100_disp_caps *caps; in gv100_disp_caps_new() local
53 if (!(caps = kzalloc(sizeof(*caps), GFP_KERNEL))) in gv100_disp_caps_new()
55 *pobject = &caps->object; in gv100_disp_caps_new()
57 nvkm_object_ctor(&gv100_disp_caps, oclass, &caps->object); in gv100_disp_caps_new()
58 caps->disp = disp; in gv100_disp_caps_new()
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| /drivers/cpufreq/ |
| D | cppc_cpufreq.c | 103 struct cppc_perf_caps *caps = &cpu->perf_caps; in cppc_cpufreq_perf_to_khz() local
106 if (caps->lowest_freq && caps->nominal_freq) { in cppc_cpufreq_perf_to_khz()
107 if (perf >= caps->nominal_perf) { in cppc_cpufreq_perf_to_khz()
108 mul = caps->nominal_freq; in cppc_cpufreq_perf_to_khz()
109 div = caps->nominal_perf; in cppc_cpufreq_perf_to_khz()
111 mul = caps->nominal_freq - caps->lowest_freq; in cppc_cpufreq_perf_to_khz()
112 div = caps->nominal_perf - caps->lowest_perf; in cppc_cpufreq_perf_to_khz()
118 div = caps->highest_perf; in cppc_cpufreq_perf_to_khz()
127 struct cppc_perf_caps *caps = &cpu->perf_caps; in cppc_cpufreq_khz_to_perf() local
130 if (caps->lowest_freq && caps->nominal_freq) { in cppc_cpufreq_khz_to_perf()
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| /drivers/mmc/core/ |
| D | host.c | 241 host->caps |= MMC_CAP_8_BIT_DATA; in mmc_of_parse()
244 host->caps |= MMC_CAP_4_BIT_DATA; in mmc_of_parse()
272 host->caps |= MMC_CAP_NONREMOVABLE; in mmc_of_parse()
282 host->caps |= MMC_CAP_NEEDS_POLL; in mmc_of_parse()
307 host->caps |= MMC_CAP_SD_HIGHSPEED; in mmc_of_parse()
309 host->caps |= MMC_CAP_MMC_HIGHSPEED; in mmc_of_parse()
311 host->caps |= MMC_CAP_UHS_SDR12; in mmc_of_parse()
313 host->caps |= MMC_CAP_UHS_SDR25; in mmc_of_parse()
315 host->caps |= MMC_CAP_UHS_SDR50; in mmc_of_parse()
317 host->caps |= MMC_CAP_UHS_SDR104; in mmc_of_parse()
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| /drivers/net/ethernet/sfc/ |
| D | mcdi_port_common.c | 357 u32 mcdi_fec_caps_to_ethtool(u32 caps, bool is_25g) in mcdi_fec_caps_to_ethtool() argument
359 bool rs = caps & (1 << MC_CMD_PHY_CAP_RS_FEC_LBN), in mcdi_fec_caps_to_ethtool()
360 rs_req = caps & (1 << MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN), in mcdi_fec_caps_to_ethtool()
361 baser = is_25g ? caps & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_LBN) in mcdi_fec_caps_to_ethtool()
362 : caps & (1 << MC_CMD_PHY_CAP_BASER_FEC_LBN), in mcdi_fec_caps_to_ethtool()
363 baser_req = is_25g ? caps & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN) in mcdi_fec_caps_to_ethtool()
364 : caps & (1 << MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN); in mcdi_fec_caps_to_ethtool()
430 u32 caps; in efx_mcdi_phy_probe() local
462 caps = MCDI_DWORD(outbuf, GET_LINK_OUT_CAP); in efx_mcdi_phy_probe()
463 if (caps & (1 << MC_CMD_PHY_CAP_AN_LBN)) in efx_mcdi_phy_probe()
[all …]
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| /drivers/net/ethernet/marvell/prestera/ |
| D | prestera_ethtool.c | 315 if (port->caps.type < PRESTERA_PORT_TYPE_MAX) in prestera_port_type_get()
316 return port_types[port->caps.type].eth_type; in prestera_port_type_get()
336 if (type == port->caps.type) in prestera_port_type_set()
338 if (type != port->caps.type && ecmd->base.autoneg == AUTONEG_ENABLE) in prestera_port_type_set()
345 port->caps.supp_link_modes) && in prestera_port_type_set()
359 port->caps.type = type; in prestera_port_type_set()
425 port->caps.supp_link_modes) == 0) in prestera_port_supp_types_get()
507 if (port->caps.type == PRESTERA_PORT_TYPE_TP) { in prestera_ethtool_get_link_ksettings()
512 port->caps.transceiver == PRESTERA_PORT_TCVR_COPPER)) in prestera_ethtool_get_link_ksettings()
518 port->caps.supp_link_modes, in prestera_ethtool_get_link_ksettings()
[all …]
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| /drivers/video/fbdev/ |
| D | amba-clcd.c | 138 u32 caps; in clcdfb_set_bitfields() local
141 if (fb->panel->caps && fb->board->caps) in clcdfb_set_bitfields()
142 caps = fb->panel->caps & fb->board->caps; in clcdfb_set_bitfields()
145 caps = fb->panel->cntl & CNTL_BGR ? in clcdfb_set_bitfields()
148 caps &= ~CLCD_CAP_444; in clcdfb_set_bitfields()
153 caps &= ~CLCD_CAP_888; in clcdfb_set_bitfields()
167 caps &= CLCD_CAP_5551; in clcdfb_set_bitfields()
168 if (!caps) { in clcdfb_set_bitfields()
183 if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) { in clcdfb_set_bitfields()
192 if (var->green.length == 4 && caps & CLCD_CAP_444) in clcdfb_set_bitfields()
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