1 /*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/acpi.h>
34 #include <linux/etherdevice.h>
35 #include <linux/interrupt.h>
36 #include <linux/iopoll.h>
37 #include <linux/kernel.h>
38 #include <linux/types.h>
39 #include <net/addrconf.h>
40 #include <rdma/ib_addr.h>
41 #include <rdma/ib_cache.h>
42 #include <rdma/ib_umem.h>
43 #include <rdma/uverbs_ioctl.h>
44
45 #include "hnae3.h"
46 #include "hns_roce_common.h"
47 #include "hns_roce_device.h"
48 #include "hns_roce_cmd.h"
49 #include "hns_roce_hem.h"
50 #include "hns_roce_hw_v2.h"
51
set_data_seg_v2(struct hns_roce_v2_wqe_data_seg * dseg,struct ib_sge * sg)52 static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
53 struct ib_sge *sg)
54 {
55 dseg->lkey = cpu_to_le32(sg->lkey);
56 dseg->addr = cpu_to_le64(sg->addr);
57 dseg->len = cpu_to_le32(sg->length);
58 }
59
60 /*
61 * mapped-value = 1 + real-value
62 * The hns wr opcode real value is start from 0, In order to distinguish between
63 * initialized and uninitialized map values, we plus 1 to the actual value when
64 * defining the mapping, so that the validity can be identified by checking the
65 * mapped value is greater than 0.
66 */
67 #define HR_OPC_MAP(ib_key, hr_key) \
68 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
69
70 static const u32 hns_roce_op_code[] = {
71 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE),
72 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM),
73 HR_OPC_MAP(SEND, SEND),
74 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM),
75 HR_OPC_MAP(RDMA_READ, RDMA_READ),
76 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP),
77 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD),
78 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV),
79 HR_OPC_MAP(LOCAL_INV, LOCAL_INV),
80 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP),
81 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
82 HR_OPC_MAP(REG_MR, FAST_REG_PMR),
83 };
84
to_hr_opcode(u32 ib_opcode)85 static u32 to_hr_opcode(u32 ib_opcode)
86 {
87 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
88 return HNS_ROCE_V2_WQE_OP_MASK;
89
90 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
91 HNS_ROCE_V2_WQE_OP_MASK;
92 }
93
set_frmr_seg(struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,const struct ib_reg_wr * wr)94 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
95 const struct ib_reg_wr *wr)
96 {
97 struct hns_roce_wqe_frmr_seg *fseg =
98 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
99 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
100 u64 pbl_ba;
101
102 /* use ib_access_flags */
103 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S,
104 wr->access & IB_ACCESS_MW_BIND ? 1 : 0);
105 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S,
106 wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
107 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RR_S,
108 wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0);
109 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RW_S,
110 wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
111 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_LW_S,
112 wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
113
114 /* Data structure reuse may lead to confusion */
115 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba;
116 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba));
117 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba));
118
119 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
120 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
121 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
122 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
123
124 fseg->pbl_size = cpu_to_le32(mr->npages);
125 roce_set_field(fseg->mode_buf_pg_sz,
126 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M,
127 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S,
128 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
129 roce_set_bit(fseg->mode_buf_pg_sz,
130 V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0);
131 }
132
set_atomic_seg(const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int valid_num_sge)133 static void set_atomic_seg(const struct ib_send_wr *wr,
134 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
135 unsigned int valid_num_sge)
136 {
137 struct hns_roce_v2_wqe_data_seg *dseg =
138 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
139 struct hns_roce_wqe_atomic_seg *aseg =
140 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg);
141
142 set_data_seg_v2(dseg, wr->sg_list);
143
144 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
145 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
146 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
147 } else {
148 aseg->fetchadd_swap_data =
149 cpu_to_le64(atomic_wr(wr)->compare_add);
150 aseg->cmp_data = 0;
151 }
152
153 roce_set_field(rc_sq_wqe->byte_16, V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
154 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
155 }
156
get_std_sge_num(struct hns_roce_qp * qp)157 static unsigned int get_std_sge_num(struct hns_roce_qp *qp)
158 {
159 if (qp->ibqp.qp_type == IB_QPT_GSI || qp->ibqp.qp_type == IB_QPT_UD)
160 return 0;
161
162 return HNS_ROCE_SGE_IN_WQE;
163 }
164
fill_ext_sge_inl_data(struct hns_roce_qp * qp,const struct ib_send_wr * wr,unsigned int * sge_idx,u32 msg_len)165 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp,
166 const struct ib_send_wr *wr,
167 unsigned int *sge_idx, u32 msg_len)
168 {
169 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev;
170 unsigned int left_len_in_pg;
171 unsigned int idx = *sge_idx;
172 unsigned int std_sge_num;
173 unsigned int i = 0;
174 unsigned int len;
175 void *addr;
176 void *dseg;
177
178 std_sge_num = get_std_sge_num(qp);
179 if (msg_len > (qp->sq.max_gs - std_sge_num) * HNS_ROCE_SGE_SIZE) {
180 ibdev_err(ibdev,
181 "no enough extended sge space for inline data.\n");
182 return -EINVAL;
183 }
184
185 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
186 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg;
187 len = wr->sg_list[0].length;
188 addr = (void *)(unsigned long)(wr->sg_list[0].addr);
189
190 /* When copying data to extended sge space, the left length in page may
191 * not long enough for current user's sge. So the data should be
192 * splited into several parts, one in the first page, and the others in
193 * the subsequent pages.
194 */
195 while (1) {
196 if (len <= left_len_in_pg) {
197 memcpy(dseg, addr, len);
198
199 idx += len / HNS_ROCE_SGE_SIZE;
200
201 i++;
202 if (i >= wr->num_sge)
203 break;
204
205 left_len_in_pg -= len;
206 len = wr->sg_list[i].length;
207 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
208 dseg += len;
209 } else {
210 memcpy(dseg, addr, left_len_in_pg);
211
212 len -= left_len_in_pg;
213 addr += left_len_in_pg;
214 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE;
215 dseg = hns_roce_get_extend_sge(qp,
216 idx & (qp->sge.sge_cnt - 1));
217 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT;
218 }
219 }
220
221 *sge_idx = idx;
222
223 return 0;
224 }
225
set_extend_sge(struct hns_roce_qp * qp,struct ib_sge * sge,unsigned int * sge_ind,unsigned int cnt)226 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge,
227 unsigned int *sge_ind, unsigned int cnt)
228 {
229 struct hns_roce_v2_wqe_data_seg *dseg;
230 unsigned int idx = *sge_ind;
231
232 while (cnt > 0) {
233 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
234 if (likely(sge->length)) {
235 set_data_seg_v2(dseg, sge);
236 idx++;
237 cnt--;
238 }
239 sge++;
240 }
241
242 *sge_ind = idx;
243 }
244
check_inl_data_len(struct hns_roce_qp * qp,unsigned int len)245 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len)
246 {
247 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
248 int mtu = ib_mtu_enum_to_int(qp->path_mtu);
249
250 if (mtu < 0 || len > qp->max_inline_data || len > mtu) {
251 ibdev_err(&hr_dev->ib_dev,
252 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n",
253 len, qp->max_inline_data, mtu);
254 return false;
255 }
256
257 return true;
258 }
259
set_rc_inl(struct hns_roce_qp * qp,const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int * sge_idx)260 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
261 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
262 unsigned int *sge_idx)
263 {
264 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
265 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len);
266 struct ib_device *ibdev = &hr_dev->ib_dev;
267 unsigned int curr_idx = *sge_idx;
268 void *dseg = rc_sq_wqe;
269 unsigned int i;
270 int ret;
271
272 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) {
273 ibdev_err(ibdev, "invalid inline parameters!\n");
274 return -EINVAL;
275 }
276
277 if (!check_inl_data_len(qp, msg_len))
278 return -EINVAL;
279
280 dseg += sizeof(struct hns_roce_v2_rc_send_wqe);
281
282 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S, 1);
283
284 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) {
285 roce_set_bit(rc_sq_wqe->byte_20,
286 V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S, 0);
287
288 for (i = 0; i < wr->num_sge; i++) {
289 memcpy(dseg, ((void *)wr->sg_list[i].addr),
290 wr->sg_list[i].length);
291 dseg += wr->sg_list[i].length;
292 }
293 } else {
294 roce_set_bit(rc_sq_wqe->byte_20,
295 V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S, 1);
296
297 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len);
298 if (ret)
299 return ret;
300
301 roce_set_field(rc_sq_wqe->byte_16,
302 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
303 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S,
304 curr_idx - *sge_idx);
305 }
306
307 *sge_idx = curr_idx;
308
309 return 0;
310 }
311
set_rwqe_data_seg(struct ib_qp * ibqp,const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int * sge_ind,unsigned int valid_num_sge)312 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
313 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
314 unsigned int *sge_ind,
315 unsigned int valid_num_sge)
316 {
317 struct hns_roce_v2_wqe_data_seg *dseg =
318 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
319 struct hns_roce_qp *qp = to_hr_qp(ibqp);
320 int j = 0;
321 int i;
322
323 roce_set_field(rc_sq_wqe->byte_20,
324 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
325 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
326 (*sge_ind) & (qp->sge.sge_cnt - 1));
327
328 if (wr->send_flags & IB_SEND_INLINE)
329 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind);
330
331 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) {
332 for (i = 0; i < wr->num_sge; i++) {
333 if (likely(wr->sg_list[i].length)) {
334 set_data_seg_v2(dseg, wr->sg_list + i);
335 dseg++;
336 }
337 }
338 } else {
339 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) {
340 if (likely(wr->sg_list[i].length)) {
341 set_data_seg_v2(dseg, wr->sg_list + i);
342 dseg++;
343 j++;
344 }
345 }
346
347 set_extend_sge(qp, wr->sg_list + i, sge_ind,
348 valid_num_sge - HNS_ROCE_SGE_IN_WQE);
349 }
350
351 roce_set_field(rc_sq_wqe->byte_16,
352 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
353 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
354
355 return 0;
356 }
357
check_send_valid(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)358 static int check_send_valid(struct hns_roce_dev *hr_dev,
359 struct hns_roce_qp *hr_qp)
360 {
361 struct ib_device *ibdev = &hr_dev->ib_dev;
362 struct ib_qp *ibqp = &hr_qp->ibqp;
363
364 if (unlikely(ibqp->qp_type != IB_QPT_RC &&
365 ibqp->qp_type != IB_QPT_GSI &&
366 ibqp->qp_type != IB_QPT_UD)) {
367 ibdev_err(ibdev, "Not supported QP(0x%x)type!\n",
368 ibqp->qp_type);
369 return -EOPNOTSUPP;
370 } else if (unlikely(hr_qp->state == IB_QPS_RESET ||
371 hr_qp->state == IB_QPS_INIT ||
372 hr_qp->state == IB_QPS_RTR)) {
373 ibdev_err(ibdev, "failed to post WQE, QP state %hhu!\n",
374 hr_qp->state);
375 return -EINVAL;
376 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) {
377 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n",
378 hr_dev->state);
379 return -EIO;
380 }
381
382 return 0;
383 }
384
calc_wr_sge_num(const struct ib_send_wr * wr,unsigned int * sge_len)385 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr,
386 unsigned int *sge_len)
387 {
388 unsigned int valid_num = 0;
389 unsigned int len = 0;
390 int i;
391
392 for (i = 0; i < wr->num_sge; i++) {
393 if (likely(wr->sg_list[i].length)) {
394 len += wr->sg_list[i].length;
395 valid_num++;
396 }
397 }
398
399 *sge_len = len;
400 return valid_num;
401 }
402
get_immtdata(const struct ib_send_wr * wr)403 static __le32 get_immtdata(const struct ib_send_wr *wr)
404 {
405 switch (wr->opcode) {
406 case IB_WR_SEND_WITH_IMM:
407 case IB_WR_RDMA_WRITE_WITH_IMM:
408 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
409 default:
410 return 0;
411 }
412 }
413
set_ud_opcode(struct hns_roce_v2_ud_send_wqe * ud_sq_wqe,const struct ib_send_wr * wr)414 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
415 const struct ib_send_wr *wr)
416 {
417 u32 ib_op = wr->opcode;
418
419 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM)
420 return -EINVAL;
421
422 ud_sq_wqe->immtdata = get_immtdata(wr);
423
424 roce_set_field(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OPCODE_M,
425 V2_UD_SEND_WQE_BYTE_4_OPCODE_S, to_hr_opcode(ib_op));
426
427 return 0;
428 }
429
set_ud_wqe(struct hns_roce_qp * qp,const struct ib_send_wr * wr,void * wqe,unsigned int * sge_idx,unsigned int owner_bit)430 static inline int set_ud_wqe(struct hns_roce_qp *qp,
431 const struct ib_send_wr *wr,
432 void *wqe, unsigned int *sge_idx,
433 unsigned int owner_bit)
434 {
435 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
436 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
437 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
438 unsigned int curr_idx = *sge_idx;
439 int valid_num_sge;
440 u32 msg_len = 0;
441 int ret;
442
443 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
444 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe));
445
446 ret = set_ud_opcode(ud_sq_wqe, wr);
447 if (WARN_ON(ret))
448 return ret;
449
450 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M,
451 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]);
452 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M,
453 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]);
454 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M,
455 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]);
456 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M,
457 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]);
458 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_4_M,
459 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S, ah->av.mac[4]);
460 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_5_M,
461 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S, ah->av.mac[5]);
462
463 ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
464
465 /* Set sig attr */
466 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_CQE_S,
467 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
468
469 /* Set se attr */
470 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_SE_S,
471 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
472
473 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OWNER_S,
474 owner_bit);
475
476 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_PD_M,
477 V2_UD_SEND_WQE_BYTE_16_PD_S, to_hr_pd(qp->ibqp.pd)->pdn);
478
479 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M,
480 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
481
482 roce_set_field(ud_sq_wqe->byte_20,
483 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
484 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
485 curr_idx & (qp->sge.sge_cnt - 1));
486
487 roce_set_field(ud_sq_wqe->byte_24, V2_UD_SEND_WQE_BYTE_24_UDPSPN_M,
488 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, ah->av.udp_sport);
489 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
490 qp->qkey : ud_wr(wr)->remote_qkey);
491 roce_set_field(ud_sq_wqe->byte_32, V2_UD_SEND_WQE_BYTE_32_DQPN_M,
492 V2_UD_SEND_WQE_BYTE_32_DQPN_S, ud_wr(wr)->remote_qpn);
493
494 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
495 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit);
496 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
497 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass);
498 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
499 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel);
500 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M,
501 V2_UD_SEND_WQE_BYTE_40_SL_S, ah->av.sl);
502 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_PORTN_M,
503 V2_UD_SEND_WQE_BYTE_40_PORTN_S, qp->port);
504
505 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M,
506 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S, ah->av.gid_index);
507
508 if (hr_dev->pci_dev->revision <= PCI_REVISION_ID_HIP08) {
509 roce_set_bit(ud_sq_wqe->byte_40,
510 V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S,
511 ah->av.vlan_en);
512 roce_set_field(ud_sq_wqe->byte_36,
513 V2_UD_SEND_WQE_BYTE_36_VLAN_M,
514 V2_UD_SEND_WQE_BYTE_36_VLAN_S, ah->av.vlan_id);
515 }
516
517 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN_V2);
518
519 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge);
520
521 *sge_idx = curr_idx;
522
523 return 0;
524 }
525
set_rc_opcode(struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,const struct ib_send_wr * wr)526 static int set_rc_opcode(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
527 const struct ib_send_wr *wr)
528 {
529 u32 ib_op = wr->opcode;
530
531 rc_sq_wqe->immtdata = get_immtdata(wr);
532
533 switch (ib_op) {
534 case IB_WR_RDMA_READ:
535 case IB_WR_RDMA_WRITE:
536 case IB_WR_RDMA_WRITE_WITH_IMM:
537 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
538 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
539 break;
540 case IB_WR_SEND:
541 case IB_WR_SEND_WITH_IMM:
542 break;
543 case IB_WR_ATOMIC_CMP_AND_SWP:
544 case IB_WR_ATOMIC_FETCH_AND_ADD:
545 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
546 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
547 break;
548 case IB_WR_REG_MR:
549 set_frmr_seg(rc_sq_wqe, reg_wr(wr));
550 break;
551 case IB_WR_LOCAL_INV:
552 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1);
553 fallthrough;
554 case IB_WR_SEND_WITH_INV:
555 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
556 break;
557 default:
558 return -EINVAL;
559 }
560
561 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
562 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, to_hr_opcode(ib_op));
563
564 return 0;
565 }
set_rc_wqe(struct hns_roce_qp * qp,const struct ib_send_wr * wr,void * wqe,unsigned int * sge_idx,unsigned int owner_bit)566 static inline int set_rc_wqe(struct hns_roce_qp *qp,
567 const struct ib_send_wr *wr,
568 void *wqe, unsigned int *sge_idx,
569 unsigned int owner_bit)
570 {
571 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
572 unsigned int curr_idx = *sge_idx;
573 unsigned int valid_num_sge;
574 u32 msg_len = 0;
575 int ret;
576
577 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
578 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
579
580 rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
581
582 ret = set_rc_opcode(rc_sq_wqe, wr);
583 if (WARN_ON(ret))
584 return ret;
585
586 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S,
587 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
588
589 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S,
590 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
591
592 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S,
593 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
594
595 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S,
596 owner_bit);
597
598 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
599 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
600 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge);
601 else if (wr->opcode != IB_WR_REG_MR)
602 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
603 &curr_idx, valid_num_sge);
604
605 *sge_idx = curr_idx;
606
607 return ret;
608 }
609
update_sq_db(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp)610 static inline void update_sq_db(struct hns_roce_dev *hr_dev,
611 struct hns_roce_qp *qp)
612 {
613 /*
614 * Hip08 hardware cannot flush the WQEs in SQ if the QP state
615 * gets into errored mode. Hence, as a workaround to this
616 * hardware limitation, driver needs to assist in flushing. But
617 * the flushing operation uses mailbox to convey the QP state to
618 * the hardware and which can sleep due to the mutex protection
619 * around the mailbox calls. Hence, use the deferred flush for
620 * now.
621 */
622 if (qp->state == IB_QPS_ERR) {
623 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag))
624 init_flush_work(hr_dev, qp);
625 } else {
626 struct hns_roce_v2_db sq_db = {};
627
628 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M,
629 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn);
630 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M,
631 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB);
632 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M,
633 V2_DB_PARAMETER_IDX_S, qp->sq.head);
634 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M,
635 V2_DB_PARAMETER_SL_S, qp->sl);
636
637 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg_l);
638 }
639 }
640
hns_roce_v2_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)641 static int hns_roce_v2_post_send(struct ib_qp *ibqp,
642 const struct ib_send_wr *wr,
643 const struct ib_send_wr **bad_wr)
644 {
645 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
646 struct ib_device *ibdev = &hr_dev->ib_dev;
647 struct hns_roce_qp *qp = to_hr_qp(ibqp);
648 unsigned long flags = 0;
649 unsigned int owner_bit;
650 unsigned int sge_idx;
651 unsigned int wqe_idx;
652 void *wqe = NULL;
653 int nreq;
654 int ret;
655
656 spin_lock_irqsave(&qp->sq.lock, flags);
657
658 ret = check_send_valid(hr_dev, qp);
659 if (unlikely(ret)) {
660 *bad_wr = wr;
661 nreq = 0;
662 goto out;
663 }
664
665 sge_idx = qp->next_sge;
666
667 for (nreq = 0; wr; ++nreq, wr = wr->next) {
668 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
669 ret = -ENOMEM;
670 *bad_wr = wr;
671 goto out;
672 }
673
674 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
675
676 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
677 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n",
678 wr->num_sge, qp->sq.max_gs);
679 ret = -EINVAL;
680 *bad_wr = wr;
681 goto out;
682 }
683
684 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
685 qp->sq.wrid[wqe_idx] = wr->wr_id;
686 owner_bit =
687 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
688
689 /* Corresponding to the QP type, wqe process separately */
690 if (ibqp->qp_type == IB_QPT_GSI)
691 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
692 else if (ibqp->qp_type == IB_QPT_RC)
693 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
694
695 if (unlikely(ret)) {
696 *bad_wr = wr;
697 goto out;
698 }
699 }
700
701 out:
702 if (likely(nreq)) {
703 qp->sq.head += nreq;
704 qp->next_sge = sge_idx;
705 /* Memory barrier */
706 wmb();
707 update_sq_db(hr_dev, qp);
708 }
709
710 spin_unlock_irqrestore(&qp->sq.lock, flags);
711
712 return ret;
713 }
714
check_recv_valid(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)715 static int check_recv_valid(struct hns_roce_dev *hr_dev,
716 struct hns_roce_qp *hr_qp)
717 {
718 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
719 return -EIO;
720 else if (hr_qp->state == IB_QPS_RESET)
721 return -EINVAL;
722
723 return 0;
724 }
725
hns_roce_v2_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)726 static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
727 const struct ib_recv_wr *wr,
728 const struct ib_recv_wr **bad_wr)
729 {
730 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
731 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
732 struct ib_device *ibdev = &hr_dev->ib_dev;
733 struct hns_roce_v2_wqe_data_seg *dseg;
734 struct hns_roce_rinl_sge *sge_list;
735 unsigned long flags;
736 void *wqe = NULL;
737 u32 wqe_idx;
738 int nreq;
739 int ret;
740 int i;
741
742 spin_lock_irqsave(&hr_qp->rq.lock, flags);
743
744 ret = check_recv_valid(hr_dev, hr_qp);
745 if (unlikely(ret)) {
746 *bad_wr = wr;
747 nreq = 0;
748 goto out;
749 }
750
751 for (nreq = 0; wr; ++nreq, wr = wr->next) {
752 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq,
753 hr_qp->ibqp.recv_cq))) {
754 ret = -ENOMEM;
755 *bad_wr = wr;
756 goto out;
757 }
758
759 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
760
761 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
762 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n",
763 wr->num_sge, hr_qp->rq.max_gs);
764 ret = -EINVAL;
765 *bad_wr = wr;
766 goto out;
767 }
768
769 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
770 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
771 for (i = 0; i < wr->num_sge; i++) {
772 if (!wr->sg_list[i].length)
773 continue;
774 set_data_seg_v2(dseg, wr->sg_list + i);
775 dseg++;
776 }
777
778 if (wr->num_sge < hr_qp->rq.max_gs) {
779 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
780 dseg->addr = 0;
781 }
782
783 /* rq support inline data */
784 if (hr_qp->rq_inl_buf.wqe_cnt) {
785 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list;
786 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt =
787 (u32)wr->num_sge;
788 for (i = 0; i < wr->num_sge; i++) {
789 sge_list[i].addr =
790 (void *)(u64)wr->sg_list[i].addr;
791 sge_list[i].len = wr->sg_list[i].length;
792 }
793 }
794
795 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
796 }
797
798 out:
799 if (likely(nreq)) {
800 hr_qp->rq.head += nreq;
801 /* Memory barrier */
802 wmb();
803
804 /*
805 * Hip08 hardware cannot flush the WQEs in RQ if the QP state
806 * gets into errored mode. Hence, as a workaround to this
807 * hardware limitation, driver needs to assist in flushing. But
808 * the flushing operation uses mailbox to convey the QP state to
809 * the hardware and which can sleep due to the mutex protection
810 * around the mailbox calls. Hence, use the deferred flush for
811 * now.
812 */
813 if (hr_qp->state == IB_QPS_ERR) {
814 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG,
815 &hr_qp->flush_flag))
816 init_flush_work(hr_dev, hr_qp);
817 } else {
818 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff;
819 }
820 }
821 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
822
823 return ret;
824 }
825
get_srq_wqe(struct hns_roce_srq * srq,int n)826 static void *get_srq_wqe(struct hns_roce_srq *srq, int n)
827 {
828 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
829 }
830
get_idx_buf(struct hns_roce_idx_que * idx_que,int n)831 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, int n)
832 {
833 return hns_roce_buf_offset(idx_que->mtr.kmem,
834 n << idx_que->entry_shift);
835 }
836
hns_roce_free_srq_wqe(struct hns_roce_srq * srq,int wqe_index)837 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, int wqe_index)
838 {
839 /* always called with interrupts disabled. */
840 spin_lock(&srq->lock);
841
842 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
843 srq->tail++;
844
845 spin_unlock(&srq->lock);
846 }
847
find_empty_entry(struct hns_roce_idx_que * idx_que,unsigned long size)848 static int find_empty_entry(struct hns_roce_idx_que *idx_que,
849 unsigned long size)
850 {
851 int wqe_idx;
852
853 if (unlikely(bitmap_full(idx_que->bitmap, size)))
854 return -ENOSPC;
855
856 wqe_idx = find_first_zero_bit(idx_que->bitmap, size);
857
858 bitmap_set(idx_que->bitmap, wqe_idx, 1);
859
860 return wqe_idx;
861 }
862
hns_roce_v2_post_srq_recv(struct ib_srq * ibsrq,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)863 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
864 const struct ib_recv_wr *wr,
865 const struct ib_recv_wr **bad_wr)
866 {
867 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
868 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
869 struct hns_roce_v2_wqe_data_seg *dseg;
870 struct hns_roce_v2_db srq_db;
871 unsigned long flags;
872 __le32 *srq_idx;
873 int ret = 0;
874 int wqe_idx;
875 void *wqe;
876 int nreq;
877 int ind;
878 int i;
879
880 spin_lock_irqsave(&srq->lock, flags);
881
882 ind = srq->head & (srq->wqe_cnt - 1);
883
884 for (nreq = 0; wr; ++nreq, wr = wr->next) {
885 if (unlikely(wr->num_sge >= srq->max_gs)) {
886 ret = -EINVAL;
887 *bad_wr = wr;
888 break;
889 }
890
891 if (unlikely(srq->head == srq->tail)) {
892 ret = -ENOMEM;
893 *bad_wr = wr;
894 break;
895 }
896
897 wqe_idx = find_empty_entry(&srq->idx_que, srq->wqe_cnt);
898 if (unlikely(wqe_idx < 0)) {
899 ret = -ENOMEM;
900 *bad_wr = wr;
901 break;
902 }
903
904 wqe = get_srq_wqe(srq, wqe_idx);
905 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
906
907 for (i = 0; i < wr->num_sge; ++i) {
908 dseg[i].len = cpu_to_le32(wr->sg_list[i].length);
909 dseg[i].lkey = cpu_to_le32(wr->sg_list[i].lkey);
910 dseg[i].addr = cpu_to_le64(wr->sg_list[i].addr);
911 }
912
913 if (wr->num_sge < srq->max_gs) {
914 dseg[i].len = 0;
915 dseg[i].lkey = cpu_to_le32(0x100);
916 dseg[i].addr = 0;
917 }
918
919 srq_idx = get_idx_buf(&srq->idx_que, ind);
920 *srq_idx = cpu_to_le32(wqe_idx);
921
922 srq->wrid[wqe_idx] = wr->wr_id;
923 ind = (ind + 1) & (srq->wqe_cnt - 1);
924 }
925
926 if (likely(nreq)) {
927 srq->head += nreq;
928
929 /*
930 * Make sure that descriptors are written before
931 * doorbell record.
932 */
933 wmb();
934
935 srq_db.byte_4 =
936 cpu_to_le32(HNS_ROCE_V2_SRQ_DB << V2_DB_BYTE_4_CMD_S |
937 (srq->srqn & V2_DB_BYTE_4_TAG_M));
938 srq_db.parameter =
939 cpu_to_le32(srq->head & V2_DB_PARAMETER_IDX_M);
940
941 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg_l);
942 }
943
944 spin_unlock_irqrestore(&srq->lock, flags);
945
946 return ret;
947 }
948
hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev * hr_dev,unsigned long instance_stage,unsigned long reset_stage)949 static int hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
950 unsigned long instance_stage,
951 unsigned long reset_stage)
952 {
953 /* When hardware reset has been completed once or more, we should stop
954 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
955 * function, we should exit with error. If now at HNAE3_INIT_CLIENT
956 * stage of soft reset process, we should exit with error, and then
957 * HNAE3_INIT_CLIENT related process can rollback the operation like
958 * notifing hardware to free resources, HNAE3_INIT_CLIENT related
959 * process will exit with error to notify NIC driver to reschedule soft
960 * reset process once again.
961 */
962 hr_dev->is_reset = true;
963 hr_dev->dis_db = true;
964
965 if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
966 instance_stage == HNS_ROCE_STATE_INIT)
967 return CMD_RST_PRC_EBUSY;
968
969 return CMD_RST_PRC_SUCCESS;
970 }
971
hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev * hr_dev,unsigned long instance_stage,unsigned long reset_stage)972 static int hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
973 unsigned long instance_stage,
974 unsigned long reset_stage)
975 {
976 #define HW_RESET_TIMEOUT_US 1000000
977 #define HW_RESET_SLEEP_US 1000
978
979 struct hns_roce_v2_priv *priv = hr_dev->priv;
980 struct hnae3_handle *handle = priv->handle;
981 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
982 unsigned long val;
983 int ret;
984
985 /* When hardware reset is detected, we should stop sending mailbox&cmq&
986 * doorbell to hardware. If now in .init_instance() function, we should
987 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
988 * process, we should exit with error, and then HNAE3_INIT_CLIENT
989 * related process can rollback the operation like notifing hardware to
990 * free resources, HNAE3_INIT_CLIENT related process will exit with
991 * error to notify NIC driver to reschedule soft reset process once
992 * again.
993 */
994 hr_dev->dis_db = true;
995
996 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val,
997 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US,
998 HW_RESET_TIMEOUT_US, false, handle);
999 if (!ret)
1000 hr_dev->is_reset = true;
1001
1002 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
1003 instance_stage == HNS_ROCE_STATE_INIT)
1004 return CMD_RST_PRC_EBUSY;
1005
1006 return CMD_RST_PRC_SUCCESS;
1007 }
1008
hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev * hr_dev)1009 static int hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
1010 {
1011 struct hns_roce_v2_priv *priv = hr_dev->priv;
1012 struct hnae3_handle *handle = priv->handle;
1013 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1014
1015 /* When software reset is detected at .init_instance() function, we
1016 * should stop sending mailbox&cmq&doorbell to hardware, and exit
1017 * with error.
1018 */
1019 hr_dev->dis_db = true;
1020 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
1021 hr_dev->is_reset = true;
1022
1023 return CMD_RST_PRC_EBUSY;
1024 }
1025
hns_roce_v2_rst_process_cmd(struct hns_roce_dev * hr_dev)1026 static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev)
1027 {
1028 struct hns_roce_v2_priv *priv = hr_dev->priv;
1029 struct hnae3_handle *handle = priv->handle;
1030 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1031 unsigned long instance_stage; /* the current instance stage */
1032 unsigned long reset_stage; /* the current reset stage */
1033 unsigned long reset_cnt;
1034 bool sw_resetting;
1035 bool hw_resetting;
1036
1037 if (hr_dev->is_reset)
1038 return CMD_RST_PRC_SUCCESS;
1039
1040 /* Get information about reset from NIC driver or RoCE driver itself,
1041 * the meaning of the following variables from NIC driver are described
1042 * as below:
1043 * reset_cnt -- The count value of completed hardware reset.
1044 * hw_resetting -- Whether hardware device is resetting now.
1045 * sw_resetting -- Whether NIC's software reset process is running now.
1046 */
1047 instance_stage = handle->rinfo.instance_state;
1048 reset_stage = handle->rinfo.reset_state;
1049 reset_cnt = ops->ae_dev_reset_cnt(handle);
1050 hw_resetting = ops->get_cmdq_stat(handle);
1051 sw_resetting = ops->ae_dev_resetting(handle);
1052
1053 if (reset_cnt != hr_dev->reset_cnt)
1054 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
1055 reset_stage);
1056 else if (hw_resetting)
1057 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
1058 reset_stage);
1059 else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
1060 return hns_roce_v2_cmd_sw_resetting(hr_dev);
1061
1062 return 0;
1063 }
1064
hns_roce_cmq_space(struct hns_roce_v2_cmq_ring * ring)1065 static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring)
1066 {
1067 int ntu = ring->next_to_use;
1068 int ntc = ring->next_to_clean;
1069 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
1070
1071 return ring->desc_num - used - 1;
1072 }
1073
hns_roce_alloc_cmq_desc(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * ring)1074 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
1075 struct hns_roce_v2_cmq_ring *ring)
1076 {
1077 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
1078
1079 ring->desc = kzalloc(size, GFP_KERNEL);
1080 if (!ring->desc)
1081 return -ENOMEM;
1082
1083 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
1084 DMA_BIDIRECTIONAL);
1085 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
1086 ring->desc_dma_addr = 0;
1087 kfree(ring->desc);
1088 ring->desc = NULL;
1089 return -ENOMEM;
1090 }
1091
1092 return 0;
1093 }
1094
hns_roce_free_cmq_desc(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * ring)1095 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
1096 struct hns_roce_v2_cmq_ring *ring)
1097 {
1098 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
1099 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
1100 DMA_BIDIRECTIONAL);
1101
1102 ring->desc_dma_addr = 0;
1103 kfree(ring->desc);
1104 }
1105
hns_roce_init_cmq_ring(struct hns_roce_dev * hr_dev,bool ring_type)1106 static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
1107 {
1108 struct hns_roce_v2_priv *priv = hr_dev->priv;
1109 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
1110 &priv->cmq.csq : &priv->cmq.crq;
1111
1112 ring->flag = ring_type;
1113 ring->next_to_clean = 0;
1114 ring->next_to_use = 0;
1115
1116 return hns_roce_alloc_cmq_desc(hr_dev, ring);
1117 }
1118
hns_roce_cmq_init_regs(struct hns_roce_dev * hr_dev,bool ring_type)1119 static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
1120 {
1121 struct hns_roce_v2_priv *priv = hr_dev->priv;
1122 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
1123 &priv->cmq.csq : &priv->cmq.crq;
1124 dma_addr_t dma = ring->desc_dma_addr;
1125
1126 if (ring_type == TYPE_CSQ) {
1127 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
1128 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
1129 upper_32_bits(dma));
1130 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
1131 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1132 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
1133 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
1134 } else {
1135 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
1136 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
1137 upper_32_bits(dma));
1138 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
1139 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1140 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
1141 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
1142 }
1143 }
1144
hns_roce_v2_cmq_init(struct hns_roce_dev * hr_dev)1145 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
1146 {
1147 struct hns_roce_v2_priv *priv = hr_dev->priv;
1148 int ret;
1149
1150 /* Setup the queue entries for command queue */
1151 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM;
1152 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM;
1153
1154 /* Setup the lock for command queue */
1155 spin_lock_init(&priv->cmq.csq.lock);
1156 spin_lock_init(&priv->cmq.crq.lock);
1157
1158 /* Setup Tx write back timeout */
1159 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
1160
1161 /* Init CSQ */
1162 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
1163 if (ret) {
1164 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret);
1165 return ret;
1166 }
1167
1168 /* Init CRQ */
1169 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
1170 if (ret) {
1171 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret);
1172 goto err_crq;
1173 }
1174
1175 /* Init CSQ REG */
1176 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
1177
1178 /* Init CRQ REG */
1179 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
1180
1181 return 0;
1182
1183 err_crq:
1184 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1185
1186 return ret;
1187 }
1188
hns_roce_v2_cmq_exit(struct hns_roce_dev * hr_dev)1189 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
1190 {
1191 struct hns_roce_v2_priv *priv = hr_dev->priv;
1192
1193 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1194 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
1195 }
1196
hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc * desc,enum hns_roce_opcode_type opcode,bool is_read)1197 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
1198 enum hns_roce_opcode_type opcode,
1199 bool is_read)
1200 {
1201 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
1202 desc->opcode = cpu_to_le16(opcode);
1203 desc->flag =
1204 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
1205 if (is_read)
1206 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
1207 else
1208 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1209 }
1210
hns_roce_cmq_csq_done(struct hns_roce_dev * hr_dev)1211 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
1212 {
1213 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
1214 struct hns_roce_v2_priv *priv = hr_dev->priv;
1215
1216 return head == priv->cmq.csq.next_to_use;
1217 }
1218
hns_roce_cmq_csq_clean(struct hns_roce_dev * hr_dev)1219 static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev)
1220 {
1221 struct hns_roce_v2_priv *priv = hr_dev->priv;
1222 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1223 struct hns_roce_cmq_desc *desc;
1224 u16 ntc = csq->next_to_clean;
1225 u32 head;
1226 int clean = 0;
1227
1228 desc = &csq->desc[ntc];
1229 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
1230 while (head != ntc) {
1231 memset(desc, 0, sizeof(*desc));
1232 ntc++;
1233 if (ntc == csq->desc_num)
1234 ntc = 0;
1235 desc = &csq->desc[ntc];
1236 clean++;
1237 }
1238 csq->next_to_clean = ntc;
1239
1240 return clean;
1241 }
1242
__hns_roce_cmq_send(struct hns_roce_dev * hr_dev,struct hns_roce_cmq_desc * desc,int num)1243 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1244 struct hns_roce_cmq_desc *desc, int num)
1245 {
1246 struct hns_roce_v2_priv *priv = hr_dev->priv;
1247 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1248 struct hns_roce_cmq_desc *desc_to_use;
1249 bool complete = false;
1250 u32 timeout = 0;
1251 int handle = 0;
1252 u16 desc_ret;
1253 int ret;
1254 int ntc;
1255
1256 spin_lock_bh(&csq->lock);
1257
1258 if (num > hns_roce_cmq_space(csq)) {
1259 spin_unlock_bh(&csq->lock);
1260 return -EBUSY;
1261 }
1262
1263 /*
1264 * Record the location of desc in the cmq for this time
1265 * which will be use for hardware to write back
1266 */
1267 ntc = csq->next_to_use;
1268
1269 while (handle < num) {
1270 desc_to_use = &csq->desc[csq->next_to_use];
1271 *desc_to_use = desc[handle];
1272 dev_dbg(hr_dev->dev, "set cmq desc:\n");
1273 csq->next_to_use++;
1274 if (csq->next_to_use == csq->desc_num)
1275 csq->next_to_use = 0;
1276 handle++;
1277 }
1278
1279 /* Write to hardware */
1280 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
1281
1282 /*
1283 * If the command is sync, wait for the firmware to write back,
1284 * if multi descriptors to be sent, use the first one to check
1285 */
1286 if (le16_to_cpu(desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
1287 do {
1288 if (hns_roce_cmq_csq_done(hr_dev))
1289 break;
1290 udelay(1);
1291 timeout++;
1292 } while (timeout < priv->cmq.tx_timeout);
1293 }
1294
1295 if (hns_roce_cmq_csq_done(hr_dev)) {
1296 complete = true;
1297 handle = 0;
1298 ret = 0;
1299 while (handle < num) {
1300 /* get the result of hardware write back */
1301 desc_to_use = &csq->desc[ntc];
1302 desc[handle] = *desc_to_use;
1303 dev_dbg(hr_dev->dev, "Get cmq desc:\n");
1304 desc_ret = le16_to_cpu(desc[handle].retval);
1305 if (unlikely(desc_ret != CMD_EXEC_SUCCESS))
1306 ret = -EIO;
1307 priv->cmq.last_status = desc_ret;
1308 ntc++;
1309 handle++;
1310 if (ntc == csq->desc_num)
1311 ntc = 0;
1312 }
1313 }
1314
1315 if (!complete)
1316 ret = -EAGAIN;
1317
1318 /* clean the command send queue */
1319 handle = hns_roce_cmq_csq_clean(hr_dev);
1320 if (handle != num)
1321 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n",
1322 handle, num);
1323
1324 spin_unlock_bh(&csq->lock);
1325
1326 return ret;
1327 }
1328
hns_roce_cmq_send(struct hns_roce_dev * hr_dev,struct hns_roce_cmq_desc * desc,int num)1329 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1330 struct hns_roce_cmq_desc *desc, int num)
1331 {
1332 int retval;
1333 int ret;
1334
1335 ret = hns_roce_v2_rst_process_cmd(hr_dev);
1336 if (ret == CMD_RST_PRC_SUCCESS)
1337 return 0;
1338 if (ret == CMD_RST_PRC_EBUSY)
1339 return -EBUSY;
1340
1341 ret = __hns_roce_cmq_send(hr_dev, desc, num);
1342 if (ret) {
1343 retval = hns_roce_v2_rst_process_cmd(hr_dev);
1344 if (retval == CMD_RST_PRC_SUCCESS)
1345 return 0;
1346 else if (retval == CMD_RST_PRC_EBUSY)
1347 return -EBUSY;
1348 }
1349
1350 return ret;
1351 }
1352
hns_roce_cmq_query_hw_info(struct hns_roce_dev * hr_dev)1353 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
1354 {
1355 struct hns_roce_query_version *resp;
1356 struct hns_roce_cmq_desc desc;
1357 int ret;
1358
1359 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1360 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1361 if (ret)
1362 return ret;
1363
1364 resp = (struct hns_roce_query_version *)desc.data;
1365 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
1366 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1367
1368 return 0;
1369 }
1370
hns_roce_func_clr_chk_rst(struct hns_roce_dev * hr_dev)1371 static bool hns_roce_func_clr_chk_rst(struct hns_roce_dev *hr_dev)
1372 {
1373 struct hns_roce_v2_priv *priv = hr_dev->priv;
1374 struct hnae3_handle *handle = priv->handle;
1375 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1376 unsigned long reset_cnt;
1377 bool sw_resetting;
1378 bool hw_resetting;
1379
1380 reset_cnt = ops->ae_dev_reset_cnt(handle);
1381 hw_resetting = ops->get_hw_reset_stat(handle);
1382 sw_resetting = ops->ae_dev_resetting(handle);
1383
1384 if (reset_cnt != hr_dev->reset_cnt || hw_resetting || sw_resetting)
1385 return true;
1386
1387 return false;
1388 }
1389
hns_roce_func_clr_rst_prc(struct hns_roce_dev * hr_dev,int retval,int flag)1390 static void hns_roce_func_clr_rst_prc(struct hns_roce_dev *hr_dev, int retval,
1391 int flag)
1392 {
1393 struct hns_roce_v2_priv *priv = hr_dev->priv;
1394 struct hnae3_handle *handle = priv->handle;
1395 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1396 unsigned long instance_stage;
1397 unsigned long reset_cnt;
1398 unsigned long end;
1399 bool sw_resetting;
1400 bool hw_resetting;
1401
1402 instance_stage = handle->rinfo.instance_state;
1403 reset_cnt = ops->ae_dev_reset_cnt(handle);
1404 hw_resetting = ops->get_hw_reset_stat(handle);
1405 sw_resetting = ops->ae_dev_resetting(handle);
1406
1407 if (reset_cnt != hr_dev->reset_cnt) {
1408 hr_dev->dis_db = true;
1409 hr_dev->is_reset = true;
1410 dev_info(hr_dev->dev, "Func clear success after reset.\n");
1411 } else if (hw_resetting) {
1412 hr_dev->dis_db = true;
1413
1414 dev_warn(hr_dev->dev,
1415 "Func clear is pending, device in resetting state.\n");
1416 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1417 while (end) {
1418 if (!ops->get_hw_reset_stat(handle)) {
1419 hr_dev->is_reset = true;
1420 dev_info(hr_dev->dev,
1421 "Func clear success after reset.\n");
1422 return;
1423 }
1424 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1425 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1426 }
1427
1428 dev_warn(hr_dev->dev, "Func clear failed.\n");
1429 } else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) {
1430 hr_dev->dis_db = true;
1431
1432 dev_warn(hr_dev->dev,
1433 "Func clear is pending, device in resetting state.\n");
1434 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1435 while (end) {
1436 if (ops->ae_dev_reset_cnt(handle) !=
1437 hr_dev->reset_cnt) {
1438 hr_dev->is_reset = true;
1439 dev_info(hr_dev->dev,
1440 "Func clear success after sw reset\n");
1441 return;
1442 }
1443 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1444 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1445 }
1446
1447 dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n");
1448 } else {
1449 if (retval && !flag)
1450 dev_warn(hr_dev->dev,
1451 "Func clear read failed, ret = %d.\n", retval);
1452
1453 dev_warn(hr_dev->dev, "Func clear failed.\n");
1454 }
1455 }
hns_roce_function_clear(struct hns_roce_dev * hr_dev)1456 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1457 {
1458 bool fclr_write_fail_flag = false;
1459 struct hns_roce_func_clear *resp;
1460 struct hns_roce_cmq_desc desc;
1461 unsigned long end;
1462 int ret = 0;
1463
1464 if (hns_roce_func_clr_chk_rst(hr_dev))
1465 goto out;
1466
1467 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1468 resp = (struct hns_roce_func_clear *)desc.data;
1469
1470 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1471 if (ret) {
1472 fclr_write_fail_flag = true;
1473 dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n",
1474 ret);
1475 goto out;
1476 }
1477
1478 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1479 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1480 while (end) {
1481 if (hns_roce_func_clr_chk_rst(hr_dev))
1482 goto out;
1483 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1484 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1485
1486 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1487 true);
1488
1489 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1490 if (ret)
1491 continue;
1492
1493 if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) {
1494 hr_dev->is_reset = true;
1495 return;
1496 }
1497 }
1498
1499 out:
1500 hns_roce_func_clr_rst_prc(hr_dev, ret, fclr_write_fail_flag);
1501 }
1502
hns_roce_query_fw_ver(struct hns_roce_dev * hr_dev)1503 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1504 {
1505 struct hns_roce_query_fw_info *resp;
1506 struct hns_roce_cmq_desc desc;
1507 int ret;
1508
1509 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1510 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1511 if (ret)
1512 return ret;
1513
1514 resp = (struct hns_roce_query_fw_info *)desc.data;
1515 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
1516
1517 return 0;
1518 }
1519
hns_roce_config_global_param(struct hns_roce_dev * hr_dev)1520 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1521 {
1522 struct hns_roce_cfg_global_param *req;
1523 struct hns_roce_cmq_desc desc;
1524
1525 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1526 false);
1527
1528 req = (struct hns_roce_cfg_global_param *)desc.data;
1529 memset(req, 0, sizeof(*req));
1530 roce_set_field(req->time_cfg_udp_port,
1531 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M,
1532 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8);
1533 roce_set_field(req->time_cfg_udp_port,
1534 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M,
1535 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7);
1536
1537 return hns_roce_cmq_send(hr_dev, &desc, 1);
1538 }
1539
hns_roce_query_pf_resource(struct hns_roce_dev * hr_dev)1540 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1541 {
1542 struct hns_roce_cmq_desc desc[2];
1543 struct hns_roce_pf_res_a *req_a;
1544 struct hns_roce_pf_res_b *req_b;
1545 int ret;
1546 int i;
1547
1548 for (i = 0; i < 2; i++) {
1549 hns_roce_cmq_setup_basic_desc(&desc[i],
1550 HNS_ROCE_OPC_QUERY_PF_RES, true);
1551
1552 if (i == 0)
1553 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1554 else
1555 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1556 }
1557
1558 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1559 if (ret)
1560 return ret;
1561
1562 req_a = (struct hns_roce_pf_res_a *)desc[0].data;
1563 req_b = (struct hns_roce_pf_res_b *)desc[1].data;
1564
1565 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num,
1566 PF_RES_DATA_1_PF_QPC_BT_NUM_M,
1567 PF_RES_DATA_1_PF_QPC_BT_NUM_S);
1568 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num,
1569 PF_RES_DATA_2_PF_SRQC_BT_NUM_M,
1570 PF_RES_DATA_2_PF_SRQC_BT_NUM_S);
1571 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num,
1572 PF_RES_DATA_3_PF_CQC_BT_NUM_M,
1573 PF_RES_DATA_3_PF_CQC_BT_NUM_S);
1574 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num,
1575 PF_RES_DATA_4_PF_MPT_BT_NUM_M,
1576 PF_RES_DATA_4_PF_MPT_BT_NUM_S);
1577
1578 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num,
1579 PF_RES_DATA_3_PF_SL_NUM_M,
1580 PF_RES_DATA_3_PF_SL_NUM_S);
1581 hr_dev->caps.sccc_bt_num = roce_get_field(req_b->sccc_bt_idx_num,
1582 PF_RES_DATA_4_PF_SCCC_BT_NUM_M,
1583 PF_RES_DATA_4_PF_SCCC_BT_NUM_S);
1584
1585 return 0;
1586 }
1587
hns_roce_query_pf_timer_resource(struct hns_roce_dev * hr_dev)1588 static int hns_roce_query_pf_timer_resource(struct hns_roce_dev *hr_dev)
1589 {
1590 struct hns_roce_pf_timer_res_a *req_a;
1591 struct hns_roce_cmq_desc desc;
1592 int ret;
1593
1594 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1595 true);
1596
1597 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1598 if (ret)
1599 return ret;
1600
1601 req_a = (struct hns_roce_pf_timer_res_a *)desc.data;
1602
1603 hr_dev->caps.qpc_timer_bt_num =
1604 roce_get_field(req_a->qpc_timer_bt_idx_num,
1605 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M,
1606 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S);
1607 hr_dev->caps.cqc_timer_bt_num =
1608 roce_get_field(req_a->cqc_timer_bt_idx_num,
1609 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M,
1610 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S);
1611
1612 return 0;
1613 }
1614
hns_roce_set_vf_switch_param(struct hns_roce_dev * hr_dev,int vf_id)1615 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, int vf_id)
1616 {
1617 struct hns_roce_cmq_desc desc;
1618 struct hns_roce_vf_switch *swt;
1619 int ret;
1620
1621 swt = (struct hns_roce_vf_switch *)desc.data;
1622 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
1623 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
1624 roce_set_field(swt->fun_id, VF_SWITCH_DATA_FUN_ID_VF_ID_M,
1625 VF_SWITCH_DATA_FUN_ID_VF_ID_S, vf_id);
1626 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1627 if (ret)
1628 return ret;
1629
1630 desc.flag =
1631 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
1632 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1633 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1);
1634 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0);
1635 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1);
1636
1637 return hns_roce_cmq_send(hr_dev, &desc, 1);
1638 }
1639
hns_roce_alloc_vf_resource(struct hns_roce_dev * hr_dev)1640 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1641 {
1642 struct hns_roce_cmq_desc desc[2];
1643 struct hns_roce_vf_res_a *req_a;
1644 struct hns_roce_vf_res_b *req_b;
1645 int i;
1646
1647 req_a = (struct hns_roce_vf_res_a *)desc[0].data;
1648 req_b = (struct hns_roce_vf_res_b *)desc[1].data;
1649 for (i = 0; i < 2; i++) {
1650 hns_roce_cmq_setup_basic_desc(&desc[i],
1651 HNS_ROCE_OPC_ALLOC_VF_RES, false);
1652
1653 if (i == 0)
1654 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1655 else
1656 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1657 }
1658
1659 roce_set_field(req_a->vf_qpc_bt_idx_num,
1660 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M,
1661 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0);
1662 roce_set_field(req_a->vf_qpc_bt_idx_num,
1663 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M,
1664 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S, HNS_ROCE_VF_QPC_BT_NUM);
1665
1666 roce_set_field(req_a->vf_srqc_bt_idx_num,
1667 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M,
1668 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0);
1669 roce_set_field(req_a->vf_srqc_bt_idx_num,
1670 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M,
1671 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S,
1672 HNS_ROCE_VF_SRQC_BT_NUM);
1673
1674 roce_set_field(req_a->vf_cqc_bt_idx_num,
1675 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M,
1676 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0);
1677 roce_set_field(req_a->vf_cqc_bt_idx_num,
1678 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M,
1679 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S, HNS_ROCE_VF_CQC_BT_NUM);
1680
1681 roce_set_field(req_a->vf_mpt_bt_idx_num,
1682 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M,
1683 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0);
1684 roce_set_field(req_a->vf_mpt_bt_idx_num,
1685 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M,
1686 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S, HNS_ROCE_VF_MPT_BT_NUM);
1687
1688 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_IDX_M,
1689 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0);
1690 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_NUM_M,
1691 VF_RES_A_DATA_5_VF_EQC_NUM_S, HNS_ROCE_VF_EQC_NUM);
1692
1693 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_IDX_M,
1694 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0);
1695 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_NUM_M,
1696 VF_RES_B_DATA_1_VF_SMAC_NUM_S, HNS_ROCE_VF_SMAC_NUM);
1697
1698 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_IDX_M,
1699 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0);
1700 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_NUM_M,
1701 VF_RES_B_DATA_2_VF_SGID_NUM_S, HNS_ROCE_VF_SGID_NUM);
1702
1703 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_QID_IDX_M,
1704 VF_RES_B_DATA_3_VF_QID_IDX_S, 0);
1705 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_SL_NUM_M,
1706 VF_RES_B_DATA_3_VF_SL_NUM_S, HNS_ROCE_VF_SL_NUM);
1707
1708 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M,
1709 VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S, 0);
1710 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M,
1711 VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S,
1712 HNS_ROCE_VF_SCCC_BT_NUM);
1713
1714 return hns_roce_cmq_send(hr_dev, desc, 2);
1715 }
1716
hns_roce_v2_set_bt(struct hns_roce_dev * hr_dev)1717 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1718 {
1719 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num;
1720 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;
1721 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;
1722 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;
1723 u8 sccc_hop_num = hr_dev->caps.sccc_hop_num;
1724 struct hns_roce_cfg_bt_attr *req;
1725 struct hns_roce_cmq_desc desc;
1726
1727 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1728 req = (struct hns_roce_cfg_bt_attr *)desc.data;
1729 memset(req, 0, sizeof(*req));
1730
1731 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
1732 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
1733 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET);
1734 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
1735 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
1736 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET);
1737 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
1738 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
1739 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
1740
1741 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
1742 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
1743 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET);
1744 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
1745 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
1746 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET);
1747 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
1748 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
1749 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
1750
1751 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
1752 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
1753 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET);
1754 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
1755 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
1756 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET);
1757 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
1758 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
1759 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
1760
1761 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
1762 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
1763 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET);
1764 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
1765 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
1766 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET);
1767 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
1768 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
1769 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
1770
1771 roce_set_field(req->vf_sccc_cfg,
1772 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M,
1773 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S,
1774 hr_dev->caps.sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1775 roce_set_field(req->vf_sccc_cfg,
1776 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M,
1777 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S,
1778 hr_dev->caps.sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1779 roce_set_field(req->vf_sccc_cfg,
1780 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M,
1781 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S,
1782 sccc_hop_num ==
1783 HNS_ROCE_HOP_NUM_0 ? 0 : sccc_hop_num);
1784
1785 return hns_roce_cmq_send(hr_dev, &desc, 1);
1786 }
1787
set_default_caps(struct hns_roce_dev * hr_dev)1788 static void set_default_caps(struct hns_roce_dev *hr_dev)
1789 {
1790 struct hns_roce_caps *caps = &hr_dev->caps;
1791
1792 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
1793 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
1794 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
1795 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM;
1796 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
1797 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
1798 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
1799 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM;
1800 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1801 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
1802 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
1803 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
1804 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM;
1805 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM;
1806 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
1807 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
1808 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1809 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
1810 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1811 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
1812 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
1813 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1814 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1815 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1816 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1817 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
1818 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ;
1819 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
1820 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ;
1821 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
1822 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ;
1823 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1824 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
1825 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ;
1826 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE;
1827 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1828 caps->reserved_lkey = 0;
1829 caps->reserved_pds = 0;
1830 caps->reserved_mrws = 1;
1831 caps->reserved_uars = 0;
1832 caps->reserved_cqs = 0;
1833 caps->reserved_srqs = 0;
1834 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS;
1835
1836 caps->qpc_ba_pg_sz = 0;
1837 caps->qpc_buf_pg_sz = 0;
1838 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1839 caps->srqc_ba_pg_sz = 0;
1840 caps->srqc_buf_pg_sz = 0;
1841 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1842 caps->cqc_ba_pg_sz = 0;
1843 caps->cqc_buf_pg_sz = 0;
1844 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1845 caps->mpt_ba_pg_sz = 0;
1846 caps->mpt_buf_pg_sz = 0;
1847 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1848 caps->mtt_ba_pg_sz = 0;
1849 caps->mtt_buf_pg_sz = 0;
1850 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
1851 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM;
1852 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM;
1853 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM;
1854 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
1855 caps->cqe_buf_pg_sz = 0;
1856 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
1857 caps->srqwqe_ba_pg_sz = 0;
1858 caps->srqwqe_buf_pg_sz = 0;
1859 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM;
1860 caps->idx_ba_pg_sz = 0;
1861 caps->idx_buf_pg_sz = 0;
1862 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM;
1863 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
1864
1865 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
1866 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
1867 HNS_ROCE_CAP_FLAG_RECORD_DB |
1868 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB;
1869
1870 caps->pkey_table_len[0] = 1;
1871 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
1872 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
1873 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
1874 caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
1875 caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
1876 caps->local_ca_ack_delay = 0;
1877 caps->max_mtu = IB_MTU_4096;
1878
1879 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR;
1880 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE;
1881
1882 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW |
1883 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR |
1884 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL;
1885
1886 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM;
1887 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
1888 caps->qpc_timer_ba_pg_sz = 0;
1889 caps->qpc_timer_buf_pg_sz = 0;
1890 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1891 caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM;
1892 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
1893 caps->cqc_timer_ba_pg_sz = 0;
1894 caps->cqc_timer_buf_pg_sz = 0;
1895 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1896
1897 caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ;
1898 caps->sccc_ba_pg_sz = 0;
1899 caps->sccc_buf_pg_sz = 0;
1900 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM;
1901
1902 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1903 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
1904 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
1905 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;
1906 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
1907 }
1908 }
1909
calc_pg_sz(int obj_num,int obj_size,int hop_num,int ctx_bt_num,int * buf_page_size,int * bt_page_size,u32 hem_type)1910 static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num,
1911 int *buf_page_size, int *bt_page_size, u32 hem_type)
1912 {
1913 u64 obj_per_chunk;
1914 u64 bt_chunk_size = PAGE_SIZE;
1915 u64 buf_chunk_size = PAGE_SIZE;
1916 u64 obj_per_chunk_default = buf_chunk_size / obj_size;
1917
1918 *buf_page_size = 0;
1919 *bt_page_size = 0;
1920
1921 switch (hop_num) {
1922 case 3:
1923 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1924 (bt_chunk_size / BA_BYTE_LEN) *
1925 (bt_chunk_size / BA_BYTE_LEN) *
1926 obj_per_chunk_default;
1927 break;
1928 case 2:
1929 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1930 (bt_chunk_size / BA_BYTE_LEN) *
1931 obj_per_chunk_default;
1932 break;
1933 case 1:
1934 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1935 obj_per_chunk_default;
1936 break;
1937 case HNS_ROCE_HOP_NUM_0:
1938 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
1939 break;
1940 default:
1941 pr_err("table %u not support hop_num = %u!\n", hem_type,
1942 hop_num);
1943 return;
1944 }
1945
1946 if (hem_type >= HEM_TYPE_MTT)
1947 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1948 else
1949 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1950 }
1951
hns_roce_query_pf_caps(struct hns_roce_dev * hr_dev)1952 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
1953 {
1954 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];
1955 struct hns_roce_caps *caps = &hr_dev->caps;
1956 struct hns_roce_query_pf_caps_a *resp_a;
1957 struct hns_roce_query_pf_caps_b *resp_b;
1958 struct hns_roce_query_pf_caps_c *resp_c;
1959 struct hns_roce_query_pf_caps_d *resp_d;
1960 struct hns_roce_query_pf_caps_e *resp_e;
1961 int ctx_hop_num;
1962 int pbl_hop_num;
1963 int ret;
1964 int i;
1965
1966 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {
1967 hns_roce_cmq_setup_basic_desc(&desc[i],
1968 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM,
1969 true);
1970 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1))
1971 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1972 else
1973 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1974 }
1975
1976 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM);
1977 if (ret)
1978 return ret;
1979
1980 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
1981 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
1982 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
1983 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
1984 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
1985
1986 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay;
1987 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg);
1988 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline);
1989 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg);
1990 caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg);
1991 caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer);
1992 caps->num_cqc_timer = le16_to_cpu(resp_a->num_cqc_timer);
1993 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges);
1994 caps->num_aeq_vectors = resp_a->num_aeq_vectors;
1995 caps->num_other_vectors = resp_a->num_other_vectors;
1996 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz;
1997 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz;
1998 caps->max_srq_desc_sz = resp_a->max_srq_desc_sz;
1999 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE;
2000
2001 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz;
2002 caps->irrl_entry_sz = resp_b->irrl_entry_sz;
2003 caps->trrl_entry_sz = resp_b->trrl_entry_sz;
2004 caps->cqc_entry_sz = resp_b->cqc_entry_sz;
2005 caps->srqc_entry_sz = resp_b->srqc_entry_sz;
2006 caps->idx_entry_sz = resp_b->idx_entry_sz;
2007 caps->sccc_sz = resp_b->sccc_sz;
2008 caps->max_mtu = resp_b->max_mtu;
2009 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ;
2010 caps->min_cqes = resp_b->min_cqes;
2011 caps->min_wqes = resp_b->min_wqes;
2012 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap);
2013 caps->pkey_table_len[0] = resp_b->pkey_table_len;
2014 caps->phy_num_uars = resp_b->phy_num_uars;
2015 ctx_hop_num = resp_b->ctx_hop_num;
2016 pbl_hop_num = resp_b->pbl_hop_num;
2017
2018 caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds,
2019 V2_QUERY_PF_CAPS_C_NUM_PDS_M,
2020 V2_QUERY_PF_CAPS_C_NUM_PDS_S);
2021 caps->flags = roce_get_field(resp_c->cap_flags_num_pds,
2022 V2_QUERY_PF_CAPS_C_CAP_FLAGS_M,
2023 V2_QUERY_PF_CAPS_C_CAP_FLAGS_S);
2024 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) <<
2025 HNS_ROCE_CAP_FLAGS_EX_SHIFT;
2026
2027 caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs,
2028 V2_QUERY_PF_CAPS_C_NUM_CQS_M,
2029 V2_QUERY_PF_CAPS_C_NUM_CQS_S);
2030 caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs,
2031 V2_QUERY_PF_CAPS_C_MAX_GID_M,
2032 V2_QUERY_PF_CAPS_C_MAX_GID_S);
2033 caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth,
2034 V2_QUERY_PF_CAPS_C_CQ_DEPTH_M,
2035 V2_QUERY_PF_CAPS_C_CQ_DEPTH_S);
2036 caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws,
2037 V2_QUERY_PF_CAPS_C_NUM_MRWS_M,
2038 V2_QUERY_PF_CAPS_C_NUM_MRWS_S);
2039 caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps,
2040 V2_QUERY_PF_CAPS_C_NUM_QPS_M,
2041 V2_QUERY_PF_CAPS_C_NUM_QPS_S);
2042 caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps,
2043 V2_QUERY_PF_CAPS_C_MAX_ORD_M,
2044 V2_QUERY_PF_CAPS_C_MAX_ORD_S);
2045 caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
2046 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
2047 caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs,
2048 V2_QUERY_PF_CAPS_D_NUM_SRQS_M,
2049 V2_QUERY_PF_CAPS_D_NUM_SRQS_S);
2050 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
2051 caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth,
2052 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M,
2053 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S);
2054 caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth,
2055 V2_QUERY_PF_CAPS_D_NUM_CEQS_M,
2056 V2_QUERY_PF_CAPS_D_NUM_CEQS_S);
2057 caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth,
2058 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M,
2059 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S);
2060 caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth,
2061 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M,
2062 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S);
2063 caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth,
2064 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M,
2065 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S);
2066 caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds,
2067 V2_QUERY_PF_CAPS_D_RSV_PDS_M,
2068 V2_QUERY_PF_CAPS_D_RSV_PDS_S);
2069 caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds,
2070 V2_QUERY_PF_CAPS_D_NUM_UARS_M,
2071 V2_QUERY_PF_CAPS_D_NUM_UARS_S);
2072 caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps,
2073 V2_QUERY_PF_CAPS_D_RSV_QPS_M,
2074 V2_QUERY_PF_CAPS_D_RSV_QPS_S);
2075 caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps,
2076 V2_QUERY_PF_CAPS_D_RSV_UARS_M,
2077 V2_QUERY_PF_CAPS_D_RSV_UARS_S);
2078 caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws,
2079 V2_QUERY_PF_CAPS_E_RSV_MRWS_M,
2080 V2_QUERY_PF_CAPS_E_RSV_MRWS_S);
2081 caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws,
2082 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M,
2083 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S);
2084 caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs,
2085 V2_QUERY_PF_CAPS_E_RSV_CQS_M,
2086 V2_QUERY_PF_CAPS_E_RSV_CQS_S);
2087 caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs,
2088 V2_QUERY_PF_CAPS_E_RSV_SRQS_M,
2089 V2_QUERY_PF_CAPS_E_RSV_SRQS_S);
2090 caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey,
2091 V2_QUERY_PF_CAPS_E_RSV_LKEYS_M,
2092 V2_QUERY_PF_CAPS_E_RSV_LKEYS_S);
2093 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
2094 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
2095 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
2096 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
2097
2098 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
2099 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
2100 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
2101 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
2102 caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
2103 caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
2104 caps->mtt_ba_pg_sz = 0;
2105 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
2106 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
2107 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
2108
2109 caps->qpc_hop_num = ctx_hop_num;
2110 caps->srqc_hop_num = ctx_hop_num;
2111 caps->cqc_hop_num = ctx_hop_num;
2112 caps->mpt_hop_num = ctx_hop_num;
2113 caps->mtt_hop_num = pbl_hop_num;
2114 caps->cqe_hop_num = pbl_hop_num;
2115 caps->srqwqe_hop_num = pbl_hop_num;
2116 caps->idx_hop_num = pbl_hop_num;
2117 caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
2118 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M,
2119 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S);
2120 caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
2121 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M,
2122 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S);
2123 caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
2124 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M,
2125 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S);
2126
2127 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2128 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
2129 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
2130 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;
2131 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
2132 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ;
2133 }
2134
2135 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num,
2136 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
2137 HEM_TYPE_QPC);
2138 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
2139 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
2140 HEM_TYPE_MTPT);
2141 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
2142 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
2143 HEM_TYPE_CQC);
2144 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, caps->srqc_hop_num,
2145 caps->srqc_bt_num, &caps->srqc_buf_pg_sz,
2146 &caps->srqc_ba_pg_sz, HEM_TYPE_SRQC);
2147
2148 caps->sccc_hop_num = ctx_hop_num;
2149 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2150 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2151
2152 calc_pg_sz(caps->num_qps, caps->sccc_sz,
2153 caps->sccc_hop_num, caps->sccc_bt_num,
2154 &caps->sccc_buf_pg_sz, &caps->sccc_ba_pg_sz,
2155 HEM_TYPE_SCCC);
2156 calc_pg_sz(caps->num_cqc_timer, caps->cqc_timer_entry_sz,
2157 caps->cqc_timer_hop_num, caps->cqc_timer_bt_num,
2158 &caps->cqc_timer_buf_pg_sz,
2159 &caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER);
2160
2161 calc_pg_sz(caps->num_cqe_segs, caps->mtt_entry_sz, caps->cqe_hop_num,
2162 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
2163 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
2164 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
2165 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
2166 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, caps->idx_hop_num,
2167 1, &caps->idx_buf_pg_sz, &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
2168
2169 if (!(caps->page_size_cap & PAGE_SIZE))
2170 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
2171
2172 return 0;
2173 }
2174
hns_roce_config_qpc_size(struct hns_roce_dev * hr_dev)2175 static int hns_roce_config_qpc_size(struct hns_roce_dev *hr_dev)
2176 {
2177 struct hns_roce_cmq_desc desc;
2178 struct hns_roce_cfg_entry_size *cfg_size =
2179 (struct hns_roce_cfg_entry_size *)desc.data;
2180
2181 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE,
2182 false);
2183
2184 cfg_size->type = cpu_to_le32(HNS_ROCE_CFG_QPC_SIZE);
2185 cfg_size->size = cpu_to_le32(hr_dev->caps.qpc_sz);
2186
2187 return hns_roce_cmq_send(hr_dev, &desc, 1);
2188 }
2189
hns_roce_config_sccc_size(struct hns_roce_dev * hr_dev)2190 static int hns_roce_config_sccc_size(struct hns_roce_dev *hr_dev)
2191 {
2192 struct hns_roce_cmq_desc desc;
2193 struct hns_roce_cfg_entry_size *cfg_size =
2194 (struct hns_roce_cfg_entry_size *)desc.data;
2195
2196 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE,
2197 false);
2198
2199 cfg_size->type = cpu_to_le32(HNS_ROCE_CFG_SCCC_SIZE);
2200 cfg_size->size = cpu_to_le32(hr_dev->caps.sccc_sz);
2201
2202 return hns_roce_cmq_send(hr_dev, &desc, 1);
2203 }
2204
hns_roce_config_entry_size(struct hns_roce_dev * hr_dev)2205 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev)
2206 {
2207 int ret;
2208
2209 if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09)
2210 return 0;
2211
2212 ret = hns_roce_config_qpc_size(hr_dev);
2213 if (ret) {
2214 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret);
2215 return ret;
2216 }
2217
2218 ret = hns_roce_config_sccc_size(hr_dev);
2219 if (ret)
2220 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret);
2221
2222 return ret;
2223 }
2224
hns_roce_v2_profile(struct hns_roce_dev * hr_dev)2225 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
2226 {
2227 struct hns_roce_caps *caps = &hr_dev->caps;
2228 int ret;
2229
2230 ret = hns_roce_cmq_query_hw_info(hr_dev);
2231 if (ret) {
2232 dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n",
2233 ret);
2234 return ret;
2235 }
2236
2237 ret = hns_roce_query_fw_ver(hr_dev);
2238 if (ret) {
2239 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n",
2240 ret);
2241 return ret;
2242 }
2243
2244 ret = hns_roce_config_global_param(hr_dev);
2245 if (ret) {
2246 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n",
2247 ret);
2248 return ret;
2249 }
2250
2251 /* Get pf resource owned by every pf */
2252 ret = hns_roce_query_pf_resource(hr_dev);
2253 if (ret) {
2254 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n",
2255 ret);
2256 return ret;
2257 }
2258
2259 ret = hns_roce_query_pf_timer_resource(hr_dev);
2260 if (ret) {
2261 dev_err(hr_dev->dev,
2262 "failed to query pf timer resource, ret = %d.\n", ret);
2263 return ret;
2264 }
2265
2266 ret = hns_roce_set_vf_switch_param(hr_dev, 0);
2267 if (ret) {
2268 dev_err(hr_dev->dev,
2269 "failed to set function switch param, ret = %d.\n",
2270 ret);
2271 return ret;
2272 }
2273
2274 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
2275 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
2276
2277 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
2278 caps->pbl_buf_pg_sz = 0;
2279 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
2280 caps->eqe_ba_pg_sz = 0;
2281 caps->eqe_buf_pg_sz = 0;
2282 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
2283 caps->tsq_buf_pg_sz = 0;
2284
2285 ret = hns_roce_query_pf_caps(hr_dev);
2286 if (ret)
2287 set_default_caps(hr_dev);
2288
2289 ret = hns_roce_alloc_vf_resource(hr_dev);
2290 if (ret) {
2291 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n",
2292 ret);
2293 return ret;
2294 }
2295
2296 ret = hns_roce_v2_set_bt(hr_dev);
2297 if (ret) {
2298 dev_err(hr_dev->dev,
2299 "Configure bt attribute fail, ret = %d.\n", ret);
2300 return ret;
2301 }
2302
2303 /* Configure the size of QPC, SCCC, etc. */
2304 ret = hns_roce_config_entry_size(hr_dev);
2305
2306 return ret;
2307 }
2308
hns_roce_config_link_table(struct hns_roce_dev * hr_dev,enum hns_roce_link_table_type type)2309 static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev,
2310 enum hns_roce_link_table_type type)
2311 {
2312 struct hns_roce_cmq_desc desc[2];
2313 struct hns_roce_cfg_llm_a *req_a =
2314 (struct hns_roce_cfg_llm_a *)desc[0].data;
2315 struct hns_roce_cfg_llm_b *req_b =
2316 (struct hns_roce_cfg_llm_b *)desc[1].data;
2317 struct hns_roce_v2_priv *priv = hr_dev->priv;
2318 struct hns_roce_link_table *link_tbl;
2319 struct hns_roce_link_table_entry *entry;
2320 enum hns_roce_opcode_type opcode;
2321 u32 page_num;
2322 int i;
2323
2324 switch (type) {
2325 case TSQ_LINK_TABLE:
2326 link_tbl = &priv->tsq;
2327 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2328 break;
2329 case TPQ_LINK_TABLE:
2330 link_tbl = &priv->tpq;
2331 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM;
2332 break;
2333 default:
2334 return -EINVAL;
2335 }
2336
2337 page_num = link_tbl->npages;
2338 entry = link_tbl->table.buf;
2339
2340 for (i = 0; i < 2; i++) {
2341 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false);
2342
2343 if (i == 0)
2344 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2345 else
2346 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2347 }
2348
2349 req_a->base_addr_l = cpu_to_le32(link_tbl->table.map & 0xffffffff);
2350 req_a->base_addr_h = cpu_to_le32(link_tbl->table.map >> 32);
2351 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_DEPTH_M,
2352 CFG_LLM_QUE_DEPTH_S, link_tbl->npages);
2353 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_PGSZ_M,
2354 CFG_LLM_QUE_PGSZ_S, link_tbl->pg_sz);
2355 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_INIT_EN_M,
2356 CFG_LLM_INIT_EN_S, 1);
2357 req_a->head_ba_l = cpu_to_le32(entry[0].blk_ba0);
2358 req_a->head_ba_h_nxtptr = cpu_to_le32(entry[0].blk_ba1_nxt_ptr);
2359 roce_set_field(req_a->head_ptr, CFG_LLM_HEAD_PTR_M, CFG_LLM_HEAD_PTR_S,
2360 0);
2361
2362 req_b->tail_ba_l = cpu_to_le32(entry[page_num - 1].blk_ba0);
2363 roce_set_field(req_b->tail_ba_h, CFG_LLM_TAIL_BA_H_M,
2364 CFG_LLM_TAIL_BA_H_S,
2365 entry[page_num - 1].blk_ba1_nxt_ptr &
2366 HNS_ROCE_LINK_TABLE_BA1_M);
2367 roce_set_field(req_b->tail_ptr, CFG_LLM_TAIL_PTR_M, CFG_LLM_TAIL_PTR_S,
2368 (entry[page_num - 2].blk_ba1_nxt_ptr &
2369 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >>
2370 HNS_ROCE_LINK_TABLE_NXT_PTR_S);
2371
2372 return hns_roce_cmq_send(hr_dev, desc, 2);
2373 }
2374
hns_roce_init_link_table(struct hns_roce_dev * hr_dev,enum hns_roce_link_table_type type)2375 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev,
2376 enum hns_roce_link_table_type type)
2377 {
2378 struct hns_roce_v2_priv *priv = hr_dev->priv;
2379 struct hns_roce_link_table *link_tbl;
2380 struct hns_roce_link_table_entry *entry;
2381 struct device *dev = hr_dev->dev;
2382 u32 buf_chk_sz;
2383 dma_addr_t t;
2384 int func_num = 1;
2385 int pg_num_a;
2386 int pg_num_b;
2387 int pg_num;
2388 int size;
2389 int i;
2390
2391 switch (type) {
2392 case TSQ_LINK_TABLE:
2393 link_tbl = &priv->tsq;
2394 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT);
2395 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz;
2396 pg_num_b = hr_dev->caps.sl_num * 4 + 2;
2397 break;
2398 case TPQ_LINK_TABLE:
2399 link_tbl = &priv->tpq;
2400 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT);
2401 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz;
2402 pg_num_b = 2 * 4 * func_num + 2;
2403 break;
2404 default:
2405 return -EINVAL;
2406 }
2407
2408 pg_num = max(pg_num_a, pg_num_b);
2409 size = pg_num * sizeof(struct hns_roce_link_table_entry);
2410
2411 link_tbl->table.buf = dma_alloc_coherent(dev, size,
2412 &link_tbl->table.map,
2413 GFP_KERNEL);
2414 if (!link_tbl->table.buf)
2415 goto out;
2416
2417 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list),
2418 GFP_KERNEL);
2419 if (!link_tbl->pg_list)
2420 goto err_kcalloc_failed;
2421
2422 entry = link_tbl->table.buf;
2423 for (i = 0; i < pg_num; ++i) {
2424 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz,
2425 &t, GFP_KERNEL);
2426 if (!link_tbl->pg_list[i].buf)
2427 goto err_alloc_buf_failed;
2428
2429 link_tbl->pg_list[i].map = t;
2430
2431 entry[i].blk_ba0 = (u32)(t >> 12);
2432 entry[i].blk_ba1_nxt_ptr = (u32)(t >> 44);
2433
2434 if (i < (pg_num - 1))
2435 entry[i].blk_ba1_nxt_ptr |=
2436 (i + 1) << HNS_ROCE_LINK_TABLE_NXT_PTR_S;
2437 }
2438 link_tbl->npages = pg_num;
2439 link_tbl->pg_sz = buf_chk_sz;
2440
2441 return hns_roce_config_link_table(hr_dev, type);
2442
2443 err_alloc_buf_failed:
2444 for (i -= 1; i >= 0; i--)
2445 dma_free_coherent(dev, buf_chk_sz,
2446 link_tbl->pg_list[i].buf,
2447 link_tbl->pg_list[i].map);
2448 kfree(link_tbl->pg_list);
2449
2450 err_kcalloc_failed:
2451 dma_free_coherent(dev, size, link_tbl->table.buf,
2452 link_tbl->table.map);
2453
2454 out:
2455 return -ENOMEM;
2456 }
2457
hns_roce_free_link_table(struct hns_roce_dev * hr_dev,struct hns_roce_link_table * link_tbl)2458 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev,
2459 struct hns_roce_link_table *link_tbl)
2460 {
2461 struct device *dev = hr_dev->dev;
2462 int size;
2463 int i;
2464
2465 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry);
2466
2467 for (i = 0; i < link_tbl->npages; ++i)
2468 if (link_tbl->pg_list[i].buf)
2469 dma_free_coherent(dev, link_tbl->pg_sz,
2470 link_tbl->pg_list[i].buf,
2471 link_tbl->pg_list[i].map);
2472 kfree(link_tbl->pg_list);
2473
2474 dma_free_coherent(dev, size, link_tbl->table.buf,
2475 link_tbl->table.map);
2476 }
2477
hns_roce_v2_init(struct hns_roce_dev * hr_dev)2478 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
2479 {
2480 struct hns_roce_v2_priv *priv = hr_dev->priv;
2481 int qpc_count, cqc_count;
2482 int ret, i;
2483
2484 /* TSQ includes SQ doorbell and ack doorbell */
2485 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE);
2486 if (ret) {
2487 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret);
2488 return ret;
2489 }
2490
2491 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE);
2492 if (ret) {
2493 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret);
2494 goto err_tpq_init_failed;
2495 }
2496
2497 /* Alloc memory for QPC Timer buffer space chunk */
2498 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
2499 qpc_count++) {
2500 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
2501 qpc_count);
2502 if (ret) {
2503 dev_err(hr_dev->dev, "QPC Timer get failed\n");
2504 goto err_qpc_timer_failed;
2505 }
2506 }
2507
2508 /* Alloc memory for CQC Timer buffer space chunk */
2509 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
2510 cqc_count++) {
2511 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
2512 cqc_count);
2513 if (ret) {
2514 dev_err(hr_dev->dev, "CQC Timer get failed\n");
2515 goto err_cqc_timer_failed;
2516 }
2517 }
2518
2519 return 0;
2520
2521 err_cqc_timer_failed:
2522 for (i = 0; i < cqc_count; i++)
2523 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2524
2525 err_qpc_timer_failed:
2526 for (i = 0; i < qpc_count; i++)
2527 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2528
2529 hns_roce_free_link_table(hr_dev, &priv->tpq);
2530
2531 err_tpq_init_failed:
2532 hns_roce_free_link_table(hr_dev, &priv->tsq);
2533
2534 return ret;
2535 }
2536
hns_roce_v2_exit(struct hns_roce_dev * hr_dev)2537 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
2538 {
2539 struct hns_roce_v2_priv *priv = hr_dev->priv;
2540
2541 hns_roce_function_clear(hr_dev);
2542
2543 hns_roce_free_link_table(hr_dev, &priv->tpq);
2544 hns_roce_free_link_table(hr_dev, &priv->tsq);
2545 }
2546
hns_roce_query_mbox_status(struct hns_roce_dev * hr_dev)2547 static int hns_roce_query_mbox_status(struct hns_roce_dev *hr_dev)
2548 {
2549 struct hns_roce_cmq_desc desc;
2550 struct hns_roce_mbox_status *mb_st =
2551 (struct hns_roce_mbox_status *)desc.data;
2552 enum hns_roce_cmd_return_status status;
2553
2554 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, true);
2555
2556 status = hns_roce_cmq_send(hr_dev, &desc, 1);
2557 if (status)
2558 return status;
2559
2560 return le32_to_cpu(mb_st->mb_status_hw_run);
2561 }
2562
hns_roce_v2_cmd_pending(struct hns_roce_dev * hr_dev)2563 static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
2564 {
2565 u32 status = hns_roce_query_mbox_status(hr_dev);
2566
2567 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
2568 }
2569
hns_roce_v2_cmd_complete(struct hns_roce_dev * hr_dev)2570 static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
2571 {
2572 u32 status = hns_roce_query_mbox_status(hr_dev);
2573
2574 return status & HNS_ROCE_HW_MB_STATUS_MASK;
2575 }
2576
hns_roce_mbox_post(struct hns_roce_dev * hr_dev,u64 in_param,u64 out_param,u32 in_modifier,u8 op_modifier,u16 op,u16 token,int event)2577 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param,
2578 u64 out_param, u32 in_modifier, u8 op_modifier,
2579 u16 op, u16 token, int event)
2580 {
2581 struct hns_roce_cmq_desc desc;
2582 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
2583
2584 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
2585
2586 mb->in_param_l = cpu_to_le32(in_param);
2587 mb->in_param_h = cpu_to_le32(in_param >> 32);
2588 mb->out_param_l = cpu_to_le32(out_param);
2589 mb->out_param_h = cpu_to_le32(out_param >> 32);
2590 mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op);
2591 mb->token_event_en = cpu_to_le32(event << 16 | token);
2592
2593 return hns_roce_cmq_send(hr_dev, &desc, 1);
2594 }
2595
hns_roce_v2_post_mbox(struct hns_roce_dev * hr_dev,u64 in_param,u64 out_param,u32 in_modifier,u8 op_modifier,u16 op,u16 token,int event)2596 static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
2597 u64 out_param, u32 in_modifier, u8 op_modifier,
2598 u16 op, u16 token, int event)
2599 {
2600 struct device *dev = hr_dev->dev;
2601 unsigned long end;
2602 int ret;
2603
2604 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
2605 while (hns_roce_v2_cmd_pending(hr_dev)) {
2606 if (time_after(jiffies, end)) {
2607 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
2608 (int)end);
2609 return -EAGAIN;
2610 }
2611 cond_resched();
2612 }
2613
2614 ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier,
2615 op_modifier, op, token, event);
2616 if (ret)
2617 dev_err(dev, "Post mailbox fail(%d)\n", ret);
2618
2619 return ret;
2620 }
2621
hns_roce_v2_chk_mbox(struct hns_roce_dev * hr_dev,unsigned long timeout)2622 static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
2623 unsigned long timeout)
2624 {
2625 struct device *dev = hr_dev->dev;
2626 unsigned long end;
2627 u32 status;
2628
2629 end = msecs_to_jiffies(timeout) + jiffies;
2630 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
2631 cond_resched();
2632
2633 if (hns_roce_v2_cmd_pending(hr_dev)) {
2634 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
2635 return -ETIMEDOUT;
2636 }
2637
2638 status = hns_roce_v2_cmd_complete(hr_dev);
2639 if (status != 0x1) {
2640 if (status == CMD_RST_PRC_EBUSY)
2641 return status;
2642
2643 dev_err(dev, "mailbox status 0x%x!\n", status);
2644 return -EBUSY;
2645 }
2646
2647 return 0;
2648 }
2649
hns_roce_config_sgid_table(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,enum hns_roce_sgid_type sgid_type)2650 static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev,
2651 int gid_index, const union ib_gid *gid,
2652 enum hns_roce_sgid_type sgid_type)
2653 {
2654 struct hns_roce_cmq_desc desc;
2655 struct hns_roce_cfg_sgid_tb *sgid_tb =
2656 (struct hns_roce_cfg_sgid_tb *)desc.data;
2657 u32 *p;
2658
2659 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
2660
2661 roce_set_field(sgid_tb->table_idx_rsv, CFG_SGID_TB_TABLE_IDX_M,
2662 CFG_SGID_TB_TABLE_IDX_S, gid_index);
2663 roce_set_field(sgid_tb->vf_sgid_type_rsv, CFG_SGID_TB_VF_SGID_TYPE_M,
2664 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type);
2665
2666 p = (u32 *)&gid->raw[0];
2667 sgid_tb->vf_sgid_l = cpu_to_le32(*p);
2668
2669 p = (u32 *)&gid->raw[4];
2670 sgid_tb->vf_sgid_ml = cpu_to_le32(*p);
2671
2672 p = (u32 *)&gid->raw[8];
2673 sgid_tb->vf_sgid_mh = cpu_to_le32(*p);
2674
2675 p = (u32 *)&gid->raw[0xc];
2676 sgid_tb->vf_sgid_h = cpu_to_le32(*p);
2677
2678 return hns_roce_cmq_send(hr_dev, &desc, 1);
2679 }
2680
hns_roce_v2_set_gid(struct hns_roce_dev * hr_dev,u8 port,int gid_index,const union ib_gid * gid,const struct ib_gid_attr * attr)2681 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
2682 int gid_index, const union ib_gid *gid,
2683 const struct ib_gid_attr *attr)
2684 {
2685 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
2686 int ret;
2687
2688 if (!gid || !attr)
2689 return -EINVAL;
2690
2691 if (attr->gid_type == IB_GID_TYPE_ROCE)
2692 sgid_type = GID_TYPE_FLAG_ROCE_V1;
2693
2694 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
2695 if (ipv6_addr_v4mapped((void *)gid))
2696 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
2697 else
2698 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
2699 }
2700
2701 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type);
2702 if (ret)
2703 ibdev_err(&hr_dev->ib_dev,
2704 "failed to configure sgid table, ret = %d!\n",
2705 ret);
2706
2707 return ret;
2708 }
2709
hns_roce_v2_set_mac(struct hns_roce_dev * hr_dev,u8 phy_port,u8 * addr)2710 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
2711 u8 *addr)
2712 {
2713 struct hns_roce_cmq_desc desc;
2714 struct hns_roce_cfg_smac_tb *smac_tb =
2715 (struct hns_roce_cfg_smac_tb *)desc.data;
2716 u16 reg_smac_h;
2717 u32 reg_smac_l;
2718
2719 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
2720
2721 reg_smac_l = *(u32 *)(&addr[0]);
2722 reg_smac_h = *(u16 *)(&addr[4]);
2723
2724 roce_set_field(smac_tb->tb_idx_rsv, CFG_SMAC_TB_IDX_M,
2725 CFG_SMAC_TB_IDX_S, phy_port);
2726 roce_set_field(smac_tb->vf_smac_h_rsv, CFG_SMAC_TB_VF_SMAC_H_M,
2727 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h);
2728 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
2729
2730 return hns_roce_cmq_send(hr_dev, &desc, 1);
2731 }
2732
set_mtpt_pbl(struct hns_roce_dev * hr_dev,struct hns_roce_v2_mpt_entry * mpt_entry,struct hns_roce_mr * mr)2733 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev,
2734 struct hns_roce_v2_mpt_entry *mpt_entry,
2735 struct hns_roce_mr *mr)
2736 {
2737 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 };
2738 struct ib_device *ibdev = &hr_dev->ib_dev;
2739 dma_addr_t pbl_ba;
2740 int i, count;
2741
2742 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
2743 min_t(int, ARRAY_SIZE(pages), mr->npages),
2744 &pbl_ba);
2745 if (count < 1) {
2746 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n",
2747 count);
2748 return -ENOBUFS;
2749 }
2750
2751 /* Aligned to the hardware address access unit */
2752 for (i = 0; i < count; i++)
2753 pages[i] >>= 6;
2754
2755 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
2756 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3);
2757 roce_set_field(mpt_entry->byte_48_mode_ba,
2758 V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S,
2759 upper_32_bits(pbl_ba >> 3));
2760
2761 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
2762 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
2763 V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0]));
2764
2765 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
2766 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
2767 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
2768 roce_set_field(mpt_entry->byte_64_buf_pa1,
2769 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2770 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2771 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
2772
2773 return 0;
2774 }
2775
hns_roce_v2_write_mtpt(struct hns_roce_dev * hr_dev,void * mb_buf,struct hns_roce_mr * mr,unsigned long mtpt_idx)2776 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev,
2777 void *mb_buf, struct hns_roce_mr *mr,
2778 unsigned long mtpt_idx)
2779 {
2780 struct hns_roce_v2_mpt_entry *mpt_entry;
2781 int ret;
2782
2783 mpt_entry = mb_buf;
2784 memset(mpt_entry, 0, sizeof(*mpt_entry));
2785
2786 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2787 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
2788 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2789 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num ==
2790 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
2791 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2792 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2793 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2794 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
2795 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2796 V2_MPT_BYTE_4_PD_S, mr->pd);
2797
2798 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
2799 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 0);
2800 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2801 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S,
2802 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
2803 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S,
2804 mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
2805 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
2806 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
2807 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
2808 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
2809 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
2810 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
2811
2812 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
2813 mr->type == MR_TYPE_MR ? 0 : 1);
2814 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S,
2815 1);
2816
2817 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
2818 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
2819 mpt_entry->lkey = cpu_to_le32(mr->key);
2820 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
2821 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
2822
2823 if (mr->type == MR_TYPE_DMA)
2824 return 0;
2825
2826 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
2827
2828 return ret;
2829 }
2830
hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev * hr_dev,struct hns_roce_mr * mr,int flags,u32 pdn,int mr_access_flags,u64 iova,u64 size,void * mb_buf)2831 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
2832 struct hns_roce_mr *mr, int flags,
2833 u32 pdn, int mr_access_flags, u64 iova,
2834 u64 size, void *mb_buf)
2835 {
2836 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
2837 int ret = 0;
2838
2839 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2840 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
2841
2842 if (flags & IB_MR_REREG_PD) {
2843 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2844 V2_MPT_BYTE_4_PD_S, pdn);
2845 mr->pd = pdn;
2846 }
2847
2848 if (flags & IB_MR_REREG_ACCESS) {
2849 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
2850 V2_MPT_BYTE_8_BIND_EN_S,
2851 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
2852 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
2853 V2_MPT_BYTE_8_ATOMIC_EN_S,
2854 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
2855 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
2856 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
2857 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
2858 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
2859 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
2860 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
2861 }
2862
2863 if (flags & IB_MR_REREG_TRANS) {
2864 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova));
2865 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova));
2866 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
2867 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
2868
2869 mr->iova = iova;
2870 mr->size = size;
2871
2872 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
2873 }
2874
2875 return ret;
2876 }
2877
hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev * hr_dev,void * mb_buf,struct hns_roce_mr * mr)2878 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev,
2879 void *mb_buf, struct hns_roce_mr *mr)
2880 {
2881 struct ib_device *ibdev = &hr_dev->ib_dev;
2882 struct hns_roce_v2_mpt_entry *mpt_entry;
2883 dma_addr_t pbl_ba = 0;
2884
2885 mpt_entry = mb_buf;
2886 memset(mpt_entry, 0, sizeof(*mpt_entry));
2887
2888 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) {
2889 ibdev_err(ibdev, "failed to find frmr mtr.\n");
2890 return -ENOBUFS;
2891 }
2892
2893 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2894 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
2895 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2896 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1);
2897 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2898 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2899 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2900 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
2901 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2902 V2_MPT_BYTE_4_PD_S, mr->pd);
2903
2904 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1);
2905 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
2906 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2907
2908 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1);
2909 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
2910 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0);
2911 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
2912
2913 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
2914
2915 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3));
2916 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
2917 V2_MPT_BYTE_48_PBL_BA_H_S,
2918 upper_32_bits(pbl_ba >> 3));
2919
2920 roce_set_field(mpt_entry->byte_64_buf_pa1,
2921 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2922 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2923 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
2924
2925 return 0;
2926 }
2927
hns_roce_v2_mw_write_mtpt(void * mb_buf,struct hns_roce_mw * mw)2928 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
2929 {
2930 struct hns_roce_v2_mpt_entry *mpt_entry;
2931
2932 mpt_entry = mb_buf;
2933 memset(mpt_entry, 0, sizeof(*mpt_entry));
2934
2935 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2936 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
2937 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2938 V2_MPT_BYTE_4_PD_S, mw->pdn);
2939 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2940 V2_MPT_BYTE_4_PBL_HOP_NUM_S,
2941 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
2942 mw->pbl_hop_num);
2943 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2944 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2945 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2946 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
2947
2948 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
2949 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2950 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 1);
2951
2952 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
2953 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1);
2954 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
2955 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S,
2956 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
2957
2958 roce_set_field(mpt_entry->byte_64_buf_pa1,
2959 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2960 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2961 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2962
2963 mpt_entry->lkey = cpu_to_le32(mw->rkey);
2964
2965 return 0;
2966 }
2967
get_cqe_v2(struct hns_roce_cq * hr_cq,int n)2968 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2969 {
2970 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
2971 }
2972
get_sw_cqe_v2(struct hns_roce_cq * hr_cq,int n)2973 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2974 {
2975 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
2976
2977 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2978 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^
2979 !!(n & hr_cq->cq_depth)) ? cqe : NULL;
2980 }
2981
hns_roce_v2_cq_set_ci(struct hns_roce_cq * hr_cq,u32 ci)2982 static inline void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 ci)
2983 {
2984 *hr_cq->set_ci_db = ci & V2_CQ_DB_PARAMETER_CONS_IDX_M;
2985 }
2986
__hns_roce_v2_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)2987 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2988 struct hns_roce_srq *srq)
2989 {
2990 struct hns_roce_v2_cqe *cqe, *dest;
2991 u32 prod_index;
2992 int nfreed = 0;
2993 int wqe_index;
2994 u8 owner_bit;
2995
2996 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
2997 ++prod_index) {
2998 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
2999 break;
3000 }
3001
3002 /*
3003 * Now backwards through the CQ, removing CQ entries
3004 * that match our QP by overwriting them with next entries.
3005 */
3006 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
3007 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
3008 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
3009 V2_CQE_BYTE_16_LCL_QPN_S) &
3010 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) {
3011 if (srq &&
3012 roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S)) {
3013 wqe_index = roce_get_field(cqe->byte_4,
3014 V2_CQE_BYTE_4_WQE_INDX_M,
3015 V2_CQE_BYTE_4_WQE_INDX_S);
3016 hns_roce_free_srq_wqe(srq, wqe_index);
3017 }
3018 ++nfreed;
3019 } else if (nfreed) {
3020 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
3021 hr_cq->ib_cq.cqe);
3022 owner_bit = roce_get_bit(dest->byte_4,
3023 V2_CQE_BYTE_4_OWNER_S);
3024 memcpy(dest, cqe, sizeof(*cqe));
3025 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S,
3026 owner_bit);
3027 }
3028 }
3029
3030 if (nfreed) {
3031 hr_cq->cons_index += nfreed;
3032 /*
3033 * Make sure update of buffer contents is done before
3034 * updating consumer index.
3035 */
3036 wmb();
3037 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
3038 }
3039 }
3040
hns_roce_v2_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)3041 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3042 struct hns_roce_srq *srq)
3043 {
3044 spin_lock_irq(&hr_cq->lock);
3045 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
3046 spin_unlock_irq(&hr_cq->lock);
3047 }
3048
hns_roce_v2_write_cqc(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq,void * mb_buf,u64 * mtts,dma_addr_t dma_handle)3049 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
3050 struct hns_roce_cq *hr_cq, void *mb_buf,
3051 u64 *mtts, dma_addr_t dma_handle)
3052 {
3053 struct hns_roce_v2_cq_context *cq_context;
3054
3055 cq_context = mb_buf;
3056 memset(cq_context, 0, sizeof(*cq_context));
3057
3058 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M,
3059 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID);
3060 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M,
3061 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE);
3062 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M,
3063 V2_CQC_BYTE_4_SHIFT_S, ilog2(hr_cq->cq_depth));
3064 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M,
3065 V2_CQC_BYTE_4_CEQN_S, hr_cq->vector);
3066
3067 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
3068 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
3069
3070 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQE_SIZE_M,
3071 V2_CQC_BYTE_8_CQE_SIZE_S, hr_cq->cqe_size ==
3072 HNS_ROCE_V3_CQE_SIZE ? 1 : 0);
3073
3074 cq_context->cqe_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
3075
3076 roce_set_field(cq_context->byte_16_hop_addr,
3077 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M,
3078 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S,
3079 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
3080 roce_set_field(cq_context->byte_16_hop_addr,
3081 V2_CQC_BYTE_16_CQE_HOP_NUM_M,
3082 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num ==
3083 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
3084
3085 cq_context->cqe_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
3086 roce_set_field(cq_context->byte_24_pgsz_addr,
3087 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M,
3088 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S,
3089 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
3090 roce_set_field(cq_context->byte_24_pgsz_addr,
3091 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
3092 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
3093 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));
3094 roce_set_field(cq_context->byte_24_pgsz_addr,
3095 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
3096 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
3097 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));
3098
3099 cq_context->cqe_ba = cpu_to_le32(dma_handle >> 3);
3100
3101 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
3102 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
3103
3104 roce_set_bit(cq_context->byte_44_db_record,
3105 V2_CQC_BYTE_44_DB_RECORD_EN_S,
3106 (hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB) ? 1 : 0);
3107
3108 roce_set_field(cq_context->byte_44_db_record,
3109 V2_CQC_BYTE_44_DB_RECORD_ADDR_M,
3110 V2_CQC_BYTE_44_DB_RECORD_ADDR_S,
3111 ((u32)hr_cq->db.dma) >> 1);
3112 cq_context->db_record_addr = cpu_to_le32(hr_cq->db.dma >> 32);
3113
3114 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
3115 V2_CQC_BYTE_56_CQ_MAX_CNT_M,
3116 V2_CQC_BYTE_56_CQ_MAX_CNT_S,
3117 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
3118 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
3119 V2_CQC_BYTE_56_CQ_PERIOD_M,
3120 V2_CQC_BYTE_56_CQ_PERIOD_S,
3121 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
3122 }
3123
hns_roce_v2_req_notify_cq(struct ib_cq * ibcq,enum ib_cq_notify_flags flags)3124 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
3125 enum ib_cq_notify_flags flags)
3126 {
3127 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3128 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3129 u32 notification_flag;
3130 __le32 doorbell[2];
3131
3132 doorbell[0] = 0;
3133 doorbell[1] = 0;
3134
3135 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
3136 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
3137 /*
3138 * flags = 0; Notification Flag = 1, next
3139 * flags = 1; Notification Flag = 0, solocited
3140 */
3141 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S,
3142 hr_cq->cqn);
3143 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S,
3144 HNS_ROCE_V2_CQ_DB_NTR);
3145 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M,
3146 V2_CQ_DB_PARAMETER_CONS_IDX_S, hr_cq->cons_index);
3147 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M,
3148 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3);
3149 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S,
3150 notification_flag);
3151
3152 hns_roce_write64(hr_dev, doorbell, hr_cq->cq_db_l);
3153
3154 return 0;
3155 }
3156
hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe * cqe,struct hns_roce_qp ** cur_qp,struct ib_wc * wc)3157 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
3158 struct hns_roce_qp **cur_qp,
3159 struct ib_wc *wc)
3160 {
3161 struct hns_roce_rinl_sge *sge_list;
3162 u32 wr_num, wr_cnt, sge_num;
3163 u32 sge_cnt, data_len, size;
3164 void *wqe_buf;
3165
3166 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M,
3167 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff;
3168 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1);
3169
3170 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list;
3171 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
3172 wqe_buf = hns_roce_get_recv_wqe(*cur_qp, wr_cnt);
3173 data_len = wc->byte_len;
3174
3175 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
3176 size = min(sge_list[sge_cnt].len, data_len);
3177 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
3178
3179 data_len -= size;
3180 wqe_buf += size;
3181 }
3182
3183 if (unlikely(data_len)) {
3184 wc->status = IB_WC_LOC_LEN_ERR;
3185 return -EAGAIN;
3186 }
3187
3188 return 0;
3189 }
3190
sw_comp(struct hns_roce_qp * hr_qp,struct hns_roce_wq * wq,int num_entries,struct ib_wc * wc)3191 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
3192 int num_entries, struct ib_wc *wc)
3193 {
3194 unsigned int left;
3195 int npolled = 0;
3196
3197 left = wq->head - wq->tail;
3198 if (left == 0)
3199 return 0;
3200
3201 left = min_t(unsigned int, (unsigned int)num_entries, left);
3202 while (npolled < left) {
3203 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3204 wc->status = IB_WC_WR_FLUSH_ERR;
3205 wc->vendor_err = 0;
3206 wc->qp = &hr_qp->ibqp;
3207
3208 wq->tail++;
3209 wc++;
3210 npolled++;
3211 }
3212
3213 return npolled;
3214 }
3215
hns_roce_v2_sw_poll_cq(struct hns_roce_cq * hr_cq,int num_entries,struct ib_wc * wc)3216 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
3217 struct ib_wc *wc)
3218 {
3219 struct hns_roce_qp *hr_qp;
3220 int npolled = 0;
3221
3222 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
3223 npolled += sw_comp(hr_qp, &hr_qp->sq,
3224 num_entries - npolled, wc + npolled);
3225 if (npolled >= num_entries)
3226 goto out;
3227 }
3228
3229 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
3230 npolled += sw_comp(hr_qp, &hr_qp->rq,
3231 num_entries - npolled, wc + npolled);
3232 if (npolled >= num_entries)
3233 goto out;
3234 }
3235
3236 out:
3237 return npolled;
3238 }
3239
get_cqe_status(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp,struct hns_roce_cq * cq,struct hns_roce_v2_cqe * cqe,struct ib_wc * wc)3240 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
3241 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe,
3242 struct ib_wc *wc)
3243 {
3244 static const struct {
3245 u32 cqe_status;
3246 enum ib_wc_status wc_status;
3247 } map[] = {
3248 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS },
3249 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR },
3250 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR },
3251 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR },
3252 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR },
3253 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR },
3254 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR },
3255 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR },
3256 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR },
3257 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR },
3258 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR },
3259 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR,
3260 IB_WC_RETRY_EXC_ERR },
3261 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR },
3262 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR },
3263 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR}
3264 };
3265
3266 u32 cqe_status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M,
3267 V2_CQE_BYTE_4_STATUS_S);
3268 int i;
3269
3270 wc->status = IB_WC_GENERAL_ERR;
3271 for (i = 0; i < ARRAY_SIZE(map); i++)
3272 if (cqe_status == map[i].cqe_status) {
3273 wc->status = map[i].wc_status;
3274 break;
3275 }
3276
3277 if (likely(wc->status == IB_WC_SUCCESS ||
3278 wc->status == IB_WC_WR_FLUSH_ERR))
3279 return;
3280
3281 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status);
3282 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe,
3283 cq->cqe_size, false);
3284
3285 /*
3286 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in
3287 * the standard protocol, the driver must ignore it and needn't to set
3288 * the QP to an error state.
3289 */
3290 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR)
3291 return;
3292
3293 /*
3294 * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state gets
3295 * into errored mode. Hence, as a workaround to this hardware
3296 * limitation, driver needs to assist in flushing. But the flushing
3297 * operation uses mailbox to convey the QP state to the hardware and
3298 * which can sleep due to the mutex protection around the mailbox calls.
3299 * Hence, use the deferred flush for now. Once wc error detected, the
3300 * flushing operation is needed.
3301 */
3302 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag))
3303 init_flush_work(hr_dev, qp);
3304 }
3305
hns_roce_v2_poll_one(struct hns_roce_cq * hr_cq,struct hns_roce_qp ** cur_qp,struct ib_wc * wc)3306 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
3307 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
3308 {
3309 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3310 struct hns_roce_srq *srq = NULL;
3311 struct hns_roce_v2_cqe *cqe;
3312 struct hns_roce_qp *hr_qp;
3313 struct hns_roce_wq *wq;
3314 int is_send;
3315 u16 wqe_ctr;
3316 u32 opcode;
3317 int qpn;
3318 int ret;
3319
3320 /* Find cqe according to consumer index */
3321 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
3322 if (!cqe)
3323 return -EAGAIN;
3324
3325 ++hr_cq->cons_index;
3326 /* Memory barrier */
3327 rmb();
3328
3329 /* 0->SQ, 1->RQ */
3330 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
3331
3332 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
3333 V2_CQE_BYTE_16_LCL_QPN_S);
3334
3335 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
3336 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3337 if (unlikely(!hr_qp)) {
3338 ibdev_err(&hr_dev->ib_dev,
3339 "CQ %06lx with entry for unknown QPN %06x\n",
3340 hr_cq->cqn, qpn & HNS_ROCE_V2_CQE_QPN_MASK);
3341 return -EINVAL;
3342 }
3343 *cur_qp = hr_qp;
3344 }
3345
3346 wc->qp = &(*cur_qp)->ibqp;
3347 wc->vendor_err = 0;
3348
3349 if (is_send) {
3350 wq = &(*cur_qp)->sq;
3351 if ((*cur_qp)->sq_signal_bits) {
3352 /*
3353 * If sg_signal_bit is 1,
3354 * firstly tail pointer updated to wqe
3355 * which current cqe correspond to
3356 */
3357 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
3358 V2_CQE_BYTE_4_WQE_INDX_M,
3359 V2_CQE_BYTE_4_WQE_INDX_S);
3360 wq->tail += (wqe_ctr - (u16)wq->tail) &
3361 (wq->wqe_cnt - 1);
3362 }
3363
3364 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3365 ++wq->tail;
3366 } else if ((*cur_qp)->ibqp.srq) {
3367 srq = to_hr_srq((*cur_qp)->ibqp.srq);
3368 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
3369 V2_CQE_BYTE_4_WQE_INDX_M,
3370 V2_CQE_BYTE_4_WQE_INDX_S);
3371 wc->wr_id = srq->wrid[wqe_ctr];
3372 hns_roce_free_srq_wqe(srq, wqe_ctr);
3373 } else {
3374 /* Update tail pointer, record wr_id */
3375 wq = &(*cur_qp)->rq;
3376 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3377 ++wq->tail;
3378 }
3379
3380 get_cqe_status(hr_dev, *cur_qp, hr_cq, cqe, wc);
3381 if (unlikely(wc->status != IB_WC_SUCCESS))
3382 return 0;
3383
3384 if (is_send) {
3385 wc->wc_flags = 0;
3386 /* SQ corresponding to CQE */
3387 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
3388 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
3389 case HNS_ROCE_V2_WQE_OP_SEND:
3390 wc->opcode = IB_WC_SEND;
3391 break;
3392 case HNS_ROCE_V2_WQE_OP_SEND_WITH_INV:
3393 wc->opcode = IB_WC_SEND;
3394 break;
3395 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM:
3396 wc->opcode = IB_WC_SEND;
3397 wc->wc_flags |= IB_WC_WITH_IMM;
3398 break;
3399 case HNS_ROCE_V2_WQE_OP_RDMA_READ:
3400 wc->opcode = IB_WC_RDMA_READ;
3401 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3402 break;
3403 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE:
3404 wc->opcode = IB_WC_RDMA_WRITE;
3405 break;
3406 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM:
3407 wc->opcode = IB_WC_RDMA_WRITE;
3408 wc->wc_flags |= IB_WC_WITH_IMM;
3409 break;
3410 case HNS_ROCE_V2_WQE_OP_LOCAL_INV:
3411 wc->opcode = IB_WC_LOCAL_INV;
3412 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3413 break;
3414 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP:
3415 wc->opcode = IB_WC_COMP_SWAP;
3416 wc->byte_len = 8;
3417 break;
3418 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD:
3419 wc->opcode = IB_WC_FETCH_ADD;
3420 wc->byte_len = 8;
3421 break;
3422 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP:
3423 wc->opcode = IB_WC_MASKED_COMP_SWAP;
3424 wc->byte_len = 8;
3425 break;
3426 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD:
3427 wc->opcode = IB_WC_MASKED_FETCH_ADD;
3428 wc->byte_len = 8;
3429 break;
3430 case HNS_ROCE_V2_WQE_OP_FAST_REG_PMR:
3431 wc->opcode = IB_WC_REG_MR;
3432 break;
3433 case HNS_ROCE_V2_WQE_OP_BIND_MW:
3434 wc->opcode = IB_WC_REG_MR;
3435 break;
3436 default:
3437 wc->status = IB_WC_GENERAL_ERR;
3438 break;
3439 }
3440 } else {
3441 /* RQ correspond to CQE */
3442 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3443
3444 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
3445 V2_CQE_BYTE_4_OPCODE_S);
3446 switch (opcode & 0x1f) {
3447 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3448 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3449 wc->wc_flags = IB_WC_WITH_IMM;
3450 wc->ex.imm_data =
3451 cpu_to_be32(le32_to_cpu(cqe->immtdata));
3452 break;
3453 case HNS_ROCE_V2_OPCODE_SEND:
3454 wc->opcode = IB_WC_RECV;
3455 wc->wc_flags = 0;
3456 break;
3457 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3458 wc->opcode = IB_WC_RECV;
3459 wc->wc_flags = IB_WC_WITH_IMM;
3460 wc->ex.imm_data =
3461 cpu_to_be32(le32_to_cpu(cqe->immtdata));
3462 break;
3463 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3464 wc->opcode = IB_WC_RECV;
3465 wc->wc_flags = IB_WC_WITH_INVALIDATE;
3466 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
3467 break;
3468 default:
3469 wc->status = IB_WC_GENERAL_ERR;
3470 break;
3471 }
3472
3473 if ((wc->qp->qp_type == IB_QPT_RC ||
3474 wc->qp->qp_type == IB_QPT_UC) &&
3475 (opcode == HNS_ROCE_V2_OPCODE_SEND ||
3476 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
3477 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
3478 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) {
3479 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc);
3480 if (unlikely(ret))
3481 return -EAGAIN;
3482 }
3483
3484 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
3485 V2_CQE_BYTE_32_SL_S);
3486 wc->src_qp = (u8)roce_get_field(cqe->byte_32,
3487 V2_CQE_BYTE_32_RMT_QPN_M,
3488 V2_CQE_BYTE_32_RMT_QPN_S);
3489 wc->slid = 0;
3490 wc->wc_flags |= (roce_get_bit(cqe->byte_32,
3491 V2_CQE_BYTE_32_GRH_S) ?
3492 IB_WC_GRH : 0);
3493 wc->port_num = roce_get_field(cqe->byte_32,
3494 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S);
3495 wc->pkey_index = 0;
3496
3497 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) {
3498 wc->vlan_id = (u16)roce_get_field(cqe->byte_28,
3499 V2_CQE_BYTE_28_VID_M,
3500 V2_CQE_BYTE_28_VID_S);
3501 wc->wc_flags |= IB_WC_WITH_VLAN;
3502 } else {
3503 wc->vlan_id = 0xffff;
3504 }
3505
3506 wc->network_hdr_type = roce_get_field(cqe->byte_28,
3507 V2_CQE_BYTE_28_PORT_TYPE_M,
3508 V2_CQE_BYTE_28_PORT_TYPE_S);
3509 }
3510
3511 return 0;
3512 }
3513
hns_roce_v2_poll_cq(struct ib_cq * ibcq,int num_entries,struct ib_wc * wc)3514 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3515 struct ib_wc *wc)
3516 {
3517 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3518 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3519 struct hns_roce_qp *cur_qp = NULL;
3520 unsigned long flags;
3521 int npolled;
3522
3523 spin_lock_irqsave(&hr_cq->lock, flags);
3524
3525 /*
3526 * When the device starts to reset, the state is RST_DOWN. At this time,
3527 * there may still be some valid CQEs in the hardware that are not
3528 * polled. Therefore, it is not allowed to switch to the software mode
3529 * immediately. When the state changes to UNINIT, CQE no longer exists
3530 * in the hardware, and then switch to software mode.
3531 */
3532 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
3533 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
3534 goto out;
3535 }
3536
3537 for (npolled = 0; npolled < num_entries; ++npolled) {
3538 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
3539 break;
3540 }
3541
3542 if (npolled) {
3543 /* Memory barrier */
3544 wmb();
3545 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
3546 }
3547
3548 out:
3549 spin_unlock_irqrestore(&hr_cq->lock, flags);
3550
3551 return npolled;
3552 }
3553
get_op_for_set_hem(struct hns_roce_dev * hr_dev,u32 type,int step_idx)3554 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
3555 int step_idx)
3556 {
3557 int op;
3558
3559 if (type == HEM_TYPE_SCCC && step_idx)
3560 return -EINVAL;
3561
3562 switch (type) {
3563 case HEM_TYPE_QPC:
3564 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
3565 break;
3566 case HEM_TYPE_MTPT:
3567 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
3568 break;
3569 case HEM_TYPE_CQC:
3570 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
3571 break;
3572 case HEM_TYPE_SRQC:
3573 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
3574 break;
3575 case HEM_TYPE_SCCC:
3576 op = HNS_ROCE_CMD_WRITE_SCCC_BT0;
3577 break;
3578 case HEM_TYPE_QPC_TIMER:
3579 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
3580 break;
3581 case HEM_TYPE_CQC_TIMER:
3582 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
3583 break;
3584 default:
3585 dev_warn(hr_dev->dev,
3586 "table %u not to be written by mailbox!\n", type);
3587 return -EINVAL;
3588 }
3589
3590 return op + step_idx;
3591 }
3592
set_hem_to_hw(struct hns_roce_dev * hr_dev,int obj,u64 bt_ba,u32 hem_type,int step_idx)3593 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, u64 bt_ba,
3594 u32 hem_type, int step_idx)
3595 {
3596 struct hns_roce_cmd_mailbox *mailbox;
3597 int ret;
3598 int op;
3599
3600 op = get_op_for_set_hem(hr_dev, hem_type, step_idx);
3601 if (op < 0)
3602 return 0;
3603
3604 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3605 if (IS_ERR(mailbox))
3606 return PTR_ERR(mailbox);
3607
3608 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,
3609 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);
3610
3611 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3612
3613 return ret;
3614 }
3615
hns_roce_v2_set_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int obj,int step_idx)3616 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
3617 struct hns_roce_hem_table *table, int obj,
3618 int step_idx)
3619 {
3620 struct hns_roce_hem_iter iter;
3621 struct hns_roce_hem_mhop mhop;
3622 struct hns_roce_hem *hem;
3623 unsigned long mhop_obj = obj;
3624 int i, j, k;
3625 int ret = 0;
3626 u64 hem_idx = 0;
3627 u64 l1_idx = 0;
3628 u64 bt_ba = 0;
3629 u32 chunk_ba_num;
3630 u32 hop_num;
3631
3632 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
3633 return 0;
3634
3635 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
3636 i = mhop.l0_idx;
3637 j = mhop.l1_idx;
3638 k = mhop.l2_idx;
3639 hop_num = mhop.hop_num;
3640 chunk_ba_num = mhop.bt_chunk_size / 8;
3641
3642 if (hop_num == 2) {
3643 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
3644 k;
3645 l1_idx = i * chunk_ba_num + j;
3646 } else if (hop_num == 1) {
3647 hem_idx = i * chunk_ba_num + j;
3648 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
3649 hem_idx = i;
3650 }
3651
3652 if (table->type == HEM_TYPE_SCCC)
3653 obj = mhop.l0_idx;
3654
3655 if (check_whether_last_step(hop_num, step_idx)) {
3656 hem = table->hem[hem_idx];
3657 for (hns_roce_hem_first(hem, &iter);
3658 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
3659 bt_ba = hns_roce_hem_addr(&iter);
3660 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type,
3661 step_idx);
3662 }
3663 } else {
3664 if (step_idx == 0)
3665 bt_ba = table->bt_l0_dma_addr[i];
3666 else if (step_idx == 1 && hop_num == 2)
3667 bt_ba = table->bt_l1_dma_addr[l1_idx];
3668
3669 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx);
3670 }
3671
3672 return ret;
3673 }
3674
hns_roce_v2_clear_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int obj,int step_idx)3675 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
3676 struct hns_roce_hem_table *table, int obj,
3677 int step_idx)
3678 {
3679 struct device *dev = hr_dev->dev;
3680 struct hns_roce_cmd_mailbox *mailbox;
3681 int ret;
3682 u16 op = 0xff;
3683
3684 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
3685 return 0;
3686
3687 switch (table->type) {
3688 case HEM_TYPE_QPC:
3689 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
3690 break;
3691 case HEM_TYPE_MTPT:
3692 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
3693 break;
3694 case HEM_TYPE_CQC:
3695 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
3696 break;
3697 case HEM_TYPE_SCCC:
3698 case HEM_TYPE_QPC_TIMER:
3699 case HEM_TYPE_CQC_TIMER:
3700 break;
3701 case HEM_TYPE_SRQC:
3702 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
3703 break;
3704 default:
3705 dev_warn(dev, "table %u not to be destroyed by mailbox!\n",
3706 table->type);
3707 return 0;
3708 }
3709
3710 if (table->type == HEM_TYPE_SCCC ||
3711 table->type == HEM_TYPE_QPC_TIMER ||
3712 table->type == HEM_TYPE_CQC_TIMER)
3713 return 0;
3714
3715 op += step_idx;
3716
3717 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3718 if (IS_ERR(mailbox))
3719 return PTR_ERR(mailbox);
3720
3721 /* configure the tag and op */
3722 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
3723 HNS_ROCE_CMD_TIMEOUT_MSECS);
3724
3725 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3726 return ret;
3727 }
3728
hns_roce_v2_qp_modify(struct hns_roce_dev * hr_dev,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct hns_roce_qp * hr_qp)3729 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
3730 struct hns_roce_v2_qp_context *context,
3731 struct hns_roce_v2_qp_context *qpc_mask,
3732 struct hns_roce_qp *hr_qp)
3733 {
3734 struct hns_roce_cmd_mailbox *mailbox;
3735 int qpc_size;
3736 int ret;
3737
3738 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3739 if (IS_ERR(mailbox))
3740 return PTR_ERR(mailbox);
3741
3742 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */
3743 qpc_size = hr_dev->caps.qpc_sz;
3744 memcpy(mailbox->buf, context, qpc_size);
3745 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);
3746
3747 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
3748 HNS_ROCE_CMD_MODIFY_QPC,
3749 HNS_ROCE_CMD_TIMEOUT_MSECS);
3750
3751 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3752
3753 return ret;
3754 }
3755
set_access_flags(struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,const struct ib_qp_attr * attr,int attr_mask)3756 static void set_access_flags(struct hns_roce_qp *hr_qp,
3757 struct hns_roce_v2_qp_context *context,
3758 struct hns_roce_v2_qp_context *qpc_mask,
3759 const struct ib_qp_attr *attr, int attr_mask)
3760 {
3761 u8 dest_rd_atomic;
3762 u32 access_flags;
3763
3764 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
3765 attr->max_dest_rd_atomic : hr_qp->resp_depth;
3766
3767 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
3768 attr->qp_access_flags : hr_qp->atomic_rd_en;
3769
3770 if (!dest_rd_atomic)
3771 access_flags &= IB_ACCESS_REMOTE_WRITE;
3772
3773 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3774 !!(access_flags & IB_ACCESS_REMOTE_READ));
3775 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0);
3776
3777 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3778 !!(access_flags & IB_ACCESS_REMOTE_WRITE));
3779 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0);
3780
3781 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3782 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
3783 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0);
3784 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S,
3785 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
3786 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, 0);
3787 }
3788
set_qpc_wqe_cnt(struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)3789 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
3790 struct hns_roce_v2_qp_context *context,
3791 struct hns_roce_v2_qp_context *qpc_mask)
3792 {
3793 roce_set_field(context->byte_4_sqpn_tst,
3794 V2_QPC_BYTE_4_SGE_SHIFT_M, V2_QPC_BYTE_4_SGE_SHIFT_S,
3795 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt,
3796 hr_qp->sge.sge_shift));
3797
3798 roce_set_field(context->byte_20_smac_sgid_idx,
3799 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
3800 ilog2(hr_qp->sq.wqe_cnt));
3801
3802 roce_set_field(context->byte_20_smac_sgid_idx,
3803 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
3804 ilog2(hr_qp->rq.wqe_cnt));
3805 }
3806
modify_qp_reset_to_init(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)3807 static void modify_qp_reset_to_init(struct ib_qp *ibqp,
3808 const struct ib_qp_attr *attr,
3809 int attr_mask,
3810 struct hns_roce_v2_qp_context *context,
3811 struct hns_roce_v2_qp_context *qpc_mask)
3812 {
3813 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3814 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3815
3816 /*
3817 * In v2 engine, software pass context and context mask to hardware
3818 * when modifying qp. If software need modify some fields in context,
3819 * we should set all bits of the relevant fields in context mask to
3820 * 0 at the same time, else set them to 0x1.
3821 */
3822 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3823 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
3824
3825 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3826 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
3827
3828 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3829 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
3830
3831 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
3832 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs));
3833
3834 set_qpc_wqe_cnt(hr_qp, context, qpc_mask);
3835
3836 /* No VLAN need to set 0xFFF */
3837 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
3838 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff);
3839
3840 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
3841 roce_set_bit(context->byte_68_rq_db,
3842 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1);
3843
3844 roce_set_field(context->byte_68_rq_db,
3845 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
3846 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S,
3847 ((u32)hr_qp->rdb.dma) >> 1);
3848 context->rq_db_record_addr = cpu_to_le32(hr_qp->rdb.dma >> 32);
3849
3850 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
3851 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
3852
3853 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3854 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
3855 if (ibqp->srq) {
3856 roce_set_field(context->byte_76_srqn_op_en,
3857 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3858 to_hr_srq(ibqp->srq)->srqn);
3859 roce_set_bit(context->byte_76_srqn_op_en,
3860 V2_QPC_BYTE_76_SRQ_EN_S, 1);
3861 }
3862
3863 roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1);
3864
3865 hr_qp->access_flags = attr->qp_access_flags;
3866 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3867 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
3868 }
3869
modify_qp_init_to_init(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)3870 static void modify_qp_init_to_init(struct ib_qp *ibqp,
3871 const struct ib_qp_attr *attr, int attr_mask,
3872 struct hns_roce_v2_qp_context *context,
3873 struct hns_roce_v2_qp_context *qpc_mask)
3874 {
3875 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3876
3877 /*
3878 * In v2 engine, software pass context and context mask to hardware
3879 * when modifying qp. If software need modify some fields in context,
3880 * we should set all bits of the relevant fields in context mask to
3881 * 0 at the same time, else set them to 0x1.
3882 */
3883 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3884 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
3885 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3886 V2_QPC_BYTE_4_TST_S, 0);
3887
3888 if (attr_mask & IB_QP_ACCESS_FLAGS) {
3889 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3890 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
3891 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3892 0);
3893
3894 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3895 !!(attr->qp_access_flags &
3896 IB_ACCESS_REMOTE_WRITE));
3897 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3898 0);
3899
3900 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3901 !!(attr->qp_access_flags &
3902 IB_ACCESS_REMOTE_ATOMIC));
3903 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3904 0);
3905 roce_set_bit(context->byte_76_srqn_op_en,
3906 V2_QPC_BYTE_76_EXT_ATE_S,
3907 !!(attr->qp_access_flags &
3908 IB_ACCESS_REMOTE_ATOMIC));
3909 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3910 V2_QPC_BYTE_76_EXT_ATE_S, 0);
3911 } else {
3912 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3913 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ));
3914 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3915 0);
3916
3917 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3918 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE));
3919 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3920 0);
3921
3922 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3923 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
3924 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3925 0);
3926 roce_set_bit(context->byte_76_srqn_op_en,
3927 V2_QPC_BYTE_76_EXT_ATE_S,
3928 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
3929 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3930 V2_QPC_BYTE_76_EXT_ATE_S, 0);
3931 }
3932
3933 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3934 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
3935 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3936 V2_QPC_BYTE_16_PD_S, 0);
3937
3938 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3939 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
3940 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3941 V2_QPC_BYTE_80_RX_CQN_S, 0);
3942
3943 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3944 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
3945 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3946 V2_QPC_BYTE_252_TX_CQN_S, 0);
3947
3948 if (ibqp->srq) {
3949 roce_set_bit(context->byte_76_srqn_op_en,
3950 V2_QPC_BYTE_76_SRQ_EN_S, 1);
3951 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3952 V2_QPC_BYTE_76_SRQ_EN_S, 0);
3953 roce_set_field(context->byte_76_srqn_op_en,
3954 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3955 to_hr_srq(ibqp->srq)->srqn);
3956 roce_set_field(qpc_mask->byte_76_srqn_op_en,
3957 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
3958 }
3959
3960 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3961 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
3962 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3963 V2_QPC_BYTE_4_SQPN_S, 0);
3964
3965 if (attr_mask & IB_QP_DEST_QPN) {
3966 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3967 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn);
3968 roce_set_field(qpc_mask->byte_56_dqpn_err,
3969 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3970 }
3971 }
3972
config_qp_rq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)3973 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev,
3974 struct hns_roce_qp *hr_qp,
3975 struct hns_roce_v2_qp_context *context,
3976 struct hns_roce_v2_qp_context *qpc_mask)
3977 {
3978 u64 mtts[MTT_MIN_COUNT] = { 0 };
3979 u64 wqe_sge_ba;
3980 int count;
3981
3982 /* Search qp buf's mtts */
3983 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts,
3984 MTT_MIN_COUNT, &wqe_sge_ba);
3985 if (hr_qp->rq.wqe_cnt && count < 1) {
3986 ibdev_err(&hr_dev->ib_dev,
3987 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn);
3988 return -EINVAL;
3989 }
3990
3991 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
3992 qpc_mask->wqe_sge_ba = 0;
3993
3994 /*
3995 * In v2 engine, software pass context and context mask to hardware
3996 * when modifying qp. If software need modify some fields in context,
3997 * we should set all bits of the relevant fields in context mask to
3998 * 0 at the same time, else set them to 0x1.
3999 */
4000 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
4001 V2_QPC_BYTE_12_WQE_SGE_BA_S, wqe_sge_ba >> (32 + 3));
4002 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
4003 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0);
4004
4005 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
4006 V2_QPC_BYTE_12_SQ_HOP_NUM_S,
4007 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num,
4008 hr_qp->sq.wqe_cnt));
4009 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
4010 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0);
4011
4012 roce_set_field(context->byte_20_smac_sgid_idx,
4013 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
4014 V2_QPC_BYTE_20_SGE_HOP_NUM_S,
4015 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num,
4016 hr_qp->sge.sge_cnt));
4017 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
4018 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
4019 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0);
4020
4021 roce_set_field(context->byte_20_smac_sgid_idx,
4022 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
4023 V2_QPC_BYTE_20_RQ_HOP_NUM_S,
4024 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num,
4025 hr_qp->rq.wqe_cnt));
4026
4027 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
4028 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
4029 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0);
4030
4031 roce_set_field(context->byte_16_buf_ba_pg_sz,
4032 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
4033 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
4034 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
4035 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
4036 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
4037 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
4038
4039 roce_set_field(context->byte_16_buf_ba_pg_sz,
4040 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
4041 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
4042 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
4043 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
4044 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
4045 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
4046
4047 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
4048 qpc_mask->rq_cur_blk_addr = 0;
4049
4050 roce_set_field(context->byte_92_srq_info,
4051 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
4052 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S,
4053 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
4054 roce_set_field(qpc_mask->byte_92_srq_info,
4055 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
4056 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0);
4057
4058 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
4059 qpc_mask->rq_nxt_blk_addr = 0;
4060
4061 roce_set_field(context->byte_104_rq_sge,
4062 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
4063 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S,
4064 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
4065 roce_set_field(qpc_mask->byte_104_rq_sge,
4066 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
4067 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0);
4068
4069 roce_set_field(context->byte_84_rq_ci_pi,
4070 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
4071 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head);
4072 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
4073 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
4074 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
4075
4076 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
4077 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
4078 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
4079
4080 return 0;
4081 }
4082
config_qp_sq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4083 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev,
4084 struct hns_roce_qp *hr_qp,
4085 struct hns_roce_v2_qp_context *context,
4086 struct hns_roce_v2_qp_context *qpc_mask)
4087 {
4088 struct ib_device *ibdev = &hr_dev->ib_dev;
4089 u64 sge_cur_blk = 0;
4090 u64 sq_cur_blk = 0;
4091 int count;
4092
4093 /* search qp buf's mtts */
4094 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL);
4095 if (count < 1) {
4096 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n",
4097 hr_qp->qpn);
4098 return -EINVAL;
4099 }
4100 if (hr_qp->sge.sge_cnt > 0) {
4101 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
4102 hr_qp->sge.offset,
4103 &sge_cur_blk, 1, NULL);
4104 if (count < 1) {
4105 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n",
4106 hr_qp->qpn);
4107 return -EINVAL;
4108 }
4109 }
4110
4111 /*
4112 * In v2 engine, software pass context and context mask to hardware
4113 * when modifying qp. If software need modify some fields in context,
4114 * we should set all bits of the relevant fields in context mask to
4115 * 0 at the same time, else set them to 0x1.
4116 */
4117 context->sq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk));
4118 roce_set_field(context->byte_168_irrl_idx,
4119 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
4120 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S,
4121 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4122 qpc_mask->sq_cur_blk_addr = 0;
4123 roce_set_field(qpc_mask->byte_168_irrl_idx,
4124 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
4125 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);
4126
4127 context->sq_cur_sge_blk_addr =
4128 cpu_to_le32(to_hr_hw_page_addr(sge_cur_blk));
4129 roce_set_field(context->byte_184_irrl_idx,
4130 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
4131 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,
4132 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4133 qpc_mask->sq_cur_sge_blk_addr = 0;
4134 roce_set_field(qpc_mask->byte_184_irrl_idx,
4135 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
4136 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);
4137
4138 context->rx_sq_cur_blk_addr =
4139 cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk));
4140 roce_set_field(context->byte_232_irrl_sge,
4141 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
4142 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S,
4143 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4144 qpc_mask->rx_sq_cur_blk_addr = 0;
4145 roce_set_field(qpc_mask->byte_232_irrl_sge,
4146 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
4147 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0);
4148
4149 return 0;
4150 }
4151
get_mtu(struct ib_qp * ibqp,const struct ib_qp_attr * attr)4152 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp,
4153 const struct ib_qp_attr *attr)
4154 {
4155 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
4156 return IB_MTU_4096;
4157
4158 return attr->path_mtu;
4159 }
4160
modify_qp_init_to_rtr(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4161 static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
4162 const struct ib_qp_attr *attr, int attr_mask,
4163 struct hns_roce_v2_qp_context *context,
4164 struct hns_roce_v2_qp_context *qpc_mask)
4165 {
4166 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4167 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4168 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4169 struct ib_device *ibdev = &hr_dev->ib_dev;
4170 dma_addr_t trrl_ba;
4171 dma_addr_t irrl_ba;
4172 enum ib_mtu mtu;
4173 u8 lp_pktn_ini;
4174 u8 port_num;
4175 u64 *mtts;
4176 u8 *dmac;
4177 u8 *smac;
4178 int port;
4179 int ret;
4180
4181 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask);
4182 if (ret) {
4183 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret);
4184 return ret;
4185 }
4186
4187 /* Search IRRL's mtts */
4188 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
4189 hr_qp->qpn, &irrl_ba);
4190 if (!mtts) {
4191 ibdev_err(ibdev, "failed to find qp irrl_table.\n");
4192 return -EINVAL;
4193 }
4194
4195 /* Search TRRL's mtts */
4196 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
4197 hr_qp->qpn, &trrl_ba);
4198 if (!mtts) {
4199 ibdev_err(ibdev, "failed to find qp trrl_table.\n");
4200 return -EINVAL;
4201 }
4202
4203 if (attr_mask & IB_QP_ALT_PATH) {
4204 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n",
4205 attr_mask);
4206 return -EINVAL;
4207 }
4208
4209 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
4210 V2_QPC_BYTE_132_TRRL_BA_S, trrl_ba >> 4);
4211 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
4212 V2_QPC_BYTE_132_TRRL_BA_S, 0);
4213 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4));
4214 qpc_mask->trrl_ba = 0;
4215 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
4216 V2_QPC_BYTE_140_TRRL_BA_S,
4217 (u32)(trrl_ba >> (32 + 16 + 4)));
4218 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
4219 V2_QPC_BYTE_140_TRRL_BA_S, 0);
4220
4221 context->irrl_ba = cpu_to_le32(irrl_ba >> 6);
4222 qpc_mask->irrl_ba = 0;
4223 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
4224 V2_QPC_BYTE_208_IRRL_BA_S,
4225 irrl_ba >> (32 + 6));
4226 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
4227 V2_QPC_BYTE_208_IRRL_BA_S, 0);
4228
4229 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1);
4230 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0);
4231
4232 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
4233 hr_qp->sq_signal_bits);
4234 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
4235 0);
4236
4237 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
4238
4239 smac = (u8 *)hr_dev->dev_addr[port];
4240 dmac = (u8 *)attr->ah_attr.roce.dmac;
4241 /* when dmac equals smac or loop_idc is 1, it should loopback */
4242 if (ether_addr_equal_unaligned(dmac, smac) ||
4243 hr_dev->loop_idc == 0x1) {
4244 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1);
4245 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0);
4246 }
4247
4248 if (attr_mask & IB_QP_DEST_QPN) {
4249 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
4250 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num);
4251 roce_set_field(qpc_mask->byte_56_dqpn_err,
4252 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
4253 }
4254
4255 /* Configure GID index */
4256 port_num = rdma_ah_get_port_num(&attr->ah_attr);
4257 roce_set_field(context->byte_20_smac_sgid_idx,
4258 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S,
4259 hns_get_gid_index(hr_dev, port_num - 1,
4260 grh->sgid_index));
4261 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
4262 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0);
4263
4264 memcpy(&(context->dmac), dmac, sizeof(u32));
4265 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
4266 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
4267 qpc_mask->dmac = 0;
4268 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
4269 V2_QPC_BYTE_52_DMAC_S, 0);
4270
4271 mtu = get_mtu(ibqp, attr);
4272 hr_qp->path_mtu = mtu;
4273
4274 if (attr_mask & IB_QP_PATH_MTU) {
4275 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
4276 V2_QPC_BYTE_24_MTU_S, mtu);
4277 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
4278 V2_QPC_BYTE_24_MTU_S, 0);
4279 }
4280
4281 #define MAX_LP_MSG_LEN 65536
4282 /* MTU * (2 ^ LP_PKTN_INI) shouldn't be bigger than 64KB */
4283 lp_pktn_ini = ilog2(MAX_LP_MSG_LEN / ib_mtu_enum_to_int(mtu));
4284
4285 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
4286 V2_QPC_BYTE_56_LP_PKTN_INI_S, lp_pktn_ini);
4287 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
4288 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
4289
4290 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */
4291 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
4292 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, lp_pktn_ini);
4293 roce_set_field(qpc_mask->byte_172_sq_psn,
4294 V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
4295 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0);
4296
4297 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
4298 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
4299 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
4300 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
4301 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
4302 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
4303 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
4304
4305 context->rq_rnr_timer = 0;
4306 qpc_mask->rq_rnr_timer = 0;
4307
4308 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
4309 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
4310 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
4311 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
4312
4313 /* rocee send 2^lp_sgen_ini segs every time */
4314 roce_set_field(context->byte_168_irrl_idx,
4315 V2_QPC_BYTE_168_LP_SGEN_INI_M,
4316 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3);
4317 roce_set_field(qpc_mask->byte_168_irrl_idx,
4318 V2_QPC_BYTE_168_LP_SGEN_INI_M,
4319 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0);
4320
4321 return 0;
4322 }
4323
modify_qp_rtr_to_rts(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4324 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
4325 const struct ib_qp_attr *attr, int attr_mask,
4326 struct hns_roce_v2_qp_context *context,
4327 struct hns_roce_v2_qp_context *qpc_mask)
4328 {
4329 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4330 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4331 struct ib_device *ibdev = &hr_dev->ib_dev;
4332 int ret;
4333
4334 /* Not support alternate path and path migration */
4335 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
4336 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
4337 return -EINVAL;
4338 }
4339
4340 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask);
4341 if (ret) {
4342 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret);
4343 return ret;
4344 }
4345
4346 /*
4347 * Set some fields in context to zero, Because the default values
4348 * of all fields in context are zero, we need not set them to 0 again.
4349 * but we should set the relevant fields of context mask to 0.
4350 */
4351 roce_set_field(qpc_mask->byte_232_irrl_sge,
4352 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
4353 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
4354
4355 roce_set_field(qpc_mask->byte_240_irrl_tail,
4356 V2_QPC_BYTE_240_RX_ACK_MSN_M,
4357 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
4358
4359 roce_set_field(qpc_mask->byte_248_ack_psn,
4360 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
4361 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
4362 roce_set_bit(qpc_mask->byte_248_ack_psn,
4363 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0);
4364 roce_set_field(qpc_mask->byte_248_ack_psn,
4365 V2_QPC_BYTE_248_IRRL_PSN_M,
4366 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
4367
4368 roce_set_field(qpc_mask->byte_240_irrl_tail,
4369 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
4370 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
4371
4372 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
4373 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
4374 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
4375
4376 roce_set_bit(qpc_mask->byte_248_ack_psn,
4377 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
4378
4379 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
4380 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
4381
4382 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
4383 V2_QPC_BYTE_212_LSN_S, 0x100);
4384 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
4385 V2_QPC_BYTE_212_LSN_S, 0);
4386
4387 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
4388 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
4389
4390 return 0;
4391 }
4392
get_udp_sport(u32 fl,u32 lqpn,u32 rqpn)4393 static inline u16 get_udp_sport(u32 fl, u32 lqpn, u32 rqpn)
4394 {
4395 if (!fl)
4396 fl = rdma_calc_flow_label(lqpn, rqpn);
4397
4398 return rdma_flow_label_to_udp_sport(fl);
4399 }
4400
hns_roce_v2_set_path(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4401 static int hns_roce_v2_set_path(struct ib_qp *ibqp,
4402 const struct ib_qp_attr *attr,
4403 int attr_mask,
4404 struct hns_roce_v2_qp_context *context,
4405 struct hns_roce_v2_qp_context *qpc_mask)
4406 {
4407 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4408 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4409 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4410 struct ib_device *ibdev = &hr_dev->ib_dev;
4411 const struct ib_gid_attr *gid_attr = NULL;
4412 int is_roce_protocol;
4413 u16 vlan_id = 0xffff;
4414 bool is_udp = false;
4415 u8 ib_port;
4416 u8 hr_port;
4417 int ret;
4418
4419 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
4420 hr_port = ib_port - 1;
4421 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
4422 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
4423
4424 if (is_roce_protocol) {
4425 gid_attr = attr->ah_attr.grh.sgid_attr;
4426 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
4427 if (ret)
4428 return ret;
4429
4430 if (gid_attr)
4431 is_udp = (gid_attr->gid_type ==
4432 IB_GID_TYPE_ROCE_UDP_ENCAP);
4433 }
4434
4435 if (vlan_id < VLAN_N_VID) {
4436 roce_set_bit(context->byte_76_srqn_op_en,
4437 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1);
4438 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
4439 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0);
4440 roce_set_bit(context->byte_168_irrl_idx,
4441 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1);
4442 roce_set_bit(qpc_mask->byte_168_irrl_idx,
4443 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0);
4444 }
4445
4446 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
4447 V2_QPC_BYTE_24_VLAN_ID_S, vlan_id);
4448 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
4449 V2_QPC_BYTE_24_VLAN_ID_S, 0);
4450
4451 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
4452 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
4453 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
4454 return -EINVAL;
4455 }
4456
4457 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
4458 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
4459 return -EINVAL;
4460 }
4461
4462 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M,
4463 V2_QPC_BYTE_52_UDPSPN_S,
4464 is_udp ? get_udp_sport(grh->flow_label, ibqp->qp_num,
4465 attr->dest_qp_num) : 0);
4466
4467 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M,
4468 V2_QPC_BYTE_52_UDPSPN_S, 0);
4469
4470 roce_set_field(context->byte_20_smac_sgid_idx,
4471 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S,
4472 grh->sgid_index);
4473
4474 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
4475 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0);
4476
4477 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
4478 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit);
4479 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
4480 V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
4481
4482 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4483 V2_QPC_BYTE_24_TC_S, get_tclass(&attr->ah_attr.grh));
4484 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4485 V2_QPC_BYTE_24_TC_S, 0);
4486
4487 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
4488 V2_QPC_BYTE_28_FL_S, grh->flow_label);
4489 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
4490 V2_QPC_BYTE_28_FL_S, 0);
4491 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4492 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
4493
4494 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
4495 if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) {
4496 ibdev_err(ibdev,
4497 "failed to fill QPC, sl (%d) shouldn't be larger than %d.\n",
4498 hr_qp->sl, MAX_SERVICE_LEVEL);
4499 return -EINVAL;
4500 }
4501
4502 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
4503 V2_QPC_BYTE_28_SL_S, hr_qp->sl);
4504 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
4505 V2_QPC_BYTE_28_SL_S, 0);
4506
4507 return 0;
4508 }
4509
check_qp_state(enum ib_qp_state cur_state,enum ib_qp_state new_state)4510 static bool check_qp_state(enum ib_qp_state cur_state,
4511 enum ib_qp_state new_state)
4512 {
4513 static const bool sm[][IB_QPS_ERR + 1] = {
4514 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
4515 [IB_QPS_INIT] = true },
4516 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
4517 [IB_QPS_INIT] = true,
4518 [IB_QPS_RTR] = true,
4519 [IB_QPS_ERR] = true },
4520 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
4521 [IB_QPS_RTS] = true,
4522 [IB_QPS_ERR] = true },
4523 [IB_QPS_RTS] = { [IB_QPS_RESET] = true,
4524 [IB_QPS_RTS] = true,
4525 [IB_QPS_ERR] = true },
4526 [IB_QPS_SQD] = {},
4527 [IB_QPS_SQE] = {},
4528 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }
4529 };
4530
4531 return sm[cur_state][new_state];
4532 }
4533
hns_roce_v2_set_abs_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4534 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
4535 const struct ib_qp_attr *attr,
4536 int attr_mask,
4537 enum ib_qp_state cur_state,
4538 enum ib_qp_state new_state,
4539 struct hns_roce_v2_qp_context *context,
4540 struct hns_roce_v2_qp_context *qpc_mask)
4541 {
4542 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4543 int ret = 0;
4544
4545 if (!check_qp_state(cur_state, new_state)) {
4546 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n");
4547 return -EINVAL;
4548 }
4549
4550 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4551 memset(qpc_mask, 0, hr_dev->caps.qpc_sz);
4552 modify_qp_reset_to_init(ibqp, attr, attr_mask, context,
4553 qpc_mask);
4554 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4555 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
4556 qpc_mask);
4557 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4558 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
4559 qpc_mask);
4560 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4561 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
4562 qpc_mask);
4563 }
4564
4565 return ret;
4566 }
4567
hns_roce_v2_set_opt_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4568 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
4569 const struct ib_qp_attr *attr,
4570 int attr_mask,
4571 struct hns_roce_v2_qp_context *context,
4572 struct hns_roce_v2_qp_context *qpc_mask)
4573 {
4574 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4575 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4576 int ret = 0;
4577
4578 if (attr_mask & IB_QP_AV) {
4579 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
4580 qpc_mask);
4581 if (ret)
4582 return ret;
4583 }
4584
4585 if (attr_mask & IB_QP_TIMEOUT) {
4586 if (attr->timeout < 31) {
4587 roce_set_field(context->byte_28_at_fl,
4588 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S,
4589 attr->timeout);
4590 roce_set_field(qpc_mask->byte_28_at_fl,
4591 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S,
4592 0);
4593 } else {
4594 ibdev_warn(&hr_dev->ib_dev,
4595 "Local ACK timeout shall be 0 to 30.\n");
4596 }
4597 }
4598
4599 if (attr_mask & IB_QP_RETRY_CNT) {
4600 roce_set_field(context->byte_212_lsn,
4601 V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
4602 V2_QPC_BYTE_212_RETRY_NUM_INIT_S,
4603 attr->retry_cnt);
4604 roce_set_field(qpc_mask->byte_212_lsn,
4605 V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
4606 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0);
4607
4608 roce_set_field(context->byte_212_lsn,
4609 V2_QPC_BYTE_212_RETRY_CNT_M,
4610 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt);
4611 roce_set_field(qpc_mask->byte_212_lsn,
4612 V2_QPC_BYTE_212_RETRY_CNT_M,
4613 V2_QPC_BYTE_212_RETRY_CNT_S, 0);
4614 }
4615
4616 if (attr_mask & IB_QP_RNR_RETRY) {
4617 roce_set_field(context->byte_244_rnr_rxack,
4618 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
4619 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry);
4620 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4621 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
4622 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0);
4623
4624 roce_set_field(context->byte_244_rnr_rxack,
4625 V2_QPC_BYTE_244_RNR_CNT_M,
4626 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry);
4627 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4628 V2_QPC_BYTE_244_RNR_CNT_M,
4629 V2_QPC_BYTE_244_RNR_CNT_S, 0);
4630 }
4631
4632 /* RC&UC&UD required attr */
4633 if (attr_mask & IB_QP_SQ_PSN) {
4634 roce_set_field(context->byte_172_sq_psn,
4635 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4636 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn);
4637 roce_set_field(qpc_mask->byte_172_sq_psn,
4638 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4639 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0);
4640
4641 roce_set_field(context->byte_196_sq_psn,
4642 V2_QPC_BYTE_196_SQ_MAX_PSN_M,
4643 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn);
4644 roce_set_field(qpc_mask->byte_196_sq_psn,
4645 V2_QPC_BYTE_196_SQ_MAX_PSN_M,
4646 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0);
4647
4648 roce_set_field(context->byte_220_retry_psn_msn,
4649 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
4650 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn);
4651 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
4652 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
4653 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0);
4654
4655 roce_set_field(context->byte_224_retry_msg,
4656 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
4657 V2_QPC_BYTE_224_RETRY_MSG_PSN_S,
4658 attr->sq_psn >> V2_QPC_BYTE_220_RETRY_MSG_PSN_S);
4659 roce_set_field(qpc_mask->byte_224_retry_msg,
4660 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
4661 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0);
4662
4663 roce_set_field(context->byte_224_retry_msg,
4664 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
4665 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S,
4666 attr->sq_psn);
4667 roce_set_field(qpc_mask->byte_224_retry_msg,
4668 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
4669 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0);
4670
4671 roce_set_field(context->byte_244_rnr_rxack,
4672 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
4673 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn);
4674 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4675 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
4676 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0);
4677 }
4678
4679 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
4680 attr->max_dest_rd_atomic) {
4681 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
4682 V2_QPC_BYTE_140_RR_MAX_S,
4683 fls(attr->max_dest_rd_atomic - 1));
4684 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
4685 V2_QPC_BYTE_140_RR_MAX_S, 0);
4686 }
4687
4688 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
4689 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
4690 V2_QPC_BYTE_208_SR_MAX_S,
4691 fls(attr->max_rd_atomic - 1));
4692 roce_set_field(qpc_mask->byte_208_irrl,
4693 V2_QPC_BYTE_208_SR_MAX_M,
4694 V2_QPC_BYTE_208_SR_MAX_S, 0);
4695 }
4696
4697 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
4698 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
4699
4700 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
4701 roce_set_field(context->byte_80_rnr_rx_cqn,
4702 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4703 V2_QPC_BYTE_80_MIN_RNR_TIME_S,
4704 attr->min_rnr_timer);
4705 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn,
4706 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4707 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0);
4708 }
4709
4710 /* RC&UC required attr */
4711 if (attr_mask & IB_QP_RQ_PSN) {
4712 roce_set_field(context->byte_108_rx_reqepsn,
4713 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4714 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn);
4715 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
4716 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4717 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);
4718
4719 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
4720 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1);
4721 roce_set_field(qpc_mask->byte_152_raq,
4722 V2_QPC_BYTE_152_RAQ_PSN_M,
4723 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
4724 }
4725
4726 if (attr_mask & IB_QP_QKEY) {
4727 context->qkey_xrcd = cpu_to_le32(attr->qkey);
4728 qpc_mask->qkey_xrcd = 0;
4729 hr_qp->qkey = attr->qkey;
4730 }
4731
4732 return ret;
4733 }
4734
hns_roce_v2_record_opt_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask)4735 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
4736 const struct ib_qp_attr *attr,
4737 int attr_mask)
4738 {
4739 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4740 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4741
4742 if (attr_mask & IB_QP_ACCESS_FLAGS)
4743 hr_qp->atomic_rd_en = attr->qp_access_flags;
4744
4745 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
4746 hr_qp->resp_depth = attr->max_dest_rd_atomic;
4747 if (attr_mask & IB_QP_PORT) {
4748 hr_qp->port = attr->port_num - 1;
4749 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
4750 }
4751 }
4752
hns_roce_v2_modify_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state)4753 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
4754 const struct ib_qp_attr *attr,
4755 int attr_mask, enum ib_qp_state cur_state,
4756 enum ib_qp_state new_state)
4757 {
4758 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4759 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4760 struct hns_roce_v2_qp_context ctx[2];
4761 struct hns_roce_v2_qp_context *context = ctx;
4762 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1;
4763 struct ib_device *ibdev = &hr_dev->ib_dev;
4764 unsigned long sq_flag = 0;
4765 unsigned long rq_flag = 0;
4766 int ret;
4767
4768 /*
4769 * In v2 engine, software pass context and context mask to hardware
4770 * when modifying qp. If software need modify some fields in context,
4771 * we should set all bits of the relevant fields in context mask to
4772 * 0 at the same time, else set them to 0x1.
4773 */
4774 memset(context, 0, hr_dev->caps.qpc_sz);
4775 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz);
4776
4777 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
4778 new_state, context, qpc_mask);
4779 if (ret)
4780 goto out;
4781
4782 /* When QP state is err, SQ and RQ WQE should be flushed */
4783 if (new_state == IB_QPS_ERR) {
4784 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
4785 hr_qp->state = IB_QPS_ERR;
4786 roce_set_field(context->byte_160_sq_ci_pi,
4787 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
4788 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S,
4789 hr_qp->sq.head);
4790 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
4791 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
4792 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
4793 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
4794
4795 if (!ibqp->srq) {
4796 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
4797 roce_set_field(context->byte_84_rq_ci_pi,
4798 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
4799 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S,
4800 hr_qp->rq.head);
4801 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
4802 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
4803 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
4804 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
4805 }
4806 }
4807
4808 /* Configure the optional fields */
4809 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
4810 qpc_mask);
4811 if (ret)
4812 goto out;
4813
4814 roce_set_bit(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S,
4815 ibqp->srq ? 1 : 0);
4816 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
4817 V2_QPC_BYTE_108_INV_CREDIT_S, 0);
4818
4819 /* Every status migrate must change state */
4820 roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
4821 V2_QPC_BYTE_60_QP_ST_S, new_state);
4822 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
4823 V2_QPC_BYTE_60_QP_ST_S, 0);
4824
4825 /* SW pass context to HW */
4826 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp);
4827 if (ret) {
4828 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret);
4829 goto out;
4830 }
4831
4832 hr_qp->state = new_state;
4833
4834 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
4835
4836 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
4837 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
4838 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
4839 if (ibqp->send_cq != ibqp->recv_cq)
4840 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
4841 hr_qp->qpn, NULL);
4842
4843 hr_qp->rq.head = 0;
4844 hr_qp->rq.tail = 0;
4845 hr_qp->sq.head = 0;
4846 hr_qp->sq.tail = 0;
4847 hr_qp->next_sge = 0;
4848 if (hr_qp->rq.wqe_cnt)
4849 *hr_qp->rdb.db_record = 0;
4850 }
4851
4852 out:
4853 return ret;
4854 }
4855
to_ib_qp_st(enum hns_roce_v2_qp_state state)4856 static int to_ib_qp_st(enum hns_roce_v2_qp_state state)
4857 {
4858 static const enum ib_qp_state map[] = {
4859 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET,
4860 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT,
4861 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR,
4862 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS,
4863 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD,
4864 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE,
4865 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR,
4866 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD
4867 };
4868
4869 return (state < ARRAY_SIZE(map)) ? map[state] : -1;
4870 }
4871
hns_roce_v2_query_qpc(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * hr_context)4872 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
4873 struct hns_roce_qp *hr_qp,
4874 struct hns_roce_v2_qp_context *hr_context)
4875 {
4876 struct hns_roce_cmd_mailbox *mailbox;
4877 int ret;
4878
4879 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4880 if (IS_ERR(mailbox))
4881 return PTR_ERR(mailbox);
4882
4883 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
4884 HNS_ROCE_CMD_QUERY_QPC,
4885 HNS_ROCE_CMD_TIMEOUT_MSECS);
4886 if (ret)
4887 goto out;
4888
4889 memcpy(hr_context, mailbox->buf, hr_dev->caps.qpc_sz);
4890
4891 out:
4892 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4893 return ret;
4894 }
4895
hns_roce_v2_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)4896 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4897 int qp_attr_mask,
4898 struct ib_qp_init_attr *qp_init_attr)
4899 {
4900 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4901 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4902 struct hns_roce_v2_qp_context context = {};
4903 struct ib_device *ibdev = &hr_dev->ib_dev;
4904 int tmp_qp_state;
4905 int state;
4906 int ret;
4907
4908 memset(qp_attr, 0, sizeof(*qp_attr));
4909 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4910
4911 mutex_lock(&hr_qp->mutex);
4912
4913 if (hr_qp->state == IB_QPS_RESET) {
4914 qp_attr->qp_state = IB_QPS_RESET;
4915 ret = 0;
4916 goto done;
4917 }
4918
4919 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context);
4920 if (ret) {
4921 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret);
4922 ret = -EINVAL;
4923 goto out;
4924 }
4925
4926 state = roce_get_field(context.byte_60_qpst_tempid,
4927 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
4928 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
4929 if (tmp_qp_state == -1) {
4930 ibdev_err(ibdev, "Illegal ib_qp_state\n");
4931 ret = -EINVAL;
4932 goto out;
4933 }
4934 hr_qp->state = (u8)tmp_qp_state;
4935 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
4936 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context.byte_24_mtu_tc,
4937 V2_QPC_BYTE_24_MTU_M,
4938 V2_QPC_BYTE_24_MTU_S);
4939 qp_attr->path_mig_state = IB_MIG_ARMED;
4940 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
4941 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
4942 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd);
4943
4944 qp_attr->rq_psn = roce_get_field(context.byte_108_rx_reqepsn,
4945 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4946 V2_QPC_BYTE_108_RX_REQ_EPSN_S);
4947 qp_attr->sq_psn = (u32)roce_get_field(context.byte_172_sq_psn,
4948 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4949 V2_QPC_BYTE_172_SQ_CUR_PSN_S);
4950 qp_attr->dest_qp_num = (u8)roce_get_field(context.byte_56_dqpn_err,
4951 V2_QPC_BYTE_56_DQPN_M,
4952 V2_QPC_BYTE_56_DQPN_S);
4953 qp_attr->qp_access_flags = ((roce_get_bit(context.byte_76_srqn_op_en,
4954 V2_QPC_BYTE_76_RRE_S)) << V2_QP_RRE_S) |
4955 ((roce_get_bit(context.byte_76_srqn_op_en,
4956 V2_QPC_BYTE_76_RWE_S)) << V2_QP_RWE_S) |
4957 ((roce_get_bit(context.byte_76_srqn_op_en,
4958 V2_QPC_BYTE_76_ATE_S)) << V2_QP_ATE_S);
4959
4960 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
4961 hr_qp->ibqp.qp_type == IB_QPT_UC) {
4962 struct ib_global_route *grh =
4963 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
4964
4965 rdma_ah_set_sl(&qp_attr->ah_attr,
4966 roce_get_field(context.byte_28_at_fl,
4967 V2_QPC_BYTE_28_SL_M,
4968 V2_QPC_BYTE_28_SL_S));
4969 grh->flow_label = roce_get_field(context.byte_28_at_fl,
4970 V2_QPC_BYTE_28_FL_M,
4971 V2_QPC_BYTE_28_FL_S);
4972 grh->sgid_index = roce_get_field(context.byte_20_smac_sgid_idx,
4973 V2_QPC_BYTE_20_SGID_IDX_M,
4974 V2_QPC_BYTE_20_SGID_IDX_S);
4975 grh->hop_limit = roce_get_field(context.byte_24_mtu_tc,
4976 V2_QPC_BYTE_24_HOP_LIMIT_M,
4977 V2_QPC_BYTE_24_HOP_LIMIT_S);
4978 grh->traffic_class = roce_get_field(context.byte_24_mtu_tc,
4979 V2_QPC_BYTE_24_TC_M,
4980 V2_QPC_BYTE_24_TC_S);
4981
4982 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
4983 }
4984
4985 qp_attr->port_num = hr_qp->port + 1;
4986 qp_attr->sq_draining = 0;
4987 qp_attr->max_rd_atomic = 1 << roce_get_field(context.byte_208_irrl,
4988 V2_QPC_BYTE_208_SR_MAX_M,
4989 V2_QPC_BYTE_208_SR_MAX_S);
4990 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context.byte_140_raq,
4991 V2_QPC_BYTE_140_RR_MAX_M,
4992 V2_QPC_BYTE_140_RR_MAX_S);
4993 qp_attr->min_rnr_timer = (u8)roce_get_field(context.byte_80_rnr_rx_cqn,
4994 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4995 V2_QPC_BYTE_80_MIN_RNR_TIME_S);
4996 qp_attr->timeout = (u8)roce_get_field(context.byte_28_at_fl,
4997 V2_QPC_BYTE_28_AT_M,
4998 V2_QPC_BYTE_28_AT_S);
4999 qp_attr->retry_cnt = roce_get_field(context.byte_212_lsn,
5000 V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
5001 V2_QPC_BYTE_212_RETRY_NUM_INIT_S);
5002 qp_attr->rnr_retry = roce_get_field(context.byte_244_rnr_rxack,
5003 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
5004 V2_QPC_BYTE_244_RNR_NUM_INIT_S);
5005
5006 done:
5007 qp_attr->cur_qp_state = qp_attr->qp_state;
5008 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
5009 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
5010
5011 if (!ibqp->uobject) {
5012 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
5013 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
5014 } else {
5015 qp_attr->cap.max_send_wr = 0;
5016 qp_attr->cap.max_send_sge = 0;
5017 }
5018
5019 qp_init_attr->cap = qp_attr->cap;
5020 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits;
5021
5022 out:
5023 mutex_unlock(&hr_qp->mutex);
5024 return ret;
5025 }
5026
hns_roce_v2_destroy_qp_common(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct ib_udata * udata)5027 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
5028 struct hns_roce_qp *hr_qp,
5029 struct ib_udata *udata)
5030 {
5031 struct ib_device *ibdev = &hr_dev->ib_dev;
5032 struct hns_roce_cq *send_cq, *recv_cq;
5033 unsigned long flags;
5034 int ret = 0;
5035
5036 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
5037 /* Modify qp to reset before destroying qp */
5038 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
5039 hr_qp->state, IB_QPS_RESET);
5040 if (ret)
5041 ibdev_err(ibdev,
5042 "failed to modify QP to RST, ret = %d.\n",
5043 ret);
5044 }
5045
5046 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
5047 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
5048
5049 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
5050 hns_roce_lock_cqs(send_cq, recv_cq);
5051
5052 if (!udata) {
5053 if (recv_cq)
5054 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
5055 (hr_qp->ibqp.srq ?
5056 to_hr_srq(hr_qp->ibqp.srq) :
5057 NULL));
5058
5059 if (send_cq && send_cq != recv_cq)
5060 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
5061
5062 }
5063
5064 hns_roce_qp_remove(hr_dev, hr_qp);
5065
5066 hns_roce_unlock_cqs(send_cq, recv_cq);
5067 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
5068
5069 return ret;
5070 }
5071
hns_roce_v2_destroy_qp(struct ib_qp * ibqp,struct ib_udata * udata)5072 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
5073 {
5074 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5075 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5076 int ret;
5077
5078 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
5079 if (ret)
5080 ibdev_err(&hr_dev->ib_dev,
5081 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n",
5082 hr_qp->qpn, ret);
5083
5084 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
5085
5086 return 0;
5087 }
5088
hns_roce_v2_qp_flow_control_init(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)5089 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
5090 struct hns_roce_qp *hr_qp)
5091 {
5092 struct ib_device *ibdev = &hr_dev->ib_dev;
5093 struct hns_roce_sccc_clr_done *resp;
5094 struct hns_roce_sccc_clr *clr;
5095 struct hns_roce_cmq_desc desc;
5096 int ret, i;
5097
5098 mutex_lock(&hr_dev->qp_table.scc_mutex);
5099
5100 /* set scc ctx clear done flag */
5101 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
5102 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5103 if (ret) {
5104 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret);
5105 goto out;
5106 }
5107
5108 /* clear scc context */
5109 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
5110 clr = (struct hns_roce_sccc_clr *)desc.data;
5111 clr->qpn = cpu_to_le32(hr_qp->qpn);
5112 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5113 if (ret) {
5114 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret);
5115 goto out;
5116 }
5117
5118 /* query scc context clear is done or not */
5119 resp = (struct hns_roce_sccc_clr_done *)desc.data;
5120 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
5121 hns_roce_cmq_setup_basic_desc(&desc,
5122 HNS_ROCE_OPC_QUERY_SCCC, true);
5123 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5124 if (ret) {
5125 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
5126 ret);
5127 goto out;
5128 }
5129
5130 if (resp->clr_done)
5131 goto out;
5132
5133 msleep(20);
5134 }
5135
5136 ibdev_err(ibdev, "Query SCC clr done flag overtime.\n");
5137 ret = -ETIMEDOUT;
5138
5139 out:
5140 mutex_unlock(&hr_dev->qp_table.scc_mutex);
5141 return ret;
5142 }
5143
hns_roce_v2_write_srqc(struct hns_roce_dev * hr_dev,struct hns_roce_srq * srq,u32 pdn,u16 xrcd,u32 cqn,void * mb_buf,u64 * mtts_wqe,u64 * mtts_idx,dma_addr_t dma_handle_wqe,dma_addr_t dma_handle_idx)5144 static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev,
5145 struct hns_roce_srq *srq, u32 pdn, u16 xrcd,
5146 u32 cqn, void *mb_buf, u64 *mtts_wqe,
5147 u64 *mtts_idx, dma_addr_t dma_handle_wqe,
5148 dma_addr_t dma_handle_idx)
5149 {
5150 struct hns_roce_srq_context *srq_context;
5151
5152 srq_context = mb_buf;
5153 memset(srq_context, 0, sizeof(*srq_context));
5154
5155 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQ_ST_M,
5156 SRQC_BYTE_4_SRQ_ST_S, 1);
5157
5158 roce_set_field(srq_context->byte_4_srqn_srqst,
5159 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M,
5160 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S,
5161 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num,
5162 srq->wqe_cnt));
5163 roce_set_field(srq_context->byte_4_srqn_srqst,
5164 SRQC_BYTE_4_SRQ_SHIFT_M, SRQC_BYTE_4_SRQ_SHIFT_S,
5165 ilog2(srq->wqe_cnt));
5166
5167 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQN_M,
5168 SRQC_BYTE_4_SRQN_S, srq->srqn);
5169
5170 roce_set_field(srq_context->byte_8_limit_wl, SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5171 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);
5172
5173 roce_set_field(srq_context->byte_12_xrcd, SRQC_BYTE_12_SRQ_XRCD_M,
5174 SRQC_BYTE_12_SRQ_XRCD_S, xrcd);
5175
5176 srq_context->wqe_bt_ba = cpu_to_le32((u32)(dma_handle_wqe >> 3));
5177
5178 roce_set_field(srq_context->byte_24_wqe_bt_ba,
5179 SRQC_BYTE_24_SRQ_WQE_BT_BA_M,
5180 SRQC_BYTE_24_SRQ_WQE_BT_BA_S,
5181 dma_handle_wqe >> 35);
5182
5183 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_PD_M,
5184 SRQC_BYTE_28_PD_S, pdn);
5185 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_RQWS_M,
5186 SRQC_BYTE_28_RQWS_S, srq->max_gs <= 0 ? 0 :
5187 fls(srq->max_gs - 1));
5188
5189 srq_context->idx_bt_ba = cpu_to_le32(dma_handle_idx >> 3);
5190 roce_set_field(srq_context->rsv_idx_bt_ba,
5191 SRQC_BYTE_36_SRQ_IDX_BT_BA_M,
5192 SRQC_BYTE_36_SRQ_IDX_BT_BA_S,
5193 dma_handle_idx >> 35);
5194
5195 srq_context->idx_cur_blk_addr =
5196 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[0]));
5197 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5198 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M,
5199 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S,
5200 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
5201 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5202 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M,
5203 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S,
5204 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num,
5205 srq->wqe_cnt));
5206
5207 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5208 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M,
5209 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S,
5210 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.ba_pg_shift));
5211 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5212 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M,
5213 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S,
5214 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.buf_pg_shift));
5215
5216 srq_context->idx_nxt_blk_addr =
5217 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[1]));
5218 roce_set_field(srq_context->rsv_idxnxtblkaddr,
5219 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M,
5220 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S,
5221 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
5222 roce_set_field(srq_context->byte_56_xrc_cqn,
5223 SRQC_BYTE_56_SRQ_XRC_CQN_M, SRQC_BYTE_56_SRQ_XRC_CQN_S,
5224 cqn);
5225 roce_set_field(srq_context->byte_56_xrc_cqn,
5226 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M,
5227 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S,
5228 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
5229 roce_set_field(srq_context->byte_56_xrc_cqn,
5230 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M,
5231 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S,
5232 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
5233
5234 roce_set_bit(srq_context->db_record_addr_record_en,
5235 SRQC_BYTE_60_SRQ_RECORD_EN_S, 0);
5236 }
5237
hns_roce_v2_modify_srq(struct ib_srq * ibsrq,struct ib_srq_attr * srq_attr,enum ib_srq_attr_mask srq_attr_mask,struct ib_udata * udata)5238 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5239 struct ib_srq_attr *srq_attr,
5240 enum ib_srq_attr_mask srq_attr_mask,
5241 struct ib_udata *udata)
5242 {
5243 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5244 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5245 struct hns_roce_srq_context *srq_context;
5246 struct hns_roce_srq_context *srqc_mask;
5247 struct hns_roce_cmd_mailbox *mailbox;
5248 int ret;
5249
5250 /* Resizing SRQs is not supported yet */
5251 if (srq_attr_mask & IB_SRQ_MAX_WR)
5252 return -EINVAL;
5253
5254 if (srq_attr_mask & IB_SRQ_LIMIT) {
5255 if (srq_attr->srq_limit >= srq->wqe_cnt)
5256 return -EINVAL;
5257
5258 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5259 if (IS_ERR(mailbox))
5260 return PTR_ERR(mailbox);
5261
5262 srq_context = mailbox->buf;
5263 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5264
5265 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5266
5267 roce_set_field(srq_context->byte_8_limit_wl,
5268 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5269 SRQC_BYTE_8_SRQ_LIMIT_WL_S, srq_attr->srq_limit);
5270 roce_set_field(srqc_mask->byte_8_limit_wl,
5271 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5272 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);
5273
5274 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0,
5275 HNS_ROCE_CMD_MODIFY_SRQC,
5276 HNS_ROCE_CMD_TIMEOUT_MSECS);
5277 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5278 if (ret) {
5279 ibdev_err(&hr_dev->ib_dev,
5280 "failed to handle cmd of modifying SRQ, ret = %d.\n",
5281 ret);
5282 return ret;
5283 }
5284 }
5285
5286 return 0;
5287 }
5288
hns_roce_v2_query_srq(struct ib_srq * ibsrq,struct ib_srq_attr * attr)5289 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
5290 {
5291 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5292 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5293 struct hns_roce_srq_context *srq_context;
5294 struct hns_roce_cmd_mailbox *mailbox;
5295 int limit_wl;
5296 int ret;
5297
5298 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5299 if (IS_ERR(mailbox))
5300 return PTR_ERR(mailbox);
5301
5302 srq_context = mailbox->buf;
5303 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0,
5304 HNS_ROCE_CMD_QUERY_SRQC,
5305 HNS_ROCE_CMD_TIMEOUT_MSECS);
5306 if (ret) {
5307 ibdev_err(&hr_dev->ib_dev,
5308 "failed to process cmd of querying SRQ, ret = %d.\n",
5309 ret);
5310 goto out;
5311 }
5312
5313 limit_wl = roce_get_field(srq_context->byte_8_limit_wl,
5314 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5315 SRQC_BYTE_8_SRQ_LIMIT_WL_S);
5316
5317 attr->srq_limit = limit_wl;
5318 attr->max_wr = srq->wqe_cnt - 1;
5319 attr->max_sge = srq->max_gs;
5320
5321 out:
5322 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5323 return ret;
5324 }
5325
hns_roce_v2_modify_cq(struct ib_cq * cq,u16 cq_count,u16 cq_period)5326 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
5327 {
5328 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
5329 struct hns_roce_v2_cq_context *cq_context;
5330 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
5331 struct hns_roce_v2_cq_context *cqc_mask;
5332 struct hns_roce_cmd_mailbox *mailbox;
5333 int ret;
5334
5335 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5336 if (IS_ERR(mailbox))
5337 return PTR_ERR(mailbox);
5338
5339 cq_context = mailbox->buf;
5340 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
5341
5342 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
5343
5344 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
5345 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
5346 cq_count);
5347 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
5348 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
5349 0);
5350 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
5351 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
5352 cq_period);
5353 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
5354 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
5355 0);
5356
5357 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
5358 HNS_ROCE_CMD_MODIFY_CQC,
5359 HNS_ROCE_CMD_TIMEOUT_MSECS);
5360 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5361 if (ret)
5362 ibdev_err(&hr_dev->ib_dev,
5363 "failed to process cmd when modifying CQ, ret = %d.\n",
5364 ret);
5365
5366 return ret;
5367 }
5368
hns_roce_irq_work_handle(struct work_struct * work)5369 static void hns_roce_irq_work_handle(struct work_struct *work)
5370 {
5371 struct hns_roce_work *irq_work =
5372 container_of(work, struct hns_roce_work, work);
5373 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev;
5374 u32 qpn = irq_work->qpn;
5375 u32 cqn = irq_work->cqn;
5376
5377 switch (irq_work->event_type) {
5378 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5379 ibdev_info(ibdev, "Path migrated succeeded.\n");
5380 break;
5381 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5382 ibdev_warn(ibdev, "Path migration failed.\n");
5383 break;
5384 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5385 break;
5386 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5387 ibdev_warn(ibdev, "Send queue drained.\n");
5388 break;
5389 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5390 ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n",
5391 qpn, irq_work->sub_type);
5392 break;
5393 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5394 ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n",
5395 qpn);
5396 break;
5397 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5398 ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n",
5399 qpn, irq_work->sub_type);
5400 break;
5401 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5402 ibdev_warn(ibdev, "SRQ limit reach.\n");
5403 break;
5404 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5405 ibdev_warn(ibdev, "SRQ last wqe reach.\n");
5406 break;
5407 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5408 ibdev_err(ibdev, "SRQ catas error.\n");
5409 break;
5410 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5411 ibdev_err(ibdev, "CQ 0x%x access err.\n", cqn);
5412 break;
5413 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5414 ibdev_warn(ibdev, "CQ 0x%x overflow\n", cqn);
5415 break;
5416 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5417 ibdev_warn(ibdev, "DB overflow.\n");
5418 break;
5419 case HNS_ROCE_EVENT_TYPE_FLR:
5420 ibdev_warn(ibdev, "Function level reset.\n");
5421 break;
5422 default:
5423 break;
5424 }
5425
5426 kfree(irq_work);
5427 }
5428
hns_roce_v2_init_irq_work(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,u32 qpn,u32 cqn)5429 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
5430 struct hns_roce_eq *eq,
5431 u32 qpn, u32 cqn)
5432 {
5433 struct hns_roce_work *irq_work;
5434
5435 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
5436 if (!irq_work)
5437 return;
5438
5439 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle);
5440 irq_work->hr_dev = hr_dev;
5441 irq_work->qpn = qpn;
5442 irq_work->cqn = cqn;
5443 irq_work->event_type = eq->event_type;
5444 irq_work->sub_type = eq->sub_type;
5445 queue_work(hr_dev->irq_workq, &(irq_work->work));
5446 }
5447
set_eq_cons_index_v2(struct hns_roce_eq * eq)5448 static void set_eq_cons_index_v2(struct hns_roce_eq *eq)
5449 {
5450 struct hns_roce_dev *hr_dev = eq->hr_dev;
5451 __le32 doorbell[2] = {};
5452
5453 if (eq->type_flag == HNS_ROCE_AEQ) {
5454 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
5455 HNS_ROCE_V2_EQ_DB_CMD_S,
5456 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5457 HNS_ROCE_EQ_DB_CMD_AEQ :
5458 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
5459 } else {
5460 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M,
5461 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn);
5462
5463 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
5464 HNS_ROCE_V2_EQ_DB_CMD_S,
5465 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5466 HNS_ROCE_EQ_DB_CMD_CEQ :
5467 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
5468 }
5469
5470 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M,
5471 HNS_ROCE_V2_EQ_DB_PARA_S,
5472 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M));
5473
5474 hns_roce_write64(hr_dev, doorbell, eq->doorbell);
5475 }
5476
next_aeqe_sw_v2(struct hns_roce_eq * eq)5477 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
5478 {
5479 struct hns_roce_aeqe *aeqe;
5480
5481 aeqe = hns_roce_buf_offset(eq->mtr.kmem,
5482 (eq->cons_index & (eq->entries - 1)) *
5483 eq->eqe_size);
5484
5485 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
5486 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
5487 }
5488
hns_roce_v2_aeq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)5489 static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
5490 struct hns_roce_eq *eq)
5491 {
5492 struct device *dev = hr_dev->dev;
5493 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
5494 int aeqe_found = 0;
5495 int event_type;
5496 int sub_type;
5497 u32 srqn;
5498 u32 qpn;
5499 u32 cqn;
5500
5501 while (aeqe) {
5502 /* Make sure we read AEQ entry after we have checked the
5503 * ownership bit
5504 */
5505 dma_rmb();
5506
5507 event_type = roce_get_field(aeqe->asyn,
5508 HNS_ROCE_V2_AEQE_EVENT_TYPE_M,
5509 HNS_ROCE_V2_AEQE_EVENT_TYPE_S);
5510 sub_type = roce_get_field(aeqe->asyn,
5511 HNS_ROCE_V2_AEQE_SUB_TYPE_M,
5512 HNS_ROCE_V2_AEQE_SUB_TYPE_S);
5513 qpn = roce_get_field(aeqe->event.qp_event.qp,
5514 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5515 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
5516 cqn = roce_get_field(aeqe->event.cq_event.cq,
5517 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5518 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
5519 srqn = roce_get_field(aeqe->event.srq_event.srq,
5520 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5521 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
5522
5523 switch (event_type) {
5524 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5525 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5526 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5527 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5528 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5529 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5530 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5531 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5532 hns_roce_qp_event(hr_dev, qpn, event_type);
5533 break;
5534 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5535 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5536 hns_roce_srq_event(hr_dev, srqn, event_type);
5537 break;
5538 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5539 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5540 hns_roce_cq_event(hr_dev, cqn, event_type);
5541 break;
5542 case HNS_ROCE_EVENT_TYPE_MB:
5543 hns_roce_cmd_event(hr_dev,
5544 le16_to_cpu(aeqe->event.cmd.token),
5545 aeqe->event.cmd.status,
5546 le64_to_cpu(aeqe->event.cmd.out_param));
5547 break;
5548 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5549 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
5550 case HNS_ROCE_EVENT_TYPE_FLR:
5551 break;
5552 default:
5553 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n",
5554 event_type, eq->eqn, eq->cons_index);
5555 break;
5556 }
5557
5558 eq->event_type = event_type;
5559 eq->sub_type = sub_type;
5560 ++eq->cons_index;
5561 aeqe_found = 1;
5562
5563 if (eq->cons_index > (2 * eq->entries - 1))
5564 eq->cons_index = 0;
5565
5566 hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn);
5567
5568 aeqe = next_aeqe_sw_v2(eq);
5569 }
5570
5571 set_eq_cons_index_v2(eq);
5572 return aeqe_found;
5573 }
5574
next_ceqe_sw_v2(struct hns_roce_eq * eq)5575 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
5576 {
5577 struct hns_roce_ceqe *ceqe;
5578
5579 ceqe = hns_roce_buf_offset(eq->mtr.kmem,
5580 (eq->cons_index & (eq->entries - 1)) *
5581 eq->eqe_size);
5582
5583 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
5584 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
5585 }
5586
hns_roce_v2_ceq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)5587 static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
5588 struct hns_roce_eq *eq)
5589 {
5590 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
5591 int ceqe_found = 0;
5592 u32 cqn;
5593
5594 while (ceqe) {
5595 /* Make sure we read CEQ entry after we have checked the
5596 * ownership bit
5597 */
5598 dma_rmb();
5599
5600 cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M,
5601 HNS_ROCE_V2_CEQE_COMP_CQN_S);
5602
5603 hns_roce_cq_completion(hr_dev, cqn);
5604
5605 ++eq->cons_index;
5606 ceqe_found = 1;
5607
5608 if (eq->cons_index > (EQ_DEPTH_COEFF * eq->entries - 1))
5609 eq->cons_index = 0;
5610
5611 ceqe = next_ceqe_sw_v2(eq);
5612 }
5613
5614 set_eq_cons_index_v2(eq);
5615
5616 return ceqe_found;
5617 }
5618
hns_roce_v2_msix_interrupt_eq(int irq,void * eq_ptr)5619 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
5620 {
5621 struct hns_roce_eq *eq = eq_ptr;
5622 struct hns_roce_dev *hr_dev = eq->hr_dev;
5623 int int_work;
5624
5625 if (eq->type_flag == HNS_ROCE_CEQ)
5626 /* Completion event interrupt */
5627 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
5628 else
5629 /* Asychronous event interrupt */
5630 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
5631
5632 return IRQ_RETVAL(int_work);
5633 }
5634
hns_roce_v2_msix_interrupt_abn(int irq,void * dev_id)5635 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
5636 {
5637 struct hns_roce_dev *hr_dev = dev_id;
5638 struct device *dev = hr_dev->dev;
5639 int int_work = 0;
5640 u32 int_st;
5641 u32 int_en;
5642
5643 /* Abnormal interrupt */
5644 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
5645 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
5646
5647 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
5648 struct pci_dev *pdev = hr_dev->pci_dev;
5649 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5650 const struct hnae3_ae_ops *ops = ae_dev->ops;
5651
5652 dev_err(dev, "AEQ overflow!\n");
5653
5654 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG,
5655 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S);
5656
5657 /* Set reset level for reset_event() */
5658 if (ops->set_default_reset_request)
5659 ops->set_default_reset_request(ae_dev,
5660 HNAE3_FUNC_RESET);
5661 if (ops->reset_event)
5662 ops->reset_event(pdev, NULL);
5663
5664 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
5665 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5666
5667 int_work = 1;
5668 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) {
5669 dev_err(dev, "BUS ERR!\n");
5670
5671 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S;
5672 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5673
5674 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
5675 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5676
5677 int_work = 1;
5678 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) {
5679 dev_err(dev, "OTHER ERR!\n");
5680
5681 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S;
5682 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5683
5684 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
5685 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5686
5687 int_work = 1;
5688 } else
5689 dev_err(dev, "There is no abnormal irq found!\n");
5690
5691 return IRQ_RETVAL(int_work);
5692 }
5693
hns_roce_v2_int_mask_enable(struct hns_roce_dev * hr_dev,int eq_num,int enable_flag)5694 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
5695 int eq_num, int enable_flag)
5696 {
5697 int i;
5698
5699 if (enable_flag == EQ_ENABLE) {
5700 for (i = 0; i < eq_num; i++)
5701 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5702 i * EQ_REG_OFFSET,
5703 HNS_ROCE_V2_VF_EVENT_INT_EN_M);
5704
5705 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
5706 HNS_ROCE_V2_VF_ABN_INT_EN_M);
5707 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
5708 HNS_ROCE_V2_VF_ABN_INT_CFG_M);
5709 } else {
5710 for (i = 0; i < eq_num; i++)
5711 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5712 i * EQ_REG_OFFSET,
5713 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0);
5714
5715 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
5716 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0);
5717 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
5718 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0);
5719 }
5720 }
5721
hns_roce_v2_destroy_eqc(struct hns_roce_dev * hr_dev,int eqn)5722 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
5723 {
5724 struct device *dev = hr_dev->dev;
5725 int ret;
5726
5727 if (eqn < hr_dev->caps.num_comp_vectors)
5728 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5729 0, HNS_ROCE_CMD_DESTROY_CEQC,
5730 HNS_ROCE_CMD_TIMEOUT_MSECS);
5731 else
5732 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5733 0, HNS_ROCE_CMD_DESTROY_AEQC,
5734 HNS_ROCE_CMD_TIMEOUT_MSECS);
5735 if (ret)
5736 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
5737 }
5738
free_eq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)5739 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
5740 {
5741 hns_roce_mtr_destroy(hr_dev, &eq->mtr);
5742 }
5743
config_eqc(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,void * mb_buf)5744 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
5745 void *mb_buf)
5746 {
5747 u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
5748 struct hns_roce_eq_context *eqc;
5749 u64 bt_ba = 0;
5750 int count;
5751
5752 eqc = mb_buf;
5753 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
5754
5755 /* init eqc */
5756 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
5757 eq->cons_index = 0;
5758 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
5759 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
5760 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
5761 eq->shift = ilog2((unsigned int)eq->entries);
5762
5763 /* if not multi-hop, eqe buffer only use one trunk */
5764 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT,
5765 &bt_ba);
5766 if (count < 1) {
5767 dev_err(hr_dev->dev, "failed to find EQE mtr\n");
5768 return -ENOBUFS;
5769 }
5770
5771 /* set eqc state */
5772 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQ_ST_M, HNS_ROCE_EQC_EQ_ST_S,
5773 HNS_ROCE_V2_EQ_STATE_VALID);
5774
5775 /* set eqe hop num */
5776 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_HOP_NUM_M,
5777 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num);
5778
5779 /* set eqc over_ignore */
5780 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_OVER_IGNORE_M,
5781 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore);
5782
5783 /* set eqc coalesce */
5784 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_COALESCE_M,
5785 HNS_ROCE_EQC_COALESCE_S, eq->coalesce);
5786
5787 /* set eqc arm_state */
5788 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_ARM_ST_M,
5789 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st);
5790
5791 /* set eqn */
5792 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQN_M, HNS_ROCE_EQC_EQN_S,
5793 eq->eqn);
5794
5795 /* set eqe_cnt */
5796 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQE_CNT_M,
5797 HNS_ROCE_EQC_EQE_CNT_S, HNS_ROCE_EQ_INIT_EQE_CNT);
5798
5799 /* set eqe_ba_pg_sz */
5800 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BA_PG_SZ_M,
5801 HNS_ROCE_EQC_BA_PG_SZ_S,
5802 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
5803
5804 /* set eqe_buf_pg_sz */
5805 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BUF_PG_SZ_M,
5806 HNS_ROCE_EQC_BUF_PG_SZ_S,
5807 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
5808
5809 /* set eq_producer_idx */
5810 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_PROD_INDX_M,
5811 HNS_ROCE_EQC_PROD_INDX_S, HNS_ROCE_EQ_INIT_PROD_IDX);
5812
5813 /* set eq_max_cnt */
5814 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_MAX_CNT_M,
5815 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt);
5816
5817 /* set eq_period */
5818 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_PERIOD_M,
5819 HNS_ROCE_EQC_PERIOD_S, eq->eq_period);
5820
5821 /* set eqe_report_timer */
5822 roce_set_field(eqc->eqe_report_timer, HNS_ROCE_EQC_REPORT_TIMER_M,
5823 HNS_ROCE_EQC_REPORT_TIMER_S,
5824 HNS_ROCE_EQ_INIT_REPORT_TIMER);
5825
5826 /* set bt_ba [34:3] */
5827 roce_set_field(eqc->eqe_ba0, HNS_ROCE_EQC_EQE_BA_L_M,
5828 HNS_ROCE_EQC_EQE_BA_L_S, bt_ba >> 3);
5829
5830 /* set bt_ba [64:35] */
5831 roce_set_field(eqc->eqe_ba1, HNS_ROCE_EQC_EQE_BA_H_M,
5832 HNS_ROCE_EQC_EQE_BA_H_S, bt_ba >> 35);
5833
5834 /* set eq shift */
5835 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_SHIFT_M, HNS_ROCE_EQC_SHIFT_S,
5836 eq->shift);
5837
5838 /* set eq MSI_IDX */
5839 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_MSI_INDX_M,
5840 HNS_ROCE_EQC_MSI_INDX_S, HNS_ROCE_EQ_INIT_MSI_IDX);
5841
5842 /* set cur_eqe_ba [27:12] */
5843 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_CUR_EQE_BA_L_M,
5844 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eqe_ba[0] >> 12);
5845
5846 /* set cur_eqe_ba [59:28] */
5847 roce_set_field(eqc->byte_32, HNS_ROCE_EQC_CUR_EQE_BA_M_M,
5848 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eqe_ba[0] >> 28);
5849
5850 /* set cur_eqe_ba [63:60] */
5851 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CUR_EQE_BA_H_M,
5852 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eqe_ba[0] >> 60);
5853
5854 /* set eq consumer idx */
5855 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M,
5856 HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX);
5857
5858 roce_set_field(eqc->byte_40, HNS_ROCE_EQC_NXT_EQE_BA_L_M,
5859 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12);
5860
5861 roce_set_field(eqc->byte_44, HNS_ROCE_EQC_NXT_EQE_BA_H_M,
5862 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44);
5863
5864 roce_set_field(eqc->byte_44, HNS_ROCE_EQC_EQE_SIZE_M,
5865 HNS_ROCE_EQC_EQE_SIZE_S,
5866 eq->eqe_size == HNS_ROCE_V3_EQE_SIZE ? 1 : 0);
5867
5868 return 0;
5869 }
5870
alloc_eq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)5871 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
5872 {
5873 struct hns_roce_buf_attr buf_attr = {};
5874 int err;
5875
5876 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
5877 eq->hop_num = 0;
5878 else
5879 eq->hop_num = hr_dev->caps.eqe_hop_num;
5880
5881 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + HNS_HW_PAGE_SHIFT;
5882 buf_attr.region[0].size = eq->entries * eq->eqe_size;
5883 buf_attr.region[0].hopnum = eq->hop_num;
5884 buf_attr.region_count = 1;
5885 buf_attr.fixed_page = true;
5886
5887 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
5888 hr_dev->caps.eqe_ba_pg_sz +
5889 HNS_HW_PAGE_SHIFT, NULL, 0);
5890 if (err)
5891 dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err);
5892
5893 return err;
5894 }
5895
hns_roce_v2_create_eq(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,unsigned int eq_cmd)5896 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
5897 struct hns_roce_eq *eq,
5898 unsigned int eq_cmd)
5899 {
5900 struct hns_roce_cmd_mailbox *mailbox;
5901 int ret;
5902
5903 /* Allocate mailbox memory */
5904 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5905 if (IS_ERR_OR_NULL(mailbox))
5906 return -ENOMEM;
5907
5908 ret = alloc_eq_buf(hr_dev, eq);
5909 if (ret)
5910 goto free_cmd_mbox;
5911
5912 ret = config_eqc(hr_dev, eq, mailbox->buf);
5913 if (ret)
5914 goto err_cmd_mbox;
5915
5916 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0,
5917 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS);
5918 if (ret) {
5919 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
5920 goto err_cmd_mbox;
5921 }
5922
5923 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5924
5925 return 0;
5926
5927 err_cmd_mbox:
5928 free_eq_buf(hr_dev, eq);
5929
5930 free_cmd_mbox:
5931 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5932
5933 return ret;
5934 }
5935
__hns_roce_request_irq(struct hns_roce_dev * hr_dev,int irq_num,int comp_num,int aeq_num,int other_num)5936 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
5937 int comp_num, int aeq_num, int other_num)
5938 {
5939 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5940 int i, j;
5941 int ret;
5942
5943 for (i = 0; i < irq_num; i++) {
5944 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
5945 GFP_KERNEL);
5946 if (!hr_dev->irq_names[i]) {
5947 ret = -ENOMEM;
5948 goto err_kzalloc_failed;
5949 }
5950 }
5951
5952 /* irq contains: abnormal + AEQ + CEQ */
5953 for (j = 0; j < other_num; j++)
5954 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5955 "hns-abn-%d", j);
5956
5957 for (j = other_num; j < (other_num + aeq_num); j++)
5958 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5959 "hns-aeq-%d", j - other_num);
5960
5961 for (j = (other_num + aeq_num); j < irq_num; j++)
5962 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5963 "hns-ceq-%d", j - other_num - aeq_num);
5964
5965 for (j = 0; j < irq_num; j++) {
5966 if (j < other_num)
5967 ret = request_irq(hr_dev->irq[j],
5968 hns_roce_v2_msix_interrupt_abn,
5969 0, hr_dev->irq_names[j], hr_dev);
5970
5971 else if (j < (other_num + comp_num))
5972 ret = request_irq(eq_table->eq[j - other_num].irq,
5973 hns_roce_v2_msix_interrupt_eq,
5974 0, hr_dev->irq_names[j + aeq_num],
5975 &eq_table->eq[j - other_num]);
5976 else
5977 ret = request_irq(eq_table->eq[j - other_num].irq,
5978 hns_roce_v2_msix_interrupt_eq,
5979 0, hr_dev->irq_names[j - comp_num],
5980 &eq_table->eq[j - other_num]);
5981 if (ret) {
5982 dev_err(hr_dev->dev, "Request irq error!\n");
5983 goto err_request_failed;
5984 }
5985 }
5986
5987 return 0;
5988
5989 err_request_failed:
5990 for (j -= 1; j >= 0; j--)
5991 if (j < other_num)
5992 free_irq(hr_dev->irq[j], hr_dev);
5993 else
5994 free_irq(eq_table->eq[j - other_num].irq,
5995 &eq_table->eq[j - other_num]);
5996
5997 err_kzalloc_failed:
5998 for (i -= 1; i >= 0; i--)
5999 kfree(hr_dev->irq_names[i]);
6000
6001 return ret;
6002 }
6003
__hns_roce_free_irq(struct hns_roce_dev * hr_dev)6004 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
6005 {
6006 int irq_num;
6007 int eq_num;
6008 int i;
6009
6010 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6011 irq_num = eq_num + hr_dev->caps.num_other_vectors;
6012
6013 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
6014 free_irq(hr_dev->irq[i], hr_dev);
6015
6016 for (i = 0; i < eq_num; i++)
6017 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
6018
6019 for (i = 0; i < irq_num; i++)
6020 kfree(hr_dev->irq_names[i]);
6021 }
6022
hns_roce_v2_init_eq_table(struct hns_roce_dev * hr_dev)6023 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
6024 {
6025 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6026 struct device *dev = hr_dev->dev;
6027 struct hns_roce_eq *eq;
6028 unsigned int eq_cmd;
6029 int irq_num;
6030 int eq_num;
6031 int other_num;
6032 int comp_num;
6033 int aeq_num;
6034 int i;
6035 int ret;
6036
6037 other_num = hr_dev->caps.num_other_vectors;
6038 comp_num = hr_dev->caps.num_comp_vectors;
6039 aeq_num = hr_dev->caps.num_aeq_vectors;
6040
6041 eq_num = comp_num + aeq_num;
6042 irq_num = eq_num + other_num;
6043
6044 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
6045 if (!eq_table->eq)
6046 return -ENOMEM;
6047
6048 /* create eq */
6049 for (i = 0; i < eq_num; i++) {
6050 eq = &eq_table->eq[i];
6051 eq->hr_dev = hr_dev;
6052 eq->eqn = i;
6053 if (i < comp_num) {
6054 /* CEQ */
6055 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
6056 eq->type_flag = HNS_ROCE_CEQ;
6057 eq->entries = hr_dev->caps.ceqe_depth;
6058 eq->eqe_size = hr_dev->caps.ceqe_size;
6059 eq->irq = hr_dev->irq[i + other_num + aeq_num];
6060 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
6061 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
6062 } else {
6063 /* AEQ */
6064 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
6065 eq->type_flag = HNS_ROCE_AEQ;
6066 eq->entries = hr_dev->caps.aeqe_depth;
6067 eq->eqe_size = hr_dev->caps.aeqe_size;
6068 eq->irq = hr_dev->irq[i - comp_num + other_num];
6069 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
6070 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
6071 }
6072
6073 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
6074 if (ret) {
6075 dev_err(dev, "eq create failed.\n");
6076 goto err_create_eq_fail;
6077 }
6078 }
6079
6080 /* enable irq */
6081 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
6082
6083 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num,
6084 aeq_num, other_num);
6085 if (ret) {
6086 dev_err(dev, "Request irq failed.\n");
6087 goto err_request_irq_fail;
6088 }
6089
6090 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
6091 if (!hr_dev->irq_workq) {
6092 dev_err(dev, "Create irq workqueue failed!\n");
6093 ret = -ENOMEM;
6094 goto err_create_wq_fail;
6095 }
6096
6097 return 0;
6098
6099 err_create_wq_fail:
6100 __hns_roce_free_irq(hr_dev);
6101
6102 err_request_irq_fail:
6103 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
6104
6105 err_create_eq_fail:
6106 for (i -= 1; i >= 0; i--)
6107 free_eq_buf(hr_dev, &eq_table->eq[i]);
6108 kfree(eq_table->eq);
6109
6110 return ret;
6111 }
6112
hns_roce_v2_cleanup_eq_table(struct hns_roce_dev * hr_dev)6113 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
6114 {
6115 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6116 int eq_num;
6117 int i;
6118
6119 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6120
6121 /* Disable irq */
6122 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
6123
6124 __hns_roce_free_irq(hr_dev);
6125
6126 for (i = 0; i < eq_num; i++) {
6127 hns_roce_v2_destroy_eqc(hr_dev, i);
6128
6129 free_eq_buf(hr_dev, &eq_table->eq[i]);
6130 }
6131
6132 kfree(eq_table->eq);
6133
6134 flush_workqueue(hr_dev->irq_workq);
6135 destroy_workqueue(hr_dev->irq_workq);
6136 }
6137
6138 static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = {
6139 .query_cqc_info = hns_roce_v2_query_cqc_info,
6140 };
6141
6142 static const struct ib_device_ops hns_roce_v2_dev_ops = {
6143 .destroy_qp = hns_roce_v2_destroy_qp,
6144 .modify_cq = hns_roce_v2_modify_cq,
6145 .poll_cq = hns_roce_v2_poll_cq,
6146 .post_recv = hns_roce_v2_post_recv,
6147 .post_send = hns_roce_v2_post_send,
6148 .query_qp = hns_roce_v2_query_qp,
6149 .req_notify_cq = hns_roce_v2_req_notify_cq,
6150 };
6151
6152 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
6153 .modify_srq = hns_roce_v2_modify_srq,
6154 .post_srq_recv = hns_roce_v2_post_srq_recv,
6155 .query_srq = hns_roce_v2_query_srq,
6156 };
6157
6158 static const struct hns_roce_hw hns_roce_hw_v2 = {
6159 .cmq_init = hns_roce_v2_cmq_init,
6160 .cmq_exit = hns_roce_v2_cmq_exit,
6161 .hw_profile = hns_roce_v2_profile,
6162 .hw_init = hns_roce_v2_init,
6163 .hw_exit = hns_roce_v2_exit,
6164 .post_mbox = hns_roce_v2_post_mbox,
6165 .chk_mbox = hns_roce_v2_chk_mbox,
6166 .rst_prc_mbox = hns_roce_v2_rst_process_cmd,
6167 .set_gid = hns_roce_v2_set_gid,
6168 .set_mac = hns_roce_v2_set_mac,
6169 .write_mtpt = hns_roce_v2_write_mtpt,
6170 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
6171 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
6172 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
6173 .write_cqc = hns_roce_v2_write_cqc,
6174 .set_hem = hns_roce_v2_set_hem,
6175 .clear_hem = hns_roce_v2_clear_hem,
6176 .modify_qp = hns_roce_v2_modify_qp,
6177 .query_qp = hns_roce_v2_query_qp,
6178 .destroy_qp = hns_roce_v2_destroy_qp,
6179 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
6180 .modify_cq = hns_roce_v2_modify_cq,
6181 .post_send = hns_roce_v2_post_send,
6182 .post_recv = hns_roce_v2_post_recv,
6183 .req_notify_cq = hns_roce_v2_req_notify_cq,
6184 .poll_cq = hns_roce_v2_poll_cq,
6185 .init_eq = hns_roce_v2_init_eq_table,
6186 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
6187 .write_srqc = hns_roce_v2_write_srqc,
6188 .modify_srq = hns_roce_v2_modify_srq,
6189 .query_srq = hns_roce_v2_query_srq,
6190 .post_srq_recv = hns_roce_v2_post_srq_recv,
6191 .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
6192 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
6193 };
6194
6195 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
6196 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
6197 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
6198 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
6199 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
6200 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
6201 /* required last entry */
6202 {0, }
6203 };
6204
6205 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
6206
hns_roce_hw_v2_get_cfg(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)6207 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
6208 struct hnae3_handle *handle)
6209 {
6210 struct hns_roce_v2_priv *priv = hr_dev->priv;
6211 int i;
6212
6213 hr_dev->pci_dev = handle->pdev;
6214 hr_dev->dev = &handle->pdev->dev;
6215 hr_dev->hw = &hns_roce_hw_v2;
6216 hr_dev->dfx = &hns_roce_dfx_hw_v2;
6217 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
6218 hr_dev->odb_offset = hr_dev->sdb_offset;
6219
6220 /* Get info from NIC driver. */
6221 hr_dev->reg_base = handle->rinfo.roce_io_base;
6222 hr_dev->caps.num_ports = 1;
6223 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
6224 hr_dev->iboe.phy_port[0] = 0;
6225
6226 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
6227 hr_dev->iboe.netdevs[0]->dev_addr);
6228
6229 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++)
6230 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6231 i + handle->rinfo.base_vector);
6232
6233 /* cmd issue mode: 0 is poll, 1 is event */
6234 hr_dev->cmd_mod = 1;
6235 hr_dev->loop_idc = 0;
6236
6237 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6238 priv->handle = handle;
6239 }
6240
__hns_roce_hw_v2_init_instance(struct hnae3_handle * handle)6241 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6242 {
6243 struct hns_roce_dev *hr_dev;
6244 int ret;
6245
6246 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
6247 if (!hr_dev)
6248 return -ENOMEM;
6249
6250 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6251 if (!hr_dev->priv) {
6252 ret = -ENOMEM;
6253 goto error_failed_kzalloc;
6254 }
6255
6256 hns_roce_hw_v2_get_cfg(hr_dev, handle);
6257
6258 ret = hns_roce_init(hr_dev);
6259 if (ret) {
6260 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6261 goto error_failed_get_cfg;
6262 }
6263
6264 handle->priv = hr_dev;
6265
6266 return 0;
6267
6268 error_failed_get_cfg:
6269 kfree(hr_dev->priv);
6270
6271 error_failed_kzalloc:
6272 ib_dealloc_device(&hr_dev->ib_dev);
6273
6274 return ret;
6275 }
6276
__hns_roce_hw_v2_uninit_instance(struct hnae3_handle * handle,bool reset)6277 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6278 bool reset)
6279 {
6280 struct hns_roce_dev *hr_dev = handle->priv;
6281
6282 if (!hr_dev)
6283 return;
6284
6285 handle->priv = NULL;
6286
6287 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
6288 hns_roce_handle_device_err(hr_dev);
6289
6290 hns_roce_exit(hr_dev);
6291 kfree(hr_dev->priv);
6292 ib_dealloc_device(&hr_dev->ib_dev);
6293 }
6294
hns_roce_hw_v2_init_instance(struct hnae3_handle * handle)6295 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6296 {
6297 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
6298 const struct pci_device_id *id;
6299 struct device *dev = &handle->pdev->dev;
6300 int ret;
6301
6302 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6303
6304 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6305 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6306 goto reset_chk_err;
6307 }
6308
6309 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
6310 if (!id)
6311 return 0;
6312
6313 ret = __hns_roce_hw_v2_init_instance(handle);
6314 if (ret) {
6315 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6316 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6317 if (ops->ae_dev_resetting(handle) ||
6318 ops->get_hw_reset_stat(handle))
6319 goto reset_chk_err;
6320 else
6321 return ret;
6322 }
6323
6324 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6325
6326
6327 return 0;
6328
6329 reset_chk_err:
6330 dev_err(dev, "Device is busy in resetting state.\n"
6331 "please retry later.\n");
6332
6333 return -EBUSY;
6334 }
6335
hns_roce_hw_v2_uninit_instance(struct hnae3_handle * handle,bool reset)6336 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6337 bool reset)
6338 {
6339 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6340 return;
6341
6342 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6343
6344 __hns_roce_hw_v2_uninit_instance(handle, reset);
6345
6346 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6347 }
hns_roce_hw_v2_reset_notify_down(struct hnae3_handle * handle)6348 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6349 {
6350 struct hns_roce_dev *hr_dev;
6351
6352 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6353 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6354 return 0;
6355 }
6356
6357 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6358 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6359
6360 hr_dev = handle->priv;
6361 if (!hr_dev)
6362 return 0;
6363
6364 hr_dev->active = false;
6365 hr_dev->dis_db = true;
6366 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
6367
6368 return 0;
6369 }
6370
hns_roce_hw_v2_reset_notify_init(struct hnae3_handle * handle)6371 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6372 {
6373 struct device *dev = &handle->pdev->dev;
6374 int ret;
6375
6376 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6377 &handle->rinfo.state)) {
6378 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6379 return 0;
6380 }
6381
6382 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6383
6384 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6385 ret = __hns_roce_hw_v2_init_instance(handle);
6386 if (ret) {
6387 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6388 * callback function, RoCE Engine reinitialize. If RoCE reinit
6389 * failed, we should inform NIC driver.
6390 */
6391 handle->priv = NULL;
6392 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6393 } else {
6394 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6395 dev_info(dev, "Reset done, RoCE client reinit finished.\n");
6396 }
6397
6398 return ret;
6399 }
6400
hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle * handle)6401 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6402 {
6403 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6404 return 0;
6405
6406 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6407 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
6408 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
6409 __hns_roce_hw_v2_uninit_instance(handle, false);
6410
6411 return 0;
6412 }
6413
hns_roce_hw_v2_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)6414 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6415 enum hnae3_reset_notify_type type)
6416 {
6417 int ret = 0;
6418
6419 switch (type) {
6420 case HNAE3_DOWN_CLIENT:
6421 ret = hns_roce_hw_v2_reset_notify_down(handle);
6422 break;
6423 case HNAE3_INIT_CLIENT:
6424 ret = hns_roce_hw_v2_reset_notify_init(handle);
6425 break;
6426 case HNAE3_UNINIT_CLIENT:
6427 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
6428 break;
6429 default:
6430 break;
6431 }
6432
6433 return ret;
6434 }
6435
6436 static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
6437 .init_instance = hns_roce_hw_v2_init_instance,
6438 .uninit_instance = hns_roce_hw_v2_uninit_instance,
6439 .reset_notify = hns_roce_hw_v2_reset_notify,
6440 };
6441
6442 static struct hnae3_client hns_roce_hw_v2_client = {
6443 .name = "hns_roce_hw_v2",
6444 .type = HNAE3_CLIENT_ROCE,
6445 .ops = &hns_roce_hw_v2_ops,
6446 };
6447
hns_roce_hw_v2_init(void)6448 static int __init hns_roce_hw_v2_init(void)
6449 {
6450 return hnae3_register_client(&hns_roce_hw_v2_client);
6451 }
6452
hns_roce_hw_v2_exit(void)6453 static void __exit hns_roce_hw_v2_exit(void)
6454 {
6455 hnae3_unregister_client(&hns_roce_hw_v2_client);
6456 }
6457
6458 module_init(hns_roce_hw_v2_init);
6459 module_exit(hns_roce_hw_v2_exit);
6460
6461 MODULE_LICENSE("Dual BSD/GPL");
6462 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
6463 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
6464 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
6465 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
6466