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Searched refs:clk_regs (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/radeon/
Drv740_dpm.c125 u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; in rv740_populate_sclk_value()
126 u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2; in rv740_populate_sclk_value()
127 u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3; in rv740_populate_sclk_value()
128 u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum; in rv740_populate_sclk_value()
129 u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2; in rv740_populate_sclk_value()
191 u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl; in rv740_populate_mclk_value()
192 u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2; in rv740_populate_mclk_value()
193 u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl; in rv740_populate_mclk_value()
194 u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2; in rv740_populate_mclk_value()
195 u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl; in rv740_populate_mclk_value()
[all …]
Drv730_dpm.c45 u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl; in rv730_populate_sclk_value()
46 u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2; in rv730_populate_sclk_value()
47 u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3; in rv730_populate_sclk_value()
48 u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum; in rv730_populate_sclk_value()
49 u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2; in rv730_populate_sclk_value()
123 u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl; in rv730_populate_mclk_value()
124 u32 dll_cntl = pi->clk_regs.rv730.dll_cntl; in rv730_populate_mclk_value()
125 u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl; in rv730_populate_mclk_value()
126 u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2; in rv730_populate_mclk_value()
127 u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3; in rv730_populate_mclk_value()
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Drv770_dpm.c392 pi->clk_regs.rv770.mpll_ad_func_cntl; in rv770_populate_mclk_value()
394 pi->clk_regs.rv770.mpll_ad_func_cntl_2; in rv770_populate_mclk_value()
396 pi->clk_regs.rv770.mpll_dq_func_cntl; in rv770_populate_mclk_value()
398 pi->clk_regs.rv770.mpll_dq_func_cntl_2; in rv770_populate_mclk_value()
400 pi->clk_regs.rv770.mclk_pwrmgt_cntl; in rv770_populate_mclk_value()
401 u32 dll_cntl = pi->clk_regs.rv770.dll_cntl; in rv770_populate_mclk_value()
490 pi->clk_regs.rv770.cg_spll_func_cntl; in rv770_populate_sclk_value()
492 pi->clk_regs.rv770.cg_spll_func_cntl_2; in rv770_populate_sclk_value()
494 pi->clk_regs.rv770.cg_spll_func_cntl_3; in rv770_populate_sclk_value()
496 pi->clk_regs.rv770.cg_spll_spread_spectrum; in rv770_populate_sclk_value()
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Dcypress_dpm.c482 pi->clk_regs.rv770.mpll_ad_func_cntl; in cypress_populate_mclk_value()
484 pi->clk_regs.rv770.mpll_ad_func_cntl_2; in cypress_populate_mclk_value()
486 pi->clk_regs.rv770.mpll_dq_func_cntl; in cypress_populate_mclk_value()
488 pi->clk_regs.rv770.mpll_dq_func_cntl_2; in cypress_populate_mclk_value()
490 pi->clk_regs.rv770.mclk_pwrmgt_cntl; in cypress_populate_mclk_value()
492 pi->clk_regs.rv770.dll_cntl; in cypress_populate_mclk_value()
493 u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1; in cypress_populate_mclk_value()
494 u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2; in cypress_populate_mclk_value()
1249 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl); in cypress_populate_smc_initial_state()
1251 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2); in cypress_populate_smc_initial_state()
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Drv770_dpm.h96 union r7xx_clock_registers clk_regs; member
/drivers/clk/tegra/
Dclk-tegra124-emc.c73 void __iomem *clk_regs; member
101 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
166 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_get_parent()
251 car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_set_timing()
259 writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC); in emc_set_timing()
492 tegra->clk_regs = base; in tegra_clk_register_emc()
/drivers/clk/samsung/
Dclk-exynos7.c198 .clk_regs = topc_clk_regs,
390 .clk_regs = top0_clk_regs,
572 .clk_regs = top1_clk_regs,
617 .clk_regs = ccore_clk_regs,
684 .clk_regs = peric0_clk_regs,
808 .clk_regs = peric1_clk_regs,
863 .clk_regs = peris_clk_regs,
973 .clk_regs = fsys0_clk_regs,
1104 .clk_regs = fsys1_clk_regs,
1217 .clk_regs = mscl_clk_regs,
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Dclk-exynos5260.c139 .clk_regs = aud_clk_regs,
329 .clk_regs = disp_clk_regs,
393 .clk_regs = egl_clk_regs,
493 .clk_regs = fsys_clk_regs,
584 .clk_regs = g2d_clk_regs,
647 .clk_regs = g3d_clk_regs,
780 .clk_regs = gscl_clk_regs,
899 .clk_regs = isp_clk_regs,
963 .clk_regs = kfc_clk_regs,
1019 .clk_regs = mfc_clk_regs,
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Dclk-exynos5433.c802 .clk_regs = top_clk_regs,
881 .clk_regs = cpif_clk_regs,
1535 .clk_regs = mif_clk_regs,
1734 .clk_regs = peric_clk_regs,
1928 .clk_regs = peris_clk_regs,
2340 .clk_regs = fsys_clk_regs,
2463 .clk_regs = g2d_clk_regs,
2891 .clk_regs = disp_clk_regs,
3061 .clk_regs = aud_clk_regs,
3196 .clk_regs = bus01_clk_regs,
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Dclk.c377 if (cmu->clk_regs) in samsung_cmu_register_one()
379 cmu->clk_regs, cmu->nr_clk_regs, in samsung_cmu_register_one()
Dclk.h306 const unsigned long *clk_regs; member
Dclk-exynos3250.c784 .clk_regs = exynos3250_cmu_clk_regs,
927 .clk_regs = exynos3250_cmu_dmc_clk_regs,
/drivers/thermal/tegra/
Dsoctherm.c334 void __iomem *clk_regs; member
1999 v = readl(ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER); in tegra_soctherm_throttle()
2001 writel(v, ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER); in tegra_soctherm_throttle()
2154 tegra->clk_regs = devm_ioremap_resource(&pdev->dev, res); in tegra_soctherm_probe()
2155 if (IS_ERR(tegra->clk_regs)) { in tegra_soctherm_probe()
2157 return PTR_ERR(tegra->clk_regs); in tegra_soctherm_probe()
/drivers/gpu/drm/amd/pm/powerplay/
Dsi_dpm.h552 union r7xx_clock_registers clk_regs; member