Home
last modified time | relevance | path

Searched refs:core_reg (Results 1 – 15 of 15) sorted by relevance

/drivers/video/backlight/
Dl4f00242t03.c28 struct regulator *core_reg; member
65 ret = regulator_set_voltage(priv->core_reg, 2800000, 2800000); in l4f00242t03_lcd_init()
71 ret = regulator_enable(priv->core_reg); in l4f00242t03_lcd_init()
94 regulator_disable(priv->core_reg); in l4f00242t03_lcd_powerdown()
204 priv->core_reg = devm_regulator_get(&spi->dev, "vcore"); in l4f00242t03_probe()
205 if (IS_ERR(priv->core_reg)) { in l4f00242t03_probe()
208 return PTR_ERR(priv->core_reg); in l4f00242t03_probe()
/drivers/input/touchscreen/
Dmms114.c63 struct regulator *core_reg; member
346 error = regulator_enable(data->core_reg); in mms114_start()
355 regulator_disable(data->core_reg); in mms114_start()
364 regulator_disable(data->core_reg); in mms114_start()
384 error = regulator_disable(data->core_reg); in mms114_stop()
516 data->core_reg = devm_regulator_get(&client->dev, "avdd"); in mms114_probe()
517 if (IS_ERR(data->core_reg)) { in mms114_probe()
518 error = PTR_ERR(data->core_reg); in mms114_probe()
/drivers/clk/rockchip/
Dclk-cpu.c91 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg); in rockchip_cpuclk_recalc_rate()
170 cpuclk->reg_base + reg_data->core_reg); in rockchip_cpuclk_pre_rate_change()
176 cpuclk->reg_base + reg_data->core_reg); in rockchip_cpuclk_pre_rate_change()
214 cpuclk->reg_base + reg_data->core_reg); in rockchip_cpuclk_post_rate_change()
Dclk-rk3188.c148 .core_reg = RK2928_CLKSEL_CON(0),
187 .core_reg = RK2928_CLKSEL_CON(0),
Dclk-rk3368.c157 .core_reg = RK3368_CLKSEL_CON(0),
167 .core_reg = RK3368_CLKSEL_CON(2),
Dclk-rk3036.c105 .core_reg = RK2928_CLKSEL_CON(0),
Dclk-rk3128.c120 .core_reg = RK2928_CLKSEL_CON(0),
Dclk-rk3228.c122 .core_reg = RK2928_CLKSEL_CON(0),
Dclk-rk3399.c294 .core_reg = RK3399_CLKSEL_CON(0),
304 .core_reg = RK3399_CLKSEL_CON(2),
Dclk-rk3328.c133 .core_reg = RK3328_CLKSEL_CON(0),
Dclk-rv1108.c109 .core_reg = RV1108_CLKSEL_CON(0),
Dclk.h342 int core_reg; member
Dclk-rk3288.c182 .core_reg = RK3288_CLKSEL_CON(0),
Dclk-px30.c127 .core_reg = PX30_CLKSEL_CON(0),
Dclk-rk3308.c112 .core_reg = RK3308_CLKSEL_CON(0),